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STM32L152CCU6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32l152ccu6factory-2.0.0extractor-text
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STM32L152CCU6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32L152CCU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VLCD power_in LCD power supply pin, applicable to STM32L152xC devices only; on STM32L151xC devices it should be connected to VDD.
2 PC13 bidirectional 5 V tolerant (FT) I/O, default function PC13; alternate WKUP2 wakeup, with RTC_TAMP1, RTC_TS and RTC_OUT as additional functions.
3 PC14 bidirectional Standard 3.3 V (TC) I/O, default function PC14; it is configured as OSC32_IN only when the LSE oscillator is on (LSEON in RCC_CSR), and LSE then has priority over the GPIO function.
4 PC15 bidirectional Standard 3.3 V (TC) I/O, default function PC15; it is configured as OSC32_OUT only when the LSE oscillator is on (LSEON in RCC_CSR), and LSE then has priority over the GPIO function.
5 PH0 bidirectional Standard 3.3 V (TC) I/O, default function PH0; it is configured as OSC_IN only when the HSE oscillator is on (HSEON in RCC_CR), and HSE then has priority over the GPIO function.
6 PH1 bidirectional Standard 3.3 V (TC) I/O, default function PH1; it is configured as OSC_OUT only when the HSE oscillator is on (HSEON in RCC_CR), and HSE then has priority over the GPIO function.
7 NRST bidirectional Bidirectional reset pin with an embedded weak pull-up resistor.
8 VSSA power_in Analog ground pin; VSSA (or VREF-) must be tied to ground.
9 VDDA power_in Analog supply pin; VDDA is specified from 1.8 V to 3.6 V for the ADC.
10 PA0 bidirectional 5 V tolerant (FT) I/O, default function PA0 (wakeup pin WKUP1); alternates TIM2_CH1_ETR, TIM5_CH1 and USART2_CTS, with RTC_TAMP2, ADC_IN0 and COMP1_INP as additional functions.
11 PA1 bidirectional 5 V tolerant (FT) I/O; alternates TIM2_CH2, TIM5_CH2, USART2_RTS and LCD_SEG0, with ADC_IN1, COMP1_INP and OPAMP1_VINP as additional functions.
12 PA2 bidirectional 5 V tolerant (FT) I/O; alternates TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX and LCD_SEG1, with ADC_IN2, COMP1_INP and OPAMP1_VINM as additional functions.
13 PA3 bidirectional Standard 3.3 V (TC) I/O; alternates TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX and LCD_SEG2, with ADC_IN3, COMP1_INP and OPAMP1_VOUT as additional functions.
14 PA4 bidirectional Standard 3.3 V (TC) I/O; alternates SPI1_NSS, SPI3_NSS, I2S3_WS, USART2_CK and TIMx_IC1, with ADC_IN4, DAC_OUT1 and COMP1_INP as additional functions.
15 PA5 bidirectional Standard 3.3 V (TC) I/O; alternates TIM2_CH1_ETR, SPI1_SCK and TIMx_IC2, with ADC_IN5, DAC_OUT2 and COMP1_INP as additional functions.
16 PA6 bidirectional 5 V tolerant (FT) I/O; alternates TIM3_CH1, TIM10_CH1, SPI1_MISO and LCD_SEG3, with ADC_IN6, COMP1_INP and OPAMP2_VINP as additional functions.
17 PA7 bidirectional 5 V tolerant (FT) I/O; alternates TIM3_CH2, TIM11_CH1, SPI1_MOSI and LCD_SEG4, with ADC_IN7, COMP1_INP and OPAMP2_VINM as additional functions.
18 PB0 bidirectional Standard 3.3 V (TC) I/O; alternates TIM3_CH3 and LCD_SEG5, with ADC_IN8, COMP1_INP, OPAMP2_VOUT, VLCDRAIL3 and VREF_OUT as additional functions.
19 PB1 bidirectional 5 V tolerant (FT) I/O; alternates TIM3_CH4 and LCD_SEG6, with ADC_IN9, COMP1_INP and VREF_OUT as additional functions.
20 PB2 bidirectional 5 V tolerant (FT) I/O; main function BOOT1, with VLCDRAIL1 and ADCIN0b as additional functions.
21 PB10 bidirectional 5 V tolerant (FT) I/O; alternates TIM2_CH3, I2C2_SCL, USART3_TX and LCD_SEG10.
22 PB11 bidirectional 5 V tolerant (FT) I/O; alternates TIM2_CH4, I2C2_SDA, USART3_RX and LCD_SEG11.
23 VSS_1 power_in Digital ground pin of the device.
24 VDD_1 power_in Digital supply pin of the device; the operating supply range is 1.65 V to 3.6 V.
25 PB12 bidirectional 5 V tolerant (FT) I/O; alternates TIM10_CH1, I2C2_SMBA, SPI2_NSS, I2S2_WS, USART3_CK and LCD_SEG12, with ADC_IN18, COMP1_INP and VLCDRAIL2 as additional functions.
26 PB13 bidirectional 5 V tolerant (FT) I/O; alternates TIM9_CH1, SPI2_SCK, I2S2_CK, USART3_CTS and LCD_SEG13, with ADC_IN19 and COMP1_INP as additional functions.
27 PB14 bidirectional 5 V tolerant (FT) I/O; alternates TIM9_CH2, SPI2_MISO, USART3_RTS and LCD_SEG14, with ADC_IN20 and COMP1_INP as additional functions.
28 PB15 bidirectional 5 V tolerant (FT) I/O; alternates TIM11_CH1, SPI2_MOSI, I2S2_SD and LCD_SEG15, with ADC_IN21, COMP1_INP and RTC_REFIN as additional functions.
29 PA8 bidirectional 5 V tolerant (FT) I/O; alternates USART1_CK, MCO and LCD_COM0.
30 PA9 bidirectional 5 V tolerant (FT) I/O; alternates USART1_TX and LCD_COM1.
31 PA10 bidirectional 5 V tolerant (FT) I/O; alternates USART1_RX and LCD_COM2.
32 PA11 bidirectional 5 V tolerant (FT) I/O; alternates USART1_CTS and SPI1_MISO, with USB_DM as an additional function.
33 PA12 bidirectional 5 V tolerant (FT) I/O; alternates USART1_RTS and SPI1_MOSI, with USB_DP as an additional function.
34 PA13 bidirectional 5 V tolerant (FT) I/O; default function JTMS-SWDIO, the serial wire debug data pin (JTAG TMS shared with SWDAT).
35 VSS_2 power_in Digital ground pin of the device.
36 VDD_2 power_in Digital supply pin of the device; the operating supply range is 1.65 V to 3.6 V.
37 PA14 bidirectional 5 V tolerant (FT) I/O; default function JTCK-SWCLK, the serial wire debug clock pin (JTAG TCK shared with SWCLK).
38 PA15 bidirectional 5 V tolerant (FT) I/O; default function JTDI; alternates TIM2_CH1_ETR, SPI1_NSS, SPI3_NSS, I2S3_WS and LCD_SEG17.
39 PB3 bidirectional 5 V tolerant (FT) I/O; default function JTDO; alternates TIM2_CH2, SPI1_SCK, SPI3_SCK, I2S3_CK and LCD_SEG7, with COMP2_INM as an additional function.
40 PB4 bidirectional 5 V tolerant (FT) I/O; default function NJTRST; alternates TIM3_CH1, SPI1_MISO, SPI3_MISO and LCD_SEG8, with COMP2_INP as an additional function.
41 PB5 bidirectional 5 V tolerant (FT) I/O; alternates TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, I2S3_SD and LCD_SEG9, with COMP2_INP as an additional function.
42 PB6 bidirectional 5 V tolerant (FT) I/O; alternates TIM4_CH1, I2C1_SCL and USART1_TX, with COMP2_INP as an additional function.
43 PB7 bidirectional 5 V tolerant (FT) I/O; alternates TIM4_CH2, I2C1_SDA and USART1_RX, with COMP2_INP and PVD_IN as additional functions.
44 BOOT0 input Dedicated BOOT0 boot-mode selection pin.
45 PB8 bidirectional 5 V tolerant (FT) I/O; alternates TIM4_CH3, TIM10_CH1, I2C1_SCL and LCD_SEG16.
46 PB9 bidirectional 5 V tolerant (FT) I/O; alternates TIM4_CH4, TIM11_CH1, I2C1_SDA and LCD_COM3.
47 VSS_3 power_in Digital ground pin of the device.
48 VDD_3 power_in Digital supply pin of the device; the operating supply range is 1.65 V to 3.6 V.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: STM32L152CCU6
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32l152ccu6-etched.step / stm32l152ccu6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32l152ccu6.step / stm32l152ccu6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (136 pp, sha256 5e6d5674cd06c108, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF