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STM32L152C8U6A
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32L152C8U6A
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32L152C8U6A from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VLCD | power_in | LCD power supply pin, applicable to STM32L152xx devices only; on STM32L151xx devices this pin must be connected to VDD. |
| 2 | PC13-WKUP2 | bidirectional | 5 V tolerant (FT) I/O with default function PC13, also usable as wakeup pin WKUP2 and for RTC_TAMP1/RTC_TS/RTC_OUT. |
| 3 | PC14-OSC32_IN | bidirectional | Standard 3.3 V (TC) I/O that functions as the OSC32_IN LSE oscillator pin only when the LSE is on (LSEON in RCC_CSR), otherwise it is GPIO PC14. |
| 4 | PC15-OSC32_OUT | bidirectional | Standard 3.3 V (TC) I/O that functions as the OSC32_OUT LSE oscillator pin only when the LSE is on (LSEON in RCC_CSR), otherwise it is GPIO PC15. |
| 5 | PH0-OSC_IN | bidirectional | Standard 3.3 V (TC) I/O that functions as the OSC_IN HSE oscillator pin only when the HSE is on (HSEON in RCC_CR), otherwise it is GPIO PH0. |
| 6 | PH1-OSC_OUT | bidirectional | Standard 3.3 V (TC) I/O that functions as the OSC_OUT HSE oscillator pin only when the HSE is on (HSEON in RCC_CR), otherwise it is GPIO PH1. |
| 7 | NRST | bidirectional | Bidirectional active-low reset pin with an embedded weak pull-up resistor. |
| 8 | VSSA | power_in | Analog ground pin, which must be tied to ground. |
| 9 | VDDA | power_in | Analog power supply pin, specified from 1.8 V to 3.6 V. |
| 10 | PA0-WKUP1 | bidirectional | 5 V tolerant (FT) I/O with wakeup function WKUP1, ADC_IN0 and COMP1_INP analog inputs, and USART2_CTS/TIM2_CH1_ETR alternate functions. |
| 11 | PA1 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN1 and COMP1_INP analog inputs, and USART2_RTS, TIM2_CH2 and LCD_SEG0 alternate functions. |
| 12 | PA2 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN2 and COMP1_INP analog inputs, and USART2_TX, TIM2_CH3, TIM9_CH1 and LCD_SEG1 alternate functions. |
| 13 | PA3 | bidirectional | Standard 3.3 V (TC) I/O with ADC_IN3 and COMP1_INP analog inputs, and USART2_RX, TIM2_CH4, TIM9_CH2 and LCD_SEG2 alternate functions. |
| 14 | PA4 | bidirectional | Standard 3.3 V (TC) I/O with ADC_IN4, DAC_OUT1 and COMP1_INP analog functions, and SPI1_NSS/USART2_CK alternate functions. |
| 15 | PA5 | bidirectional | Standard 3.3 V (TC) I/O with ADC_IN5, DAC_OUT2 and COMP1_INP analog functions, and SPI1_SCK/TIM2_CH1_ETR alternate functions. |
| 16 | PA6 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN6 and COMP1_INP analog inputs, and SPI1_MISO, TIM3_CH1, LCD_SEG3 and TIM10_CH1 alternate functions. |
| 17 | PA7 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN7 and COMP1_INP analog inputs, and SPI1_MOSI, TIM3_CH2, LCD_SEG4 and TIM11_CH1 alternate functions. |
| 18 | PB0 | bidirectional | Standard 3.3 V (TC) I/O with ADC_IN8, COMP1_INP and VREF_OUT analog functions, and TIM3_CH3 and LCD_SEG5 alternate functions. |
| 19 | PB1 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN9, COMP1_INP and VREF_OUT analog functions, and TIM3_CH4 and LCD_SEG6 alternate functions. |
| 20 | PB2/BOOT1 | bidirectional | 5 V tolerant (FT) I/O whose main function is PB2/BOOT1 for boot mode selection. |
| 21 | PB10 | bidirectional | 5 V tolerant (FT) I/O with I2C2_SCL, USART3_TX, TIM2_CH3 and LCD_SEG10 alternate functions. |
| 22 | PB11 | bidirectional | 5 V tolerant (FT) I/O with I2C2_SDA, USART3_RX, TIM2_CH4 and LCD_SEG11 alternate functions. |
| 23 | VSS_1 | power_in | Ground pin for the digital supply domain. |
| 24 | VDD_1 | power_in | Digital supply pin; the datasheet states a device power supply range of 1.65 V to 3.6 V. |
| 25 | PB12 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN18 and COMP1_INP analog inputs, and SPI2_NSS, I2C2_SMBA, USART3_CK, LCD_SEG12 and TIM10_CH1 alternate functions. |
| 26 | PB13 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN19 and COMP1_INP analog inputs, and SPI2_SCK, USART3_CTS, LCD_SEG13 and TIM9_CH1 alternate functions. |
| 27 | PB14 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN20 and COMP1_INP analog inputs, and SPI2_MISO, USART3_RTS, LCD_SEG14 and TIM9_CH2 alternate functions. |
| 28 | PB15 | bidirectional | 5 V tolerant (FT) I/O with ADC_IN21, COMP1_INP and RTC_REFIN analog functions, and SPI2_MOSI, LCD_SEG15 and TIM11_CH1 alternate functions. |
| 29 | PA8 | bidirectional | 5 V tolerant (FT) I/O with USART1_CK, MCO and LCD_COM0 alternate functions. |
| 30 | PA9 | bidirectional | 5 V tolerant (FT) I/O with USART1_TX and LCD_COM1 alternate functions. |
| 31 | PA10 | bidirectional | 5 V tolerant (FT) I/O with USART1_RX and LCD_COM2 alternate functions. |
| 32 | PA11 | bidirectional | 5 V tolerant (FT) I/O with USART1_CTS, SPI1_MISO and USB_DM alternate functions. |
| 33 | PA12 | bidirectional | 5 V tolerant (FT) I/O with USART1_RTS, SPI1_MOSI and USB_DP alternate functions. |
| 34 | PA13 | bidirectional | 5 V tolerant (FT) I/O whose main function is JTMS-SWDIO (serial wire debug data). |
| 35 | VSS_2 | power_in | Ground pin for the digital supply domain. |
| 36 | VDD_2 | power_in | Digital supply pin; the datasheet states a device power supply range of 1.65 V to 3.6 V. |
| 37 | PA14 | bidirectional | 5 V tolerant (FT) I/O whose main function is JTCK-SWCLK (serial wire debug clock). |
| 38 | PA15 | bidirectional | 5 V tolerant (FT) I/O with JTDI, TIM2_CH1_ETR, SPI1_NSS and LCD_SEG17 alternate functions. |
| 39 | PB3 | bidirectional | 5 V tolerant (FT) I/O with JTDO, TIM2_CH2, SPI1_SCK, LCD_SEG7 and COMP2_INM alternate functions. |
| 40 | PB4 | bidirectional | 5 V tolerant (FT) I/O with NJTRST, TIM3_CH1, SPI1_MISO, LCD_SEG8 and COMP2_INP alternate functions. |
| 41 | PB5 | bidirectional | 5 V tolerant (FT) I/O with I2C1_SMBA, TIM3_CH2, SPI1_MOSI, LCD_SEG9 and COMP2_INP alternate functions. |
| 42 | PB6 | bidirectional | 5 V tolerant (FT) I/O with I2C1_SCL, TIM4_CH1 and USART1_TX alternate functions. |
| 43 | PB7 | bidirectional | 5 V tolerant (FT) I/O with I2C1_SDA, TIM4_CH2, USART1_RX and PVD_IN alternate functions. |
| 44 | BOOT0 | input | Dedicated BOOT0 pin used to select the boot mode. |
| 45 | PB8 | bidirectional | 5 V tolerant (FT) I/O with TIM4_CH3, I2C1_SCL, LCD_SEG16 and TIM10_CH1 alternate functions. |
| 46 | PB9 | bidirectional | 5 V tolerant (FT) I/O with TIM4_CH4, I2C1_SDA, LCD_COM3 and TIM11_CH1 alternate functions. |
| 47 | VSS_3 | power_in | Ground pin for the digital supply domain. |
| 48 | VDD_3 | power_in | Digital supply pin; the datasheet states a device power supply range of 1.65 V to 3.6 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32L152C8U6A - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32l152c8u6a-etched.step/stm32l152c8u6a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l152c8u6a.step/stm32l152c8u6a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (133 pp, sha256
5223296de36fe904, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).