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STM32L053R8H6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-64. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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STM32L053R8H6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · TFBGA-64
STM32L053R8H6 from STMicroelectronics, in a TFBGA-64. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PC14-OSC32_IN | bidirectional | FT 5 V tolerant I/O; alternate function OSC32_IN for the 32.768 kHz oscillator, and floating input during and after reset. |
| A2 | PC13 | bidirectional | FT 5 V tolerant I/O; additional functions RTC_TAMP1/RTC_TS/RTC_OUT/WKUP2, and floating input during and after reset. |
| A3 | PB9 | bidirectional | FTf 5 V tolerant I/O with Fast Mode Plus capability; alternate functions LCD_COM3, EVENTOUT, I2C1_SDA and SPI2_NSS/I2S2_WS. |
| A4 | PB4 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI1_MISO, LCD_SEG8, EVENTOUT, TSC_G5_IO2 and TIM22_CH1; additional function COMP2_INP. |
| A5 | PB3 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI1_SCK, LCD_SEG7, TIM2_CH2, TSC_G5_IO1 and EVENTOUT; additional function COMP2_INN. |
| A6 | PA15 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI1_NSS, LCD_SEG17, TIM2_ETR, EVENTOUT, USART2_RX and TIM2_CH1. |
| A7 | PA14 | bidirectional | FT 5 V tolerant I/O; alternate functions SWCLK and USART2_TX. |
| A8 | PA13 | bidirectional | FT 5 V tolerant I/O; alternate functions SWDIO and USB_NOE. |
| B1 | PC15-OSC32_OUT | bidirectional | Standard TC 3.3 V I/O; alternate function OSC32_OUT for the 32.768 kHz oscillator. |
| B2 | VLCD | power_in | LCD supply pin (VLCD) for the LCD controller, listed as a supply pin in the pin definition table. |
| B3 | PB8 | bidirectional | FTf 5 V tolerant I/O with Fast Mode Plus capability; alternate functions LCD_SEG16, TSC_SYNC and I2C1_SCL. |
| B4 | BOOT0 | input | Dedicated BOOT0 pin (type B, input) that selects the boot mode. |
| B5 | PD2 | bidirectional | FT 5 V tolerant I/O; alternate functions LPUART1_RTS/LPUART1_DE and LCD_COM7/LCD_SEG31/LCD_SEG43. |
| B6 | PC11 | bidirectional | FT 5 V tolerant I/O; alternate functions LPUART1_RX and LCD_COM5/LCD_SEG29/LCD_SEG41. |
| B7 | PC10 | bidirectional | FT 5 V tolerant I/O; alternate functions LPUART1_TX and LCD_COM4/LCD_SEG28/LCD_SEG40. |
| B8 | PA12 | bidirectional | FT 5 V tolerant I/O powered by VDD_USB; alternate functions SPI1_MOSI, EVENTOUT, TSC_G4_IO4, USART1_RTS/USART1_DE, USB_DP and COMP2_OUT. |
| C1 | PH0-OSC_IN | bidirectional | Standard TC 3.3 V I/O; alternate function OSC_IN for the high-speed oscillator input and USB_CRS_SYNC. |
| C2 | VSS | power_in | Ground supply pin. |
| C3 | PB7 | bidirectional | FTf 5 V tolerant I/O with Fast Mode Plus capability; alternate functions USART1_RX, I2C1_SDA, LPTIM1_IN2 and TSC_G5_IO4; additional functions COMP2_INP and PVD_IN. |
| C4 | PB5 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI1_MOSI, LCD_SEG9, LPTIM1_IN1, I2C1_SMBA and TIM22_CH2; additional function COMP2_INP. |
| C5 | PC12 | bidirectional | FT 5 V tolerant I/O; alternate function LCD_COM6/LCD_SEG30/LCD_SEG42. |
| C6 | PA10 | bidirectional | FT 5 V tolerant I/O; alternate functions LCD_COM2, TSC_G4_IO2 and USART1_RX. |
| C7 | PA9 | bidirectional | FT 5 V tolerant I/O; alternate functions MCO, LCD_COM1, TSC_G4_IO1 and USART1_TX. |
| C8 | PA11 | bidirectional | FT 5 V tolerant I/O powered by VDD_USB; alternate functions SPI1_MISO, EVENTOUT, TSC_G4_IO3, USART1_CTS and USB_DM; additional function COMP1_OUT. |
| D1 | PH1-OSC_OUT | bidirectional | Standard TC 3.3 V I/O; alternate function OSC_OUT for the high-speed oscillator output. |
| D2 | VDD | power_in | Positive supply pin of the device. |
| D3 | PB6 | bidirectional | FTf 5 V tolerant I/O with Fast Mode Plus capability; alternate functions USART1_TX, I2C1_SCL, LPTIM1_ETR and TSC_G5_IO3; additional function COMP2_INP. |
| D4 | VSS | power_in | Ground supply pin. |
| D5 | VSS | power_in | Ground supply pin. |
| D6 | VSS | power_in | Ground supply pin. |
| D7 | PA8 | bidirectional | FT 5 V tolerant I/O; alternate functions MCO, LCD_COM0, USB_CRS_SYNC, EVENTOUT and USART1_CK. |
| D8 | PC9 | bidirectional | FT 5 V tolerant I/O; alternate functions TIM21_ETR, LCD_SEG27, USB_NOE and TSC_G8_IO4. |
| E1 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| E2 | PC1 | bidirectional | FT 5 V tolerant I/O; alternate functions LPTIM1_OUT, LCD_SEG19, EVENTOUT and TSC_G7_IO2; additional function ADC_IN11. |
| E3 | PC0 | bidirectional | FT 5 V tolerant I/O; alternate functions LPTIM1_IN1, LCD_SEG18, EVENTOUT and TSC_G7_IO1; additional function ADC_IN10. |
| E4 | VDD | power_in | Positive supply pin of the device. |
| E5 | VDD | power_in | Positive supply pin of the device. |
| E6 | VDD_USB | power_in | Supply pin for the I/Os PA11 and PA12; for all characteristics that refer to VDD, VDD_USB must be used instead. |
| E7 | PC7 | bidirectional | FT 5 V tolerant I/O; alternate functions TIM22_CH2, LCD_SEG25 and TSC_G8_IO2. |
| E8 | PC8 | bidirectional | FT 5 V tolerant I/O; alternate functions TIM22_ETR, LCD_SEG26 and TSC_G8_IO3. |
| F1 | VSSA | power_in | Analog ground supply pin. |
| F2 | PC2 | bidirectional | FT 5 V tolerant I/O; alternate functions LPTIM1_IN2, LCD_SEG20, SPI2_MISO/I2S2_MCK and TSC_G7_IO3; additional function ADC_IN12. |
| F3 | PA2 | bidirectional | FT 5 V tolerant I/O; alternate functions TIM21_CH1, LCD_SEG1, TIM2_CH3, TSC_G1_IO3, USART2_TX and COMP2_OUT; additional functions COMP2_INM6 and ADC_IN2. |
| F4 | PA5 | bidirectional | Standard TC 3.3 V I/O; alternate functions SPI1_SCK, TIM2_ETR, TSC_G2_IO2 and TIM2_CH1; additional functions COMP1_INM5, COMP2_INM5 and ADC_IN5. |
| F5 | PB0 | bidirectional | FT 5 V tolerant I/O; alternate functions EVENTOUT, LCD_SEG5 and TSC_G3_IO2; additional functions LCD_VLCD3, ADC_IN8 and VREF_OUT. |
| F6 | PC6 | bidirectional | FT 5 V tolerant I/O; alternate functions TIM22_CH1, LCD_SEG24 and TSC_G8_IO1. |
| F7 | PB15 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI2_MOSI/I2S2_SD and LCD_SEG15; additional function RTC_REFIN. |
| F8 | PB14 | bidirectional | FTf 5 V tolerant I/O with Fast Mode Plus capability; alternate functions SPI2_MISO/I2S2_MCK, LCD_SEG14, RTC_OUT, TSC_G6_IO4, LPUART1_RTS/LPUART1_DE, I2C2_SDA and TIM21_CH2. |
| G1 | VREF+ | power_in | Input reference voltage pin for the ADC and DAC. |
| G2 | PA0 | bidirectional | Standard TC 3.3 V I/O; alternate functions TIM2_CH1, TSC_G1_IO1, USART2_CTS, TIM2_ETR and COMP1_OUT; additional functions COMP1_INM6, ADC_IN0 and RTC_TAMP2/WKUP1. |
| G3 | PA3 | bidirectional | FT 5 V tolerant I/O; alternate functions TIM21_CH2, LCD_SEG2, TIM2_CH4, TSC_G1_IO4 and USART2_RX; additional functions COMP2_INP and ADC_IN3. |
| G4 | PA6 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI1_MISO, LCD_SEG3, TSC_G2_IO3, LPUART1_CTS, TIM22_CH1, EVENTOUT and COMP1_OUT; additional function ADC_IN6. |
| G5 | PB1 | bidirectional | FT 5 V tolerant I/O; alternate functions LCD_SEG6, TSC_G3_IO3 and LPUART1_RTS/LPUART1_DE; additional functions ADC_IN9 and VREF_OUT. |
| G6 | PB2 | bidirectional | FT 5 V tolerant I/O; alternate functions LPTIM1_OUT and TSC_G3_IO4; additional function LCD_VLCD2. |
| G7 | PB10 | bidirectional | FT 5 V tolerant I/O; alternate functions LCD_SEG10, TIM2_CH3, TSC_SYNC, LPUART1_TX, SPI2_SCK and I2C2_SCL. |
| G8 | PB13 | bidirectional | FTf 5 V tolerant I/O with Fast Mode Plus capability; alternate functions SPI2_SCK/I2S2_CK, LCD_SEG13, TSC_G6_IO3, LPUART1_CTS, I2C2_SCL and TIM21_CH1. |
| H1 | VDDA | power_in | Analog supply pin of the device. |
| H2 | PA1 | bidirectional | FT 5 V tolerant I/O; alternate functions EVENTOUT, LCD_SEG0, TIM2_CH2, TSC_G1_IO2, USART2_RTS/USART2_DE and TIM21_ETR; additional functions COMP1_INP and ADC_IN1. |
| H3 | PA4 | bidirectional | Standard TC 3.3 V I/O with reduced touch sensing sensitivity; alternate functions SPI1_NSS, TSC_G2_IO1, USART2_CK and TIM22_ETR; additional functions COMP1_INM4, COMP2_INM4, ADC_IN4 and DAC_OUT. |
| H4 | PA7 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI1_MOSI, LCD_SEG4, TSC_G2_IO4, TIM22_CH2, EVENTOUT and COMP2_OUT; additional function ADC_IN7. |
| H5 | PC4 | bidirectional | FT 5 V tolerant I/O; alternate functions EVENTOUT, LCD_SEG22 and LPUART1_TX; additional function ADC_IN14. |
| H6 | PC5 | bidirectional | FT 5 V tolerant I/O; alternate functions LCD_SEG23, LPUART1_RX and TSC_G3_IO1; additional function ADC_IN15. |
| H7 | PB11 | bidirectional | FT 5 V tolerant I/O; alternate functions EVENTOUT, LCD_SEG11, TIM2_CH4, TSC_G6_IO1, LPUART1_RX and I2C2_SDA. |
| H8 | PB12 | bidirectional | FT 5 V tolerant I/O; alternate functions SPI2_NSS/I2S2_WS, LCD_SEG12, LPUART1_RTS/LPUART1_DE, TSC_G6_IO2, I2C2_SMBA and EVENTOUT; additional function LCD_VLCD1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TFBGA-64 |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Standard operating voltage (BOR enabled at power-on) | VDD | 1.8 | 3.6 | V | BOR detector enabled, at power-on | 56 | |
| Analog operating voltage (all features) | VDDA | 1.8 | 3.6 | V | Must be the same voltage as VDD | 56 | |
| Internal AHB clock frequency | fHCLK | 0 | 32 | MHz | - | 56 | |
| Internal APB1 clock frequency | fPCLK1 | 0 | 32 | MHz | - | 56 | |
| Internal APB2 clock frequency | fPCLK2 | 0 | 32 | MHz | - | 56 | |
| Standard operating voltage, USB domain | VDD_USB | 3 | 3.6 | V | USB peripheral used | 56 | |
| Standard operating voltage, USB domain | VDD_USB | 0 | 3.6 | V | USB peripheral not used | 56 | |
| Input voltage on FT, FTf and RST pins | VIN | -0.3 | 5.5 | V | 2.0 V ≤ VDD ≤ 3.6 V | 56 | |
| Input voltage on FT, FTf and RST pins | VIN | -0.3 | 5.2 | V | 1.65 V ≤ VDD ≤ 2.0 V | 56 | |
| Input voltage on BOOT0 pin | VIN | 0 | 5.5 | V | - | 56 | |
| Power dissipation TFBGA64 | PD | 327 | mW | TA = 85 °C (range 6) | 56 | ||
| Temperature range | TA | -40 | 85 | °C | Maximum power dissipation (range 6) | 56 | |
| Junction temperature range | TJ | -40 | 105 | °C | Range 6: -40 °C ≤ TA ≤ 85 °C | 56 | |
| External main supply voltage (VDDA, VDD_USB, VDD) | VDD-VSS | -0.3 | 4 | V | Including VDDA, VDD_USB, VDD | 54 | |
| Variations between any VDDx and VDDA power pins | /VDDA-VDDx/ | 300 | mV | - | 54 | ||
| Allowed voltage difference for VREF+ > VDDA | VREF+ -VDDA | 0.4 | V | - | 54 | ||
| Total current into sum of all VDD power lines (source) | ΣIVDD | 105 | mA | - | 55 | ||
| Total current into VDD_USB power lines (source) | ΣIVDD_USB | 25 | mA | - | 55 | ||
| Maximum current into each VDD power pin (source) | IVDD(PIN) | 100 | mA | - | 55 | ||
| Output current sunk by any I/O and control pin except FTf pins | IIO | 16 | mA | - | 55 | ||
| Output current sunk by FTf pins | IIO | 22 | mA | - | 55 | ||
| Output current sourced by any I/O and control pin | IIO | -16 | mA | - | 55 | ||
| Total output current sunk by sum of all IOs and control pins except PA11 and PA12 | ΣIIO(PIN) | 90 | mA | - | 55 | ||
| Total output current sunk by PA11 and PA12 | ΣIIO(PIN) | 25 | mA | PA11 and PA12 only | 55 | ||
| Total output current sourced by sum of all IOs and control pins | ΣIIO(PIN) | -90 | mA | - | 55 | ||
| Injected current on FT, FTf, RST and B pins | IINJ(PIN) | -5 | 0 | mA | Negative injection only; positive not possible | 55 | |
| Injected current on TC pin | IINJ(PIN) | -5 | 5 | mA | - | 55 | |
| Total injected current (sum of all I/O and control pins) | ΣIINJ(PIN) | -25 | 25 | mA | Absolute sum of positive and negative injected currents | 55 | |
| Storage temperature range | TSTG | -65 | 150 | °C | - | 55 | |
| Power-on/power down reset threshold, falling edge | VPOR/PDR | 1 | 1.5 | 1.65 | V | Falling edge | 58 |
| Power-on/power down reset threshold, rising edge | VPOR/PDR | 1.3 | 1.5 | 1.65 | V | Rising edge | 58 |
| Brown-out reset threshold 0, falling edge | VBOR0 | 1.67 | 1.7 | 1.74 | V | Falling edge | 58 |
| Brown-out reset threshold 0, rising edge | VBOR0 | 1.69 | 1.76 | 1.8 | V | Rising edge | 58 |
| Brown-out reset threshold 1, falling edge | VBOR1 | 1.87 | 1.93 | 1.97 | V | Falling edge | 58 |
| Brown-out reset threshold 1, rising edge | VBOR1 | 1.96 | 2.03 | 2.07 | V | Rising edge | 58 |
| Brown-out reset threshold 2, falling edge | VBOR2 | 2.22 | 2.3 | 2.35 | V | Falling edge | 58 |
| Brown-out reset threshold 2, rising edge | VBOR2 | 2.31 | 2.41 | 2.44 | V | Rising edge | 58 |
| Brown-out reset threshold 3, falling edge | VBOR3 | 2.45 | 2.55 | 2.6 | V | Falling edge | 58 |
| Brown-out reset threshold 3, rising edge | VBOR3 | 2.54 | 2.66 | 2.7 | V | Rising edge | 58 |
| Brown-out reset threshold 4, falling edge | VBOR4 | 2.68 | 2.8 | 2.85 | V | Falling edge | 58 |
| Brown-out reset threshold 4, rising edge | VBOR4 | 2.78 | 2.9 | 2.95 | V | Rising edge | 58 |
| Internal reference voltage | VREFINT out | 1.202 | 1.224 | 1.242 | V | -40 °C < TJ < +125 °C | 59 |
| Temperature coefficient of internal reference voltage | TCoeff | 25 | 100 | ppm/°C | -40 °C < TJ < +125 °C | 59 | |
| Long-term stability of internal reference voltage | ACoeff | 1000 | ppm | 1000 hours, T= 25 °C | 59 | ||
| Voltage coefficient of internal reference voltage | VDDCoeff | 2000 | ppm/V | 3.0 V < VDDA < 3.6 V | 59 | ||
| LSI frequency | fLSI | 26 | 38 | 56 | kHz | 78 | |
| LSI oscillator frequency drift | DLSI | -10 | 4 | % | 0°C ≤ TA ≤ 85°C | 78 | |
| Accuracy of factory-calibrated HSI16 oscillator | ACCHSI16 | -5.45 | 3.25 | % | VDDA = 1.65 V to 3.6 V, TA = − 40 to 125 °C | 77 | |
| Accuracy of factory-calibrated HSI16 oscillator | ACCHSI16 | -1 | 1 | % | VDDA = 3.0 V, TA = 25 °C | 77 | |
| HSI16 frequency | fHSI16 | 16 | MHz | VDD = 3.0 V | 77 | ||
| Supply current in Stop mode | IDD (Stop) | 0.41 | 1 | µA | TA = − 40 to 25°C | 67 | |
| Supply current in Stop mode | IDD (Stop) | 1.7 | 4.5 | µA | TA= 85°C | 67 | |
| Supply current in Standby mode, independent watchdog and LSI enabled | IDD (Standby) | 1.3 | 1.7 | µA | TA = − 40 to 25°C | 68 | |
| Supply current in Standby mode, independent watchdog and LSI OFF | IDD (Standby) | 0.29 | 0.6 | µA | TA = − 40 to 25°C | 68 | |
| Supply current in Run mode, code executed from Flash | IDD (Run from Flash) | 6.3 | 6.8 | mA | Range 1, VCORE=1.8 V, VOS[1:0]=01, HSI clock 32 MHz | 61 | |
| Weak pull-up equivalent resistor | RPU | 25 | 45 | 65 | kΩ | VIN = VSS | 86 |
| Weak pull-down equivalent resistor | RPD | 25 | 45 | 65 | kΩ | VIN = VDD | 86 |
| I/O pin capacitance | CIO | 5 | pF | 86 | |||
| Data retention voltage in Stop mode or under Reset | VRM | 1.65 | V | STOP mode (or RESET) | 81 |
CAD (KiCad official)
- Symbol:
STM32L053R8H6 - Footprint:
Package_BGA:TFBGA-64_5x5mm_Layout8x8_P0.5mm - 3D model: TFBGA-64 (KiCad packages3D, STEP)
- 3D model files:
stm32l053r8h6-etched.step/stm32l053r8h6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l053r8h6.step/stm32l053r8h6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (136 pp, sha256
b30ef01e0e2d9c80, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).