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STM32H7R7I8T6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-176(24x24). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32h7r7i8t6factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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STM32H7R7I8T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-176(24x24)

STM32H7R7I8T6 from STMicroelectronics, in a LQFP-176(24x24). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup domain supply, 1.2 V to 3.6 V.
2 PC13 bidirectional GPIO supplied through the VSW power switch (output limited to 2 MHz, 30 pF, not a current source); TAMP_IN1/TAMP_OUT2, RTC_OUT1/RTC_TS, WKUP3.
3 PC14-OSC32_IN bidirectional GPIO supplied through the VSW power switch (limited output drive); OSC32_IN for the 32.768 kHz crystal.
4 PC15-OSC32_OUT bidirectional GPIO supplied through the VSW power switch (limited output drive); OSC32_OUT for the 32.768 kHz crystal.
5 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
6 VSS power_in Digital ground.
7 PE3 bidirectional FT_h I/O with TRACED0, LPTIM5_ETR, TIM15_BKIN, SAI1_SD_B, ETH_MII_RXD3, FMC_D12/AD12 alternate functions.
8 PE4 bidirectional FT_h I/O with TRACED1, SAI1_D2, ADF1_SDI0, SPI4_NSS, SAI1_FS_A, FMC_D13/AD13, DCMIPP_D4 alternate functions.
9 PE5 bidirectional FT_h I/O with TRACED2, ADF1_CCK1, SAI1_CK2, SPI4_MISO, SAI1_SCK_A, FMC_D14/AD14 alternate functions.
10 PE6 bidirectional FT_h I/O with TRACED3, TIM1_BKIN2, SAI1_D1, SPI4_MOSI, SAI1_SD_A, FMC_D15/AD15 alternate functions.
11 VSS power_in Digital ground.
12 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
13 VSSSMPS power_in Ground for the internal SMPS step-down converter.
14 VLXSMPS power_out Switching node of the internal SMPS step-down converter, connected to the external inductor.
15 VDDSMPS power_in Supply for the internal SMPS step-down converter, 1.71 V to 3.6 V.
16 VFBSMPS input SMPS step-down converter output voltage feedback sense input.
17 PF5 bidirectional FT_h I/O with DCMIPP_D15, UCPD_FRSTX1, PSSI_D15, FMC_CLE, ETH_MII_RXD2, FMC_A16 alternate functions.
18 PF6 bidirectional FT_h I/O with TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, FMC_ALE, FMC_A17 alternate functions.
19 PF7 bidirectional FT_h I/O with TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, FMC_A18, LCD_G0 alternate functions.
20 PF8 bidirectional FT_h I/O with TIM16_CH1N, DCMIPP_PIXCLK, SPI5_MISO, SAI1_SCK_B, UART7_RTS/DE, TIM13_CH1, FMC_A19, LCD_G1.
21 PF9 bidirectional FT_h I/O with TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, FMC_A21, LCD_R0.
22 PF10 bidirectional FT_h I/O with TIM16_BKIN, SAI1_D3, DCMIPP_D15/D11, PSSI_D15/D11, FMC_A22, LCD_R1.
23 PH0-OSC_IN bidirectional FT_h I/O after reset (PH0); OSC_IN input for the HSE crystal/clock.
24 PH1-OSC_OUT bidirectional FT_h I/O after reset (PH1); OSC_OUT output for the HSE crystal.
25 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
26 VSS power_in Digital ground.
27 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
28 PC0 bidirectional FT_h I/O with GFXTIM_FCKCAL, SAI2_FS_B, FMC_NBL1, GFXTIM_LCKCAL; analog input ADC12_INP10.
29 PC1 bidirectional FT_h I/O with TRACED0, SAI1_D1, SPI2_MOSI, ETH_MDC, MDIOS_MDC; ADC12_INP11/INN10, TAMP_IN7/OUT8, WKUP4.
30 PC2 bidirectional FT_h I/O with TIM1_CH1, SPI2_MISO, ETH_MII_TXD2, FMC_A1; analog inputs ADC12_INP12/INN11.
31 PC3 bidirectional FT_h I/O with TIM1_CH2, SPI2_MOSI, ETH_MII_TX_CLK, FMC_A2; analog inputs ADC12_INP13/INN12.
32 VSSA power_in Analog ground.
33 VREFM power_in Negative reference voltage input for the ADCs.
34 VREFP power_in Positive reference voltage for the ADCs (VREFBUF output/input).
35 VDDA power_in Analog supply: 1.62 V min with ADC, 2.10 V min with VREFBUF, up to 3.6 V.
36 PA0 bidirectional FT_h I/O with TIM2_CH1, TIM5_CH1, USART2_CTS, UART4_TX, SDMMC2_CMD, FMC_AD7; ADC12_INP0/INN1, WKUP1.
37 PA1 bidirectional FT_h I/O with TIM2_CH2, TIM5_CH2, USART2_RTS/DE, UART4_RX, ETH_MII_RX_CLK, LCD_G2; ADC12_INP1.
38 PA2 bidirectional FT_h I/O with TIM2_CH3, USART2_TX, ETH_MDIO, LCD_B7, MDIOS_MDIO; ADC12_INP14, WKUP2.
39 PA3 bidirectional FT_h I/O with TIM2_CH4, USART2_RX, ETH_MII_COL, LCD_DE, TIM1_CH3; analog input ADC12_INP15.
40 VSS power_in Digital ground.
41 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
42 PA4 bidirectional FT_h I/O with SPI1_NSS/I2S1_WS, SPI3_NSS, USART2_CK, OTG_HS_SOF, DCMIPP_HSYNC; analog input ADC1_INP18.
43 PA5 bidirectional FT_h I/O with PWR_CSTOP, TIM2_CH1, SPI1_SCK, FMC_NOE, LCD_CLK; analog input ADC2_INP18.
44 PA6 bidirectional FT_h I/O with PWR_CSLEEP, TIM1_BKIN, TIM3_CH1, SPI1_MISO, LCD_HSYNC; analog input ADC12_INP3.
45 PA7 bidirectional FT_h I/O with TIM1_CH1N, TIM3_CH2, SPI1_MOSI, ETH_MII_RX_DV, FMC_INT; ADC12_INP7/INN3.
46 PC4 bidirectional FT_h I/O with I2S1_MCK, SPDIFRX_IN2, ETH_MII_RXD0, FMC_A3; analog input ADC12_INP4.
47 PC5 bidirectional FT_h I/O with SAI1_D3, SPDIFRX_IN3, ETH_MII_RXD1, FMC_A5; ADC12_INP8/INN4.
48 PB0 bidirectional FT_h I/O with TIM1_CH2N, TIM3_CH3, SPI1_SCK, UART4_CTS, ETH_MII_TXD0, LCD_VSYNC; ADC12_INP9/INN5.
49 PB1 bidirectional FT_h I/O with TIM1_CH3N, TIM3_CH4, FDCAN2_TX, LCD_G2, ETH_MII_TXD1, FMC_NOE; analog input ADC12_INP5.
50 PB2 bidirectional FT_h I/O with RTC_OUT2, SAI1_D1, ADF1_SDI0, SPI3_MOSI, LCD_B2, FMC_NWE.
51 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
52 VSS power_in Digital ground.
53 PF11 bidirectional FT_h I/O with SPI5_MOSI, PSSI_D12, SAI2_SD_B, FMC_A23, LCD_B0; analog input ADC1_INP2.
54 PE7 bidirectional FT_h I/O with TIM1_ETR, UART7_RX, FMC_A20, SAI2_SD_B, FMC_A4.
55 PE8 bidirectional FT_h I/O with TIM1_CH1N, UART7_TX, FMC_A12.
56 PE9 bidirectional FT_h I/O with TIM1_CH1, UART7_RTS/DE, FMC_A14, FMC_BA0.
57 PE10 bidirectional FT_h I/O with TIM1_CH2N, UART7_CTS, FMC_A15, FMC_BA1.
58 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
59 VDDLDO power_in Internal regulator supply, 1.71 V to 3.6 V.
60 VSS power_in Digital ground.
61 VCAP1 passive Core regulator output; connect 2.2 µF (ESR < 100 mΩ) external capacitor.
62 PO1 bidirectional FT_h I/O, XSPIM_P1_NCS2 (XSPI port 1 chip select 2).
63 VDDXSPI1 power_in XSPI port 1 I/O supply, 1.62 V to 3.6 V (HSLV=0).
64 VSS power_in Digital ground.
65 PP4 bidirectional FT_h I/O, XSPIM_P1_IO4.
66 PP2 bidirectional FT_h I/O, XSPIM_P1_IO2.
67 PP3 bidirectional FT_h I/O, XSPIM_P1_IO3.
68 VSS power_in Digital ground.
69 VDDXSPI1 power_in XSPI port 1 I/O supply, 1.62 V to 3.6 V (HSLV=0).
70 PO5 bidirectional FT_h I/O, XSPIM_P1_NCLK (inverted clock).
71 PO4 bidirectional FT_h I/O, XSPIM_P1_CLK.
72 PP5 bidirectional FT_h I/O, XSPIM_P1_IO5.
73 PP0 bidirectional FT_h I/O, XSPIM_P1_IO0.
74 VSS power_in Digital ground.
75 VDDXSPI1 power_in XSPI port 1 I/O supply, 1.62 V to 3.6 V (HSLV=0).
76 PP6 bidirectional FT_h I/O, XSPIM_P1_IO6.
77 PO2 bidirectional FT_h I/O, XSPIM_P1_DQS0.
78 PP7 bidirectional FT_h I/O, XSPIM_P1_IO7.
79 PP1 bidirectional FT_h I/O, XSPIM_P1_IO1.
80 VSS power_in Digital ground.
81 VDDXSPI1 power_in XSPI port 1 I/O supply, 1.62 V to 3.6 V (HSLV=0).
82 PO0 bidirectional FT_h I/O, XSPIM_P1_NCS1.
83 PB10 bidirectional FT_fh (Fm+) I/O with TIM2_CH3, LPTIM2_IN1, I2C2_SCL, SPI2_SCK, USART3_TX, ETH_MII_RX_ER, FMC_D11, LCD_G7.
84 PB11 bidirectional FT_fh (Fm+) I/O with TIM2_CH4, I2C2_SDA, USART3_RX, ETH_MII_TX_EN, FMC_D10, LCD_G6.
85 PB12 bidirectional FT_h I/O with TIM1_BKIN, I2C2_SMBA, SPI2_NSS, USART3_CK, FDCAN2_RX, FMC_D9, LCD_G5, UART5_RX.
86 PB13 bidirectional FT_h I/O with TIM1_CH1N, SPI2_SCK, SDMMC1_D0, USART3_CTS, FDCAN2_TX, LCD_G4, FMC_D8, UART5_TX.
87 PB14 bidirectional FT_h I/O with TIM1_CH2N, TIM12_CH1, USART1_TX, SPI2_MISO, USART3_RTS/DE, SDMMC2_D0, FMC_NE1, LCD_DE.
88 PB15 bidirectional FT_h I/O with RTC_REFIN, TIM1_CH3N, USART1_RX, SPI2_MOSI, UART4_CTS, SDMMC2_D1, LCD_G7; PVD_IN.
89 VCAP2 passive Core regulator output; connect 2.2 µF (ESR < 100 mΩ) external capacitor.
90 VSS power_in Digital ground.
91 VDDLDO power_in Internal regulator supply, 1.71 V to 3.6 V.
92 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
93 VDDXSPI2 power_in XSPI port 2 I/O supply, 1.62 V to 3.6 V (HSLV=0).
94 VSS power_in Digital ground.
95 PN8 bidirectional FT_h I/O with XSPIM_P2_IO4, FMC_D4/AD4.
96 PN4 bidirectional FT_h I/O with XSPIM_P2_IO2, FMC_D2/AD2.
97 PN5 bidirectional FT_h I/O with XSPIM_P2_IO3, FMC_D3/AD3.
98 VSS power_in Digital ground.
99 VDDXSPI2 power_in XSPI port 2 I/O supply, 1.62 V to 3.6 V (HSLV=0).
100 PN7 bidirectional FT_h I/O with XSPIM_P2_NCLK, FMC_CLK.
101 PN6 bidirectional FT_h I/O with XSPIM_P2_CLK, FMC_SDCLK.
102 PN9 bidirectional FT_h I/O with XSPIM_P2_IO5, FMC_D5/AD5.
103 PN2 bidirectional FT_h I/O with XSPIM_P2_IO0, FMC_D0/AD0.
104 VSS power_in Digital ground.
105 VDDXSPI2 power_in XSPI port 2 I/O supply, 1.62 V to 3.6 V (HSLV=0).
106 PN10 bidirectional FT_h I/O with XSPIM_P2_IO6, FMC_D6/AD6.
107 PN0 bidirectional FT_h I/O with XSPIM_P2_DQS0, FMC_NE4.
108 PN11 bidirectional FT_h I/O with XSPIM_P2_IO7, FMC_D7/AD7.
109 PN3 bidirectional FT_h I/O with XSPIM_P2_IO1, FMC_D1/AD1.
110 VDDXSPI2 power_in XSPI port 2 I/O supply, 1.62 V to 3.6 V (HSLV=0).
111 PN1 bidirectional FT_h I/O with XSPIM_P2_NCS1, FMC_NBL0.
112 PC6 bidirectional FT_h I/O with TIM3_CH1, TIM9_CH1, I2S2_MCK, SDMMC1_D0DIR, PSSI_D0, SDMMC2_D6, SDMMC1_D6, DCMIPP_D0.
113 PC7 bidirectional FT_h I/O with TRGIO, TIM3_CH2, TIM9_CH2, I2S3_MCK, SDMMC1_D123DIR, SDMMC2_D7, SDMMC1_D7, DCMIPP_D1.
114 PC8 bidirectional FT_h I/O with TRACED1, TIM3_CH3, I2C3_SMBA, UART5_RTS/DE, PSSI_D2, SDMMC1_D0, DCMIPP_D2.
115 PC9 bidirectional FT_fh (Fm+) I/O with MCO2, TIM3_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, SDMMC1_D1, DCMIPP_D3.
116 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
117 PA8 bidirectional FT_fh (Fm+) I/O with MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, UART7_RX, FMC_AD4, LCD_B6.
118 PA9 bidirectional FT_fh (Fm+) I/O with TIM1_CH2, LPUART1_TX, I2C3_SDA, SPI2_SCK, USART1_TX, FMC_AD3, LCD_B5.
119 PA10 bidirectional FT_h I/O with TIM1_CH3, LPUART1_RX, USART1_RX, MDIOS_MDIO, FMC_AD2, LCD_B4.
120 PA11 bidirectional FT_h I/O with TIM1_CH4, LPUART1_CTS, SPI2_NSS, UART4_RX, USART1_CTS, FDCAN1_RX, LCD_B3.
121 PA12 bidirectional FT_h I/O with TIM1_ETR, LPUART1_RTS/DE, SPI2_SCK, UART4_TX, USART1_RTS/DE, FDCAN1_TX, LCD_B2.
122 PA13(JTMS/SWDIO) bidirectional FT_h I/O configured as JTMS-SWDIO after reset with internal pull-up active.
123 PA14(JTCK/SWCLK) bidirectional FT_h I/O configured as JTCK-SWCLK after reset with internal pull-down active.
124 PA15(JTDI) bidirectional FT_h I/O configured as JTDI after reset with internal pull-up active; also TIM2_CH1, HDMI_CEC, SPI1_NSS, UART4_RTS/DE, LCD_R5.
125 VCAP3 passive Core regulator output; connect 2.2 µF (ESR < 100 mΩ) external capacitor.
126 VSS power_in Digital ground.
127 VDDLDO power_in Internal regulator supply, 1.71 V to 3.6 V.
128 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
129 PC10 bidirectional FT_h I/O with TIM1_BKIN, SPI3_SCK, USART3_TX, UART4_TX, PSSI_D14, SDMMC1_D2, DCMIPP_D14.
130 PC11 bidirectional FT_h I/O with SPI3_MISO, USART3_RX, UART4_RX, PSSI_D4, SDMMC1_D3, DCMIPP_D4.
131 PC12 bidirectional FT_h I/O with TRACED3, TIM1_CH4, SPI3_MOSI, USART3_CK, UART5_TX, PSSI_D9, SDMMC1_CK, DCMIPP_D9.
132 PD0 bidirectional FT_h I/O with PSSI_DE, FMC_A22, UART4_RX, FDCAN1_RX, FMC_A6, DCMIPP_HSYNC.
133 PD1 bidirectional FT_h I/O with FMC_A23, UART4_TX, FDCAN1_TX, FMC_A7.
134 PD2 bidirectional FT_h I/O with TRACED2, TIM1_ETR, TIM3_ETR, UART5_RX, SDMMC1_CMD, PSSI_D11, DCMIPP_D11.
135 PE11 bidirectional FT_h I/O with TIM1_CH2, SPI4_NSS, SAI2_SD_B, LCD_VSYNC, FMC_SDNWE.
136 PE12 bidirectional FT_h I/O with TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_SDNRAS.
137 PE13 bidirectional FT_h I/O with TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_SDNCAS.
138 PE14 bidirectional FT_h I/O with TIM1_CH4, GFXTIM_FCKCAL, SPI4_MOSI, SAI2_MCLK_B, FMC_SDNE0, GFXTIM_LCKCAL.
139 PE15 bidirectional FT_h I/O with TIM1_BKIN, GFXTIM_LCKCAL, FMC_SDCKE0, GFXTIM_FCKCAL.
140 VSS power_in Digital ground.
141 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
142 PD3 bidirectional FT_h I/O with TIM1_CH3N, SPI2_SCK, PSSI_D5, USART2_CTS, FMC_NWAIT, DCMIPP_D5, LCD_B1.
143 PD4 bidirectional FT_h I/O with DCMIPP_HSYNC, PSSI_DE, USART2_RTS/DE, ETH_PHY_INTN, FMC_NL; TAMP_IN6/TAMP_OUT3.
144 PG0 bidirectional FT_h I/O with TIM1_CH4N, LCD_R7.
145 PG1 bidirectional FT_h I/O with LCD_R6.
146 VDD50USB power_in USB regulator supply, 4.0 V to 5.5 V (5.0 V typ) when the USB regulator is ON.
147 VDD33USB power_in USB supply, 3.0 V to 3.6 V when USB is used.
148 PM12 bidirectional FT_u I/O with SPI5_NSS; OTG_FS_DM USB full-speed D-.
149 PM11 bidirectional FT_u I/O with SPI5_SCK; OTG_FS_DP USB full-speed D+.
150 PM14 bidirectional FT_u I/O with SPI5_MISO, OTG_FS_VBUS.
151 PM13 bidirectional FT_u I/O with SPI5_MOSI, OTG_FS_ID.
152 BOOT0 input Dedicated boot pin, input up to 9.0 V max; [VPP] additional function.
153 PD5 bidirectional FT_h I/O with TIM1_CH4N, DCMIPP_PIXCLK, PSSI_PDCK, USART2_TX, FMC_NCE, FMC_NE2; TAMP_IN5/TAMP_OUT4.
154 PD6 bidirectional FT_h I/O with SAI1_D1, ADF1_SDI0, ETH_CLK, SPI3_MOSI, USART2_RX, SDMMC2_CK, FMC_NE3, DCMIPP_D10.
155 PD7 bidirectional FT_h I/O with ETH_MII_RX_CLK, SPI1_MOSI, USART2_CK, SPDIFRX_IN0, SDMMC2_CMD, FMC_D8, DCMIPP_D2.
156 PG2 bidirectional FT_h I/O with LCD_HSYNC.
157 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
158 PF0 bidirectional FT_fh (Fm+) I/O with I2C2_SDA, LCD_R2, FMC_A8.
159 PF1 bidirectional FT_fh (Fm+) I/O with I2C2_SCL, FMC_A9.
160 PF2 bidirectional FT_h I/O with I2C2_SMBA, DCMIPP_D14, PSSI_D14, FMC_A10.
161 PF3 bidirectional FT_h I/O with DCMIPP_D9, PSSI_D9, ETH_MII_CRS, FMC_A11.
162 PF4 bidirectional FT_h I/O with DCMIPP_D8, PSSI_D8, ETH_MII_TX_ER, FMC_A13.
163 PB3(JTDO/TRACESWO) bidirectional FT_h I/O configured as JTDO-SWO after reset; also TIM2_CH2, SPI1_SCK, SPI3_SCK, SDMMC2_D2, UART7_RX, LCD_R4.
164 PB4(NJTRST) bidirectional FT_h I/O configured as NJTRST after reset with internal pull-up active; also TIM3_CH1, SPI1_MISO, UART7_TX, LCD_R3.
165 PB5 bidirectional FT_h I/O with TIM17_BKIN, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, FDCAN2_RX, LCD_R2, UART5_RX.
166 VCAP4 passive Core regulator output; connect to the other VCAP pins, no additional capacitor required.
167 VSS power_in Digital ground.
168 VDDLDO power_in Internal regulator supply, 1.71 V to 3.6 V.
169 VDD power_in Digital I/O supply, 1.71 V to 3.6 V.
170 PE0 bidirectional FT_h I/O with LPTIM1_ETR, TIM4_ETR, UART8_RX, SAI2_MCLK_A, FMC_D9; TAMP_IN4/TAMP_OUT5.
171 PE1 bidirectional FT_h I/O with LPTIM1_IN2, UART8_TX, FMC_D10, DCMIPP_D3; TAMP_IN3/TAMP_OUT6.
172 PE2 bidirectional FT_h I/O with TRACECLK, ADF1_CCK0, SAI1_CK1, SPI4_SCK, ETH_MII_TXD3, FMC_D11, TIM1_CH2N.
173 PB6 bidirectional FT_fh (Fm+) I/O with TIM16_CH1N, TIM4_CH1, I2C1_SCL/I3C1_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, FMC_SDNE1.
174 PB7 bidirectional FT_fh (Fm+) I/O with TIM17_CH1N, TIM4_CH2, I2C1_SDA/I3C1_SDA, USART1_RX, LPUART1_RX, FMC_SDCKE1.
175 PB8 bidirectional FT_fh (Fm+) I/O with TIM16_CH1, TIM4_CH3, I2C1_SCL/I3C1_SCL, UART4_RX, FDCAN1_RX, SDMMC2_D4, FMC_D9.
176 PB9 bidirectional FT_fh (Fm+) I/O with TIM17_CH1, TIM4_CH4, I2C1_SDA/I3C1_SDA, SPI2_NSS, UART4_TX, FDCAN1_TX; TAMP_IN2/TAMP_OUT1.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-176(24x24)
Category Embedded Processors & Controllers
Pins 176

CAD (KiCad official)

  • Symbol: STM32H7R7I8T6
  • Footprint: Package_QFP:LQFP-176_24x24mm_P0.5mm
  • 3D model: LQFP-176(24x24) (KiCad packages3D, STEP)
  • 3D model files: stm32h7r7i8t6-etched.step / stm32h7r7i8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32h7r7i8t6.step / stm32h7r7i8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (320 pp, sha256 f818b9d0f5f67e1a, retrieved 2026-10-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF