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STM32H7A3ZIT6Q

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32H7A3ZIT6Q

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

STM32H7A3ZIT6Q from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional FT_h2 I/O (5 V tolerant, high-speed low-voltage group h2, mainly FMC); alternate functions include TRACECLK, SAI1_CK1, SPI4_SCK, OCTOSPIM_P1_IO2, USART10_RX and FMC_A23.
2 PE3 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TRACED0, TIM15_BKIN, SAI1_SD_B, USART10_TX and FMC_A19.
3 PE4 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TRACED1, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, SPI4_NSS, FMC_A20, DCMI_D4/PSSI_D4 and LCD_B0.
4 PE5 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TRACED2, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, FMC_A21, DCMI_D6/PSSI_D6 and LCD_G0.
5 PE6 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, FMC_A22, DCMI_D7/PSSI_D7 and LCD_G1.
6 VSS power_in Ground reference pin of the digital supply domain.
7 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
8 VBAT power_in Backup-domain supply, 1.2 V minimum to 3.6 V maximum (Table 22).
9 PC13 bidirectional FT I/O (5 V tolerant); additional functions TAMP_IN1/TAMP_OUT2/TAMP_OUT3, RTC_OUT1/RTC_TS and WKUP3.
10 PC14-OSC32_IN bidirectional FT I/O (5 V tolerant) that also serves as the LSE (32.768 kHz) oscillator input OSC32_IN.
11 PC15-OSC32_OUT bidirectional FT I/O (5 V tolerant) that also serves as the LSE (32.768 kHz) oscillator output OSC32_OUT.
12 VSS power_in Ground reference pin of the digital supply domain.
13 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
14 VSSSMPS power_in Ground pin of the internal SMPS step-down converter.
15 VLXSMPS power_out Switching output node of the SMPS step-down converter, connected to the external inductor.
16 VDDSMPS power_in Supply of the internal SMPS step-down converter, 1.62 V minimum to 3.6 V maximum (VDDSMPS = VDD).
17 VFBSMPS input Feedback input of the SMPS step-down converter used to regulate its output.
18 VSS power_in Ground reference pin of the digital supply domain.
19 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
20 PF6 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_Rx and OCTOSPIM_P1_IO3.
21 PF7 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_Tx and OCTOSPIM_P1_IO2.
22 PF8 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS, TIM13_CH1 and OCTOSPIM_P1_IO0.
23 PF9 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1 and OCTOSPIM_P1_IO1.
24 PF10 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include TIM16_BKIN, SAI1_D3, PSSI_D15, OCTOSPIM_P1_CLK, DCMI_D11/PSSI_D11 and LCD_DE.
25 PH0-OSC_IN bidirectional FT I/O (5 V tolerant) that also serves as the HSE (4-50 MHz) oscillator input OSC_IN.
26 PH1-OSC_OUT bidirectional FT I/O (5 V tolerant) that also serves as the HSE (4-50 MHz) oscillator output OSC_OUT.
27 NRST bidirectional Bidirectional reset pin with an embedded weak pull-up resistor.
28 PC0 bidirectional FT_a I/O (5 V tolerant, analog option supplied by VDDA); alternate functions include DFSDM1_CKIN0, SAI2_FS_B, FMC_A25, OTG_HS_ULPI_STP and LCD_G2; additional function ADC12_INP10.
29 PC1 bidirectional FT_ah0 I/O (5 V tolerant, analog option and high-speed low-voltage group h0 on VDDMMC); alternate functions include TRACED0, SAI1_D1, SPI2_MOSI/I2S2_SDO, SDMMC2_CK and OCTOSPIM_P1_IO4; additional functions ADC12_INP11, ADC12_INN10, TAMP_IN3 and WKUP6.
30 PC2_C passive TT_a analog pad (3.3 V tolerant); it is a separate pad from PC2 and connects to it only through the SYSCFG-configured analog switch; additional functions ADC2_INP0 and ADC2_INN1.
31 PC3_C passive TT_a analog pad (3.3 V tolerant); it is a separate pad from PC3 and connects to it only through the SYSCFG-configured analog switch; additional function ADC2_INP1.
32 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
33 VSS power_in Ground reference pin of the digital supply domain.
34 VSSA power_in Ground reference pin of the analog domain (ADC, DAC, OPAMP, COMP, VREFBUF).
35 VREF+ power_in Positive reference voltage input for the ADC and DAC.
36 VDDA power_in Analog supply: 1.62 V minimum when ADC or COMP is used (1.8 V for DAC, 2.0 V for OPAMP), 3.6 V maximum.
37 PA0 bidirectional FT_a I/O (5 V tolerant, analog option); alternate functions include TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX and SDMMC2_CMD; additional functions ADC1_INP16 and WKUP1.
38 PA1 bidirectional FT_ah1 I/O (5 V tolerant, analog option and high-speed low-voltage group h1 for OCTOSPI); alternate functions include TIM2_CH2, TIM5_CH2, LPTIM3_OUT, USART2_RTS, UART4_RX and OCTOSPIM_P1_IO3; additional functions ADC1_INP17 and ADC1_INN16.
39 PA2 bidirectional FT_a I/O (5 V tolerant, analog option); alternate functions include TIM2_CH3, TIM5_CH3, TIM15_CH1, USART2_TX, MDIOS_MDIO and LCD_R1; additional functions ADC1_INP14 and WKUP2.
40 PA3 bidirectional FT_ah1 I/O (5 V tolerant, analog option and group h1); alternate functions include TIM2_CH4, TIM5_CH4, OCTOSPIM_P1_CLK, TIM15_CH2, USART2_RX, OTG_HS_ULPI_D0 and LCD_B5; additional function ADC1_INP15.
41 VSS power_in Ground reference pin of the digital supply domain.
42 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
43 PA4 bidirectional TT_a I/O (3.3 V tolerant, analog option); alternate functions include TIM5_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, DCMI_HSYNC/PSSI_DE and LCD_VSYNC; additional functions ADC1_INP18 and DAC1_OUT1.
44 PA5 bidirectional TT_ah0 I/O (3.3 V tolerant, analog option and group h0); alternate functions include TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK and LCD_R4; additional functions ADC1_INP19, ADC1_INN18 and DAC1_OUT2.
45 PA6 bidirectional TT_ah1 I/O (3.3 V tolerant, analog option and group h1); alternate functions include TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, OCTOSPIM_P1_IO3 and LCD_G2; additional functions ADC12_INP3 and DAC2_OUT1.
46 PA7 bidirectional FT_ah1 I/O (5 V tolerant, analog option and group h1); alternate functions include TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, OCTOSPIM_P1_IO2 and FMC_SDNWE; additional functions ADC12_INP7, ADC12_INN3 and OPAMP1_VINM.
47 PC4 bidirectional FT_a I/O (5 V tolerant, analog option); alternate functions include DFSDM1_CKIN2, I2S1_MCK, SPDIFRX1_IN2, FMC_SDNE0 and LCD_R7; additional functions ADC12_INP4, OPAMP1_VOUT and COMP1_INM.
48 PC5 bidirectional FT_ah1 I/O (5 V tolerant, analog option and group h1); alternate functions include SAI1_D3, DFSDM1_DATIN2, PSSI_D15, SPDIFRX1_IN3, OCTOSPIM_P1_DQS, FMC_SDCKE0, COMP1_OUT and LCD_DE; additional functions ADC12_INP8, ADC12_INN4 and OPAMP1_VINM.
49 PB0 bidirectional FT_ah0 I/O (5 V tolerant, analog option and group h0); alternate functions include TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS, LCD_R3, OTG_HS_ULPI_D1 and OCTOSPIM_P1_IO1; additional functions ADC12_INP9, ADC12_INN5, OPAMP1_VINP and COMP1_INP.
50 PB1 bidirectional FT_ah0 I/O (5 V tolerant, analog option and group h0); alternate functions include TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN1, LCD_R6, OTG_HS_ULPI_D2 and OCTOSPIM_P1_IO0; additional functions ADC12_INP5 and COMP1_INM.
51 PB2 bidirectional FT_ah1 I/O (5 V tolerant, analog option and group h1); alternate functions include RTC_OUT2, SAI1_D1, DFSDM1_CKIN1, SPI3_MOSI/I2S3_SDO and OCTOSPIM_P1_CLK; additional function COMP1_INP.
52 PF11 bidirectional FT_ah1 I/O (5 V tolerant, analog option and group h1); alternate functions include SPI5_MOSI, OCTOSPIM_P1_NCLK, SAI2_SD_B, FMC_SDNRAS and DCMI_D12/PSSI_D12; additional function ADC1_INP2.
53 PF14 bidirectional FT_fah2 I/O (5 V tolerant, FM+ I2C option, analog option and group h2); alternate functions include DFSDM1_CKIN6, I2C4_SCL and FMC_A8; additional functions ADC2_INP6 and ADC2_INN2.
54 PF15 bidirectional FT_fh2 I/O (5 V tolerant, FM+ I2C option and group h2); alternate functions include I2C4_SDA and FMC_A9.
55 VSS power_in Ground reference pin of the digital supply domain.
56 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
57 PE7 bidirectional FT_ah2 I/O (5 V tolerant, analog option and group h2); alternate functions include TIM1_ETR, DFSDM1_DATIN2, UART7_Rx, OCTOSPIM_P1_IO4 and FMC_D4/FMC_DA4; additional functions OPAMP2_VOUT and COMP2_INM.
58 PE8 bidirectional FT_ah2 I/O (5 V tolerant, analog option and group h2); alternate functions include TIM1_CH1N, DFSDM1_CKIN2, UART7_Tx, OCTOSPIM_P1_IO5, FMC_D5/FMC_DA5 and COMP2_OUT; additional function OPAMP2_VINM.
59 PE9 bidirectional FT_ah2 I/O (5 V tolerant, analog option and group h2); alternate functions include TIM1_CH1, DFSDM1_CKOUT, UART7_RTS, OCTOSPIM_P1_IO6 and FMC_D6/FMC_DA6; additional functions OPAMP2_VINP and COMP2_INP.
60 PE10 bidirectional FT_ah2 I/O (5 V tolerant, analog option and group h2); alternate functions include TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, OCTOSPIM_P1_IO7 and FMC_D7/FMC_DA7; additional function COMP2_INM.
61 PE11 bidirectional FT_ah2 I/O (5 V tolerant, analog option and group h2); alternate functions include TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS, SAI2_SD_B, OCTOSPIM_P1_NCS, FMC_D8/FMC_DA8 and LCD_G3; additional function COMP2_INP.
62 PE12 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_DA9 and LCD_B4; additional function COMP1_OUT.
63 PE13 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_DA10 and LCD_DE; additional function COMP2_OUT.
64 PE14 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM1_CH4, SPI4_MOSI, SAI2_MCK_B, FMC_D11/FMC_DA11 and LCD_CLK.
65 PE15 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM1_BKIN, USART10_CK, FMC_D12/FMC_DA12 and LCD_R7; additional function TIM1_BKIN_COMP12.
66 PB10 bidirectional FT_f I/O (5 V tolerant, FM+ I2C option); alternate functions include TIM2_CH3, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, OCTOSPIM_P1_NCS, OTG_HS_ULPI_D3 and LCD_G4.
67 PB11 bidirectional FT_f I/O (5 V tolerant, FM+ I2C option); alternate functions include TIM2_CH4, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, OTG_HS_ULPI_D4 and LCD_G5.
68 VCAP power_out Core-voltage regulator output; connect to the external VCAP capacitor (Section 6.3.2).
69 VSS power_in Ground reference pin of the digital supply domain.
70 VDDLDO power_in Supply of the internal LDO regulator, 1.62 V minimum to 3.6 V maximum, not higher than VDD (Table 22).
71 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
72 PB12 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include TIM1_BKIN, OCTOSPIM_P1_NCLK, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, FDCAN2_RX, OTG_HS_ULPI_D5 and UART5_RX.
73 PB13 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TIM1_CH1N, LPTIM2_OUT, SPI2_SCK/I2S2_CK, USART3_CTS/USART3_NSS, FDCAN2_TX, OTG_HS_ULPI_D6, SDMMC1_D0 and UART5_TX.
74 PB14 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS, UART4_RTS, SDMMC2_D0 and LCD_CLK.
75 PB15 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, SDMMC2_D1 and LCD_G7.
76 PD8 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include DFSDM1_CKIN3, USART3_TX, SPDIFRX1_IN1 and FMC_D13/FMC_DA13.
77 PD9 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include DFSDM1_DATIN3, USART3_RX and FMC_D14/FMC_DA14.
78 PD10 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include DFSDM1_CKOUT, DFSDM2_CKOUT, USART3_CK, FMC_D15/FMC_DA15 and LCD_B3.
79 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
80 VSS power_in Ground reference pin of the digital supply domain.
81 PD11 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART3_NSS, OCTOSPIM_P1_IO0, SAI2_SD_A and FMC_A16/FMC_CLE.
82 PD12 bidirectional FT_fh2 I/O (5 V tolerant, FM+ I2C option and group h2); alternate functions include LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, USART3_RTS, OCTOSPIM_P1_IO1, SAI2_FS_A and FMC_A17/FMC_ALE.
83 PD13 bidirectional FT_fh2 I/O (5 V tolerant, FM+ I2C option and group h2); alternate functions include LPTIM1_OUT, TIM4_CH2, I2C4_SDA, OCTOSPIM_P1_IO3, SAI2_SCK_A, UART9_RTS and FMC_A18.
84 PD14 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM4_CH3, UART8_CTS, UART9_RX and FMC_D0/FMC_DA0.
85 PD15 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM4_CH4, UART8_RTS, UART9_TX and FMC_D1/FMC_DA1.
86 PG6 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM17_BKIN, OCTOSPIM_P1_NCS, FMC_NE3, DCMI_D12/PSSI_D12 and LCD_R7.
87 PG7 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include SAI1_MCLK_A, USART6_CK, OCTOSPIM_P2_DQS, FMC_INT, DCMI_D13/PSSI_D13 and LCD_CLK.
88 PG8 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include TIM8_ETR, SPI6_NSS/I2S6_WS, USART6_RTS, SPDIFRX1_IN2, FMC_SDCLK and LCD_G7.
89 VSS power_in Ground reference pin of the digital supply domain.
90 VDD50USB power_in Supply pin of the USB 5 V domain feeding the USB regulator (see USB regulator characteristics, Table 32).
91 VDD33USB power_in Standard operating supply of the USB domain, 3.0 V minimum to 3.6 V maximum when USB is used (Table 22).
92 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
93 PC6 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, I2S2_MCK, USART6_TX, FMC_NWAIT, SDMMC1_D6, DCMI_D0/PSSI_D0 and LCD_HSYNC.
94 PC7 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TRGIO, TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, I2S3_MCK, USART6_RX, FMC_NE1, SWPMI_TX, DCMI_D1/PSSI_D1 and LCD_G6.
95 PC8 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS, FMC_NE2/FMC_NCE, FMC_INT, SDMMC1_D0 and DCMI_D2/PSSI_D2.
96 PC9 bidirectional FT_fh0 I/O (5 V tolerant, FM+ I2C option and group h0); alternate functions include MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, OCTOSPIM_P1_IO0, SDMMC1_D1 and DCMI_D3/PSSI_D3.
97 PA8 bidirectional FT_fh0 I/O (5 V tolerant, FM+ I2C option and group h0); alternate functions include MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_HS_SOF, UART7_RX and LCD_R6.
98 PA9 bidirectional FT_u I/O (5 V tolerant, USB option supplied by VDD33USB); alternate functions include TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, DCMI_D0/PSSI_D0 and LCD_R5; additional function OTG_HS_VBUS.
99 PA10 bidirectional FT_u I/O (5 V tolerant, USB option supplied by VDD33USB); alternate functions include TIM1_CH3, LPUART1_RX, USART1_RX, OTG_HS_ID, MDIOS_MDIO, LCD_B4, DCMI_D1/PSSI_D1 and LCD_B1.
100 PA11 bidirectional FT_u I/O (5 V tolerant, USB option supplied by VDD33USB); alternate functions include TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX and LCD_R4; additional function OTG_HS_DM.
101 PA12 bidirectional FT_u I/O (5 V tolerant, USB option supplied by VDD33USB); alternate functions include TIM1_ETR, LPUART1_RTS, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS, SAI2_FS_B, FDCAN1_TX and LCD_R5; additional function OTG_HS_DP.
102 PA13(JTMS/SWDIO) bidirectional FT I/O (5 V tolerant) whose reset function is the JTMS/SWDIO serial-wire debug data pin.
103 VCAP power_out Core-voltage regulator output; connect to the external VCAP capacitor (Section 6.3.2).
104 VSS power_in Ground reference pin of the digital supply domain.
105 VDDLDO power_in Supply of the internal LDO regulator, 1.62 V minimum to 3.6 V maximum, not higher than VDD (Table 22).
106 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
107 PA14(JTCK/SWCLK) bidirectional FT I/O (5 V tolerant) whose reset function is the JTCK/SWCLK serial-wire debug clock pin.
108 PA15(JTDI) bidirectional FT I/O (5 V tolerant) whose reset function is the JTDI debug data input; alternate functions include TIM2_CH1/TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS/I2S6_WS, UART4_RTS, LCD_R3 and UART7_TX.
109 PC10 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include DFSDM1_CKIN5, DFSDM2_CKIN0, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPIM_P1_IO1, SWPMI_RX, SDMMC1_D2, DCMI_D8/PSSI_D8 and LCD_R2.
110 PC11 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include DFSDM1_DATIN5, DFSDM2_DATIN0, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPIM_P1_NCS, SDMMC1_D3, DCMI_D4/PSSI_D4 and LCD_B4.
111 PC12 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TRACED3, TIM15_CH1, DFSDM2_CKOUT, SPI6_SCK/I2S6_CK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9 and LCD_R6.
112 PD0 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include DFSDM1_CKIN6, UART4_RX, FDCAN1_RX, UART9_CTS, FMC_D2/FMC_DA2 and LCD_B1.
113 PD1 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include DFSDM1_DATIN6, UART4_TX, FDCAN1_TX and FMC_D3/FMC_DA3.
114 PD2 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, LCD_B7, SDMMC1_CMD, DCMI_D11/PSSI_D11 and LCD_B2.
115 PD3 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, USART2_CTS/USART2_NSS, FMC_CLK, DCMI_D5/PSSI_D5 and LCD_G7.
116 PD4 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include USART2_RTS, OCTOSPIM_P1_IO4 and FMC_NOE.
117 PD5 bidirectional FT_h1 I/O (5 V tolerant, group h1); alternate functions include USART2_TX, OCTOSPIM_P1_IO5 and FMC_NWE.
118 VSS power_in Ground reference pin of the digital supply domain.
119 VDDMMC power_in Supply for the independent MMC I/Os (secondary supply for _s pads), 1.62 V minimum to 3.6 V maximum; equal to VDD when not used (Table 22).
120 PD6 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include SAI1_D1, DFSDM1_DATIN1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, OCTOSPIM_P1_IO6, SDMMC2_CK, FMC_NWAIT, DCMI_D10/PSSI_D10 and LCD_B2.
121 PD7 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include DFSDM1_DATIN4, SPI1_MOSI/I2S1_SDO, DFSDM1_CKIN1, USART2_CK, SPDIFRX1_IN0, OCTOSPIM_P1_IO7, SDMMC2_CMD and FMC_NE1.
122 PG9 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include SPI1_MISO/I2S1_SDI, USART6_RX, SPDIFRX1_IN3, OCTOSPIM_P1_IO6, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE and DCMI_VSYNC/PSSI_RDY.
123 PG10 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include OCTOSPIM_P2_IO6, SPI1_NSS/I2S1_WS, LCD_G3, SAI2_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2/PSSI_D2 and LCD_B2.
124 PG11 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include LPTIM1_IN2, SPI1_SCK/I2S1_CK, SPDIFRX1_IN0, OCTOSPIM_P2_IO7, SDMMC2_D2, USART10_RX, DCMI_D3/PSSI_D3 and LCD_B3.
125 PG12 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include LPTIM1_IN1, OCTOSPIM_P2_NCS, SPI6_MISO/I2S6_SDI, USART6_RTS, SPDIFRX1_IN1, SDMMC2_D3, USART10_TX, FMC_NE4 and LCD_B1.
126 PG13 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include TRACED0, LPTIM1_OUT, SPI6_SCK/I2S6_CK, USART6_CTS/USART6_NSS, SDMMC2_D6, USART10_CTS/USART10_NSS, FMC_A24 and LCD_R0.
127 PG14 bidirectional FT_sh3 I/O (5 V tolerant, secondary supply VDDMMC); alternate functions include TRACED1, LPTIM1_ETR, SPI6_MOSI/I2S6_SDO, USART6_TX, OCTOSPIM_P1_IO7, SDMMC2_D7, USART10_RTS, FMC_A25 and LCD_B0.
128 VSS power_in Ground reference pin of the digital supply domain.
129 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).
130 PB3(JTDO/TRACESWO) bidirectional FT_h0 I/O (5 V tolerant, group h0) whose reset function is the JTDO/TRACESWO trace output; alternate functions include TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK/I2S6_CK, SDMMC2_D2, CRS_SYNC and UART7_RX.
131 PB4(NJTRST) bidirectional FT_h0 I/O (5 V tolerant, group h0) whose reset function is the NJTRST JTAG reset pin; alternate functions include TIM16_BKIN, TIM3_CH1, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO/I2S6_SDI, SDMMC2_D3 and UART7_TX.
132 PB5 bidirectional FT_h0 I/O (5 V tolerant, group h0); alternate functions include TIM17_BKIN, TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI/I2S6_SDO, FDCAN2_RX, OTG_HS_ULPI_D7, LCD_B5, FMC_SDCKE1, DCMI_D10/PSSI_D10 and UART5_RX.
133 PB6 bidirectional FT_f I/O (5 V tolerant, FM+ I2C option); alternate functions include TIM16_CH1N, TIM4_CH1, I2C1_SCL, HDMI_CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPIM_P1_NCS, DFSDM1_DATIN5, FMC_SDNE1, DCMI_D5/PSSI_D5 and UART5_TX.
134 PB7 bidirectional FT_fa I/O (5 V tolerant, FM+ I2C option and analog option); alternate functions include TIM17_CH1N, TIM4_CH2, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, DFSDM1_CKIN5, FMC_NL and DCMI_VSYNC/PSSI_RDY; additional function PVD_IN.
135 BOOT0 input Dedicated BOOT0 boot-mode selection input; the input voltage range is 0 V to 9 V (Table 22).
136 PB8 bidirectional FT_fsh3 I/O (5 V tolerant, FM+ I2C option, secondary supply VDDMMC); alternate functions include TIM16_CH1, TIM4_CH3, DFSDM1_CKIN7, I2C1_SCL, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, SDMMC1_D4 and DCMI_D6/PSSI_D6.
137 PB9 bidirectional FT_fsh3 I/O (5 V tolerant, FM+ I2C option, secondary supply VDDMMC); alternate functions include TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5 and DCMI_D7/PSSI_D7.
138 PE0 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include LPTIM1_ETR, TIM4_ETR, LPTIM2_ETR, UART8_RX, SAI2_MCK_A, FMC_NBL0, DCMI_D2/PSSI_D2 and LCD_R0.
139 PE1 bidirectional FT_h2 I/O (5 V tolerant, group h2); alternate functions include LPTIM1_IN2, UART8_TX, FMC_NBL1, DCMI_D3/PSSI_D3 and LCD_R6.
140 VCAP power_out Core-voltage regulator output; connect to the external VCAP capacitor (Section 6.3.2).
141 VSS power_in Ground reference pin of the digital supply domain.
142 PDR_ON input Control pin that switches the power-down reset (PDR) on or off; the PDR can only be switched off through this pin, and it is not available on all packages (Table 22 note 1).
143 VDDLDO power_in Supply of the internal LDO regulator, 1.62 V minimum to 3.6 V maximum, not higher than VDD (Table 22).
144 VDD power_in Standard operating supply, 1.62 V minimum to 3.6 V maximum (Table 22).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: STM32H7A3ZIT6Q
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: stm32h7a3zit6q-etched.step / stm32h7a3zit6q-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32h7a3zit6q.step / stm32h7a3zit6q.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (230 pp, sha256 1b145349083f63b4, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF