component
STM32H757XIH6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-265. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
5 files changed
+971−722
README.md+235−201@@ -9,235 +9,269 @@ STM32H757XIH6 from STMicroelectronics, in a TFBGA-265. Pinout and pin descriptio | Pin | Name | Type | Function | |---|---|---|---| | A1 | VSS | power_in | Ground supply pin for domain D1. |-| A2 | PI6 | output | Port I pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A3 | PI5 | output | Port I pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A4 | PI4 | output | Port I pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A5 | PB5 | output | Port B pin 5, I/O with 5V tolerant I/O structure. |+| A2 | PI6 | bidirectional | Port I pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A3 | PI5 | bidirectional | Port I pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A4 | PI4 | bidirectional | Port I pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A5 | PB5 | bidirectional | Port B pin 5, I/O with 5V tolerant I/O structure. | | A6 | VDDLDO | power_in | Supply voltage output from embedded LDO regulator. |-| A7 | VCAP | passive | External capacitor connection pin for main regulator stabilization. |-| A8 | PK5 | output | Port K pin 5, I/O for LCD display control. |-| A9 | PG10 | output | Port G pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A10 | PG9 | output | Port G pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A11 | PD5 | output | Port D pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A12 | PD4 | output | Port D pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A13 | PC10 | output | Port C pin 10, I/O with 5V tolerant high-speed and analog I/O structure. |-| A14 | PA15 | output | Port A pin 15 JTDI, I/O with 5V tolerant I/O structure, JTAG debug interface. |-| A15 | PI1 | output | Port I pin 1, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| A16 | PI0 | output | Port I pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A7 | VCAP | power_in | External capacitor connection pin for main regulator stabilization. |+| A8 | PK5 | bidirectional | Port K pin 5, I/O for LCD display control. |+| A9 | PG10 | bidirectional | Port G pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. | | B1 | VBAT | power_in | Battery supply pin for backup domain and VBAT charging, 1.2 to 3.6 V. |-| B3 | PI7 | output | Port I pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B4 | PE1 | output | Port E pin 1, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B5 | PB6 | output | Port B pin 6, I/O with 5V tolerant and FM+ I/O structure. |+| B2 | VSS | power_in | Ground supply pin. |+| B3 | PI7 | bidirectional | Port I pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B4 | PE1 | bidirectional | Port E pin 1, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B5 | PB6 | bidirectional | Port B pin 6, I/O with 5V tolerant and FM+ I/O structure. | | B6 | VSS | power_in | Ground supply pin. |-| B7 | PB4 | output | Port B pin 4 NJTRST, I/O with 5V tolerant I/O structure, JTAG interface. |-| B8 | PK4 | output | Port K pin 4, I/O for LCD display control. |-| B9 | PG11 | output | Port G pin 11, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B10 | PJ15 | output | Port J pin 15, I/O for LCD display control. |-| B11 | PD6 | output | Port D pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B12 | PD3 | output | Port D pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B13 | PC11 | output | Port C pin 11, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B14 | PA14 | output | Port A pin 14 JTCK/SWCLK, I/O with 5V tolerant I/O structure, debug interface. |-| B15 | PI2 | output | Port I pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B16 | PH15 | output | Port H pin 15, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| B17 | PH14 | output | Port H pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| C1 | PC15-OSC32_OUT | output | Port C pin 15 OSC32_OUT, I/O with 5V tolerant I/O structure, 32 kHz oscillator output. |-| C2 | PC14-OSC32_IN | input | Port C pin 14 OSC14_IN, I/O with 5V tolerant I/O structure, 32 kHz oscillator input. |-| C3 | PE2 | output | Port E pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| C4 | PE0 | output | Port E pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| C5 | PB7 | output | Port B pin 7, I/O with 5V tolerant FM+ and analog I/O structure. |-| C6 | PB3 | output | Port B pin 3 JTDO/TRACESWO, I/O with 5V tolerant I/O structure, JTAG trace interface. |-| C7 | PK6 | output | Port K pin 6, I/O for LCD display control. |-| C8 | PK3 | output | Port K pin 3, I/O for LCD display control. |-| C9 | PG12 | output | Port G pin 12, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| C10 | VSS | power_in | Ground supply pin. |-| C11 | PD7 | output | Port D pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| C12 | PC12 | output | Port C pin 12, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| C13 | VSS | power_in | Ground supply pin. |-| C14 | PI3 | output | Port I pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| C15 | PA12 | output | Port A pin 12, I/O with 5V tolerant and USB I/O structure. |-| C16 | VSS | power_in | Ground supply pin. |-| C17 | PA13 | output | Port A pin 13 JTMS/SWDIO, I/O with 5V tolerant I/O structure, debug interface. |-| D1 | PE5 | output | Port E pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D2 | PE4 | output | Port E pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D3 | PE3 | output | Port E pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D4 | PB9 | output | Port B pin 9, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| D5 | PB8 | output | Port B pin 8, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| D6 | PG15 | output | Port G pin 15, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D7 | PK7 | output | Port K pin 7, I/O for LCD display control. |-| D8 | PG14 | output | Port G pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D9 | PG13 | output | Port G pin 13, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D10 | PJ14 | output | Port J pin 14, I/O for LCD display control. |-| D11 | PJ12 | output | Port J pin 12, I/O for LCD display control. |-| D12 | PD2 | output | Port D pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D13 | PD0 | output | Port D pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D14 | PA10 | output | Port A pin 10, I/O with 5V tolerant and USB I/O structure. |-| D15 | PA9 | output | Port A pin 9, I/O with 5V tolerant and USB I/O structure. |-| D16 | PH13 | output | Port H pin 13, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| D17 | VCAP | passive | External capacitor connection pin for main regulator stabilization. |-| E1 | VLXSMPS | passive | SMPS step-down converter switching node, inductor connection pin. |-| E2 | PI9 | output | Port I pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| E3 | PC13 | output | Port C pin 13, I/O with 5V tolerant I/O structure, RTC tamper/wakeup. |-| E4 | PI8 | output | Port I pin 8, I/O with 5V tolerant I/O structure, RTC tamper/wakeup. |-| E5 | PE6 | output | Port E pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B7 | PB4 (NJTRST) | bidirectional | Port B pin 4 NJTRST, I/O with 5V tolerant I/O structure, JTAG interface. |+| B8 | PK4 | bidirectional | Port K pin 4, I/O for LCD display control. |+| B9 | PG11 | bidirectional | Port G pin 11, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| C1 | PC15-OSC32_OUT (OSC32_OUT) | bidirectional | Port C pin 15 OSC32_OUT, I/O with 5V tolerant I/O structure, 32 kHz oscillator output. |+| C2 | PC14-OSC32_IN (OSC32_IN) | bidirectional | Port C pin 14 OSC14_IN, I/O with 5V tolerant I/O structure, 32 kHz oscillator input. |+| C3 | PE2 | bidirectional | Port E pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| C4 | PE0 | bidirectional | Port E pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| C5 | PB7 | bidirectional | Port B pin 7, I/O with 5V tolerant FM+ and analog I/O structure. |+| C6 | PB3 (JTDO/TRACESWO) | bidirectional | Port B pin 3 JTDO/TRACESWO, I/O with 5V tolerant I/O structure, JTAG trace interface. |+| C7 | PK6 | bidirectional | Port K pin 6, I/O for LCD display control. |+| C8 | PK3 | bidirectional | Port K pin 3, I/O for LCD display control. |+| C9 | PG12 | bidirectional | Port G pin 12, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D1 | PE5 | bidirectional | Port E pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D2 | PE4 | bidirectional | Port E pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D3 | PE3 | bidirectional | Port E pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D4 | PB9 | bidirectional | Port B pin 9, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| D5 | PB8 | bidirectional | Port B pin 8, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| D6 | PG15 | bidirectional | Port G pin 15, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D7 | PK7 | bidirectional | Port K pin 7, I/O for LCD display control. |+| D8 | PG14 | bidirectional | Port G pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D9 | PG13 | bidirectional | Port G pin 13, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| E1 | VLXSMPS | power_in | SMPS step-down converter switching node, inductor connection pin. |+| E2 | PI9 | bidirectional | Port I pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| E3 | PC13 | bidirectional | Port C pin 13, I/O with 5V tolerant I/O structure, RTC tamper/wakeup. |+| E4 | PI8 | bidirectional | Port I pin 8, I/O with 5V tolerant I/O structure, RTC tamper/wakeup. |+| E5 | PE6 | bidirectional | Port E pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. | | E6 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| E7 | PDR_ON | power_in | | | E8 | BOOT0 | input | Boot pin (VPP), selects boot mode from Flash or system memory. | | E9 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| E10 | PJ13 | output | Port J pin 13, I/O for LCD display control. |-| E11 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| E12 | PD1 | output | Port D pin 1, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| E13 | PC8 | output | Port C pin 8, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| E14 | PC9 | output | Port C pin 9, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| E15 | PA8 | output | Port A pin 8, I/O with 5V tolerant FM+, high-speed and analog I/O structure. |-| E16 | PA11 | output | Port A pin 11, I/O with 5V tolerant and USB I/O structure. |-| E17 | PA10 | output | Port A pin 10, I/O with 5V tolerant and USB I/O structure. | | F1 | VDDSMPS | power_in | SMPS step-down converter power supply input pin. | | F2 | VSSSMPS | power_in | SMPS step-down converter ground return pin. |-| F3 | PI10 | output | Port I pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| F4 | PI11 | output | Port I pin 11, I/O with 5V tolerant I/O structure, USB wakeup. |+| F3 | PI10 | bidirectional | Port I pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| F4 | PI11 | bidirectional | Port I pin 11, I/O with 5V tolerant I/O structure, USB wakeup. | | F5 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| F13 | PC7 | output | Port C pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| F14 | PC6 | output | Port C pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| F15 | PG8 | output | Port G pin 8, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| F16 | PG7 | output | Port G pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| F17 | VDD50USB | power_in | USB 5V tolerant I/O power supply pin. |-| G1 | PF2 | output | Port F pin 2, I/O with 5V tolerant FM+ I/O structure. |-| G2 | VFBSMPS | passive | SMPS step-down converter feedback network connection pin. |-| G3 | PF1 | output | Port F pin 1, I/O with 5V tolerant FM+ I/O structure. |-| G4 | PF0 | output | Port F pin 0, I/O with 5V tolerant FM+ I/O structure. |+| G1 | PF2 | bidirectional | Port F pin 2, I/O with 5V tolerant FM+ I/O structure. |+| G2 | VFBSMPS | power_in | SMPS step-down converter feedback network connection pin. |+| G3 | PF1 | bidirectional | Port F pin 1, I/O with 5V tolerant FM+ I/O structure. |+| G4 | PF0 | bidirectional | Port F pin 0, I/O with 5V tolerant FM+ I/O structure. | | G5 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| G13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| G14 | PG5 | output | Port G pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| G15 | PG6 | output | Port G pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| G17 | VDD33USB | power_in | USB 3.3V power supply pin. |-| H1 | PI12 | output | Port I pin 12, I/O with 5V tolerant I/O structure. |-| H2 | PI13 | output | Port I pin 13, I/O with 5V tolerant I/O structure. |-| H3 | PI14 | output | Port I pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| H4 | PF3 | output | Port F pin 3, I/O with 5V tolerant FM+ and analog I/O structure. |+| G7 | VSS | power_in | Ground supply pin. |+| G8 | VSS | power_in | Ground supply pin. |+| G9 | VSS | power_in | Ground supply pin. |+| H1 | PI12 | bidirectional | Port I pin 12, I/O with 5V tolerant I/O structure. |+| H2 | PI13 | bidirectional | Port I pin 13, I/O with 5V tolerant I/O structure. |+| H3 | PI14 | bidirectional | Port I pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| H4 | PF3 | bidirectional | Port F pin 3, I/O with 5V tolerant FM+ and analog I/O structure. | | H5 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| H13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| H14 | PG4 | output | Port G pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| H15 | PG3 | output | Port G pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| H16 | PG2 | output | Port G pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| H17 | PK2 | output | Port K pin 2, I/O for LCD display control. |-| J1 | PH1-OSC_OUT | output | Port H pin 1 OSC_OUT, I/O with 5V tolerant I/O structure, oscillator output. |-| J2 | PH0-OSC_IN | input | Port H pin 0 OSC_IN, I/O with 5V tolerant I/O structure, oscillator input. |+| H7 | VSS | power_in | Ground supply pin. |+| H8 | VSS | power_in | Ground supply pin. |+| H9 | VSS | power_in | Ground supply pin. |+| J1 | PH1-OSC_OUT (PH1) | bidirectional | Port H pin 1 OSC_OUT, I/O with 5V tolerant I/O structure, oscillator output. |+| J2 | PH0-OSC_IN (PH0) | bidirectional | Port H pin 0 OSC_IN, I/O with 5V tolerant I/O structure, oscillator input. | | J3 | VSS | power_in | Ground supply pin. |-| J4 | PF5 | output | Port F pin 5, I/O with 5V tolerant FM+ and analog I/O structure. |-| J5 | PF4 | output | Port F pin 4, I/O with 5V tolerant FM+ and analog I/O structure. |+| J4 | PF5 | bidirectional | Port F pin 5, I/O with 5V tolerant FM+ and analog I/O structure. |+| J5 | PF4 | bidirectional | Port F pin 4, I/O with 5V tolerant FM+ and analog I/O structure. |+| J7 | VSS | power_in | Ground supply pin. |+| J8 | VSS | power_in | Ground supply pin. |+| J9 | VSS | power_in | Ground supply pin. |+| K1 | NRST | input | Reset pin with embedded pull-up resistor, bidirectional reset interface. |+| K2 | PF6 | bidirectional | Port F pin 6, I/O with 5V tolerant FM+ and analog I/O structure. |+| K3 | PF7 | bidirectional | Port F pin 7, I/O with 5V tolerant FM+ and analog I/O structure. |+| K4 | PF8 | bidirectional | Port F pin 8, I/O with 5V tolerant FM+ and analog I/O structure. |+| K5 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| K7 | VSS | power_in | Ground supply pin. |+| K8 | VSS | power_in | Ground supply pin. |+| K9 | VSS | power_in | Ground supply pin. |+| L1 | VDDA | power_in | Analog power supply pin for ADCs, DACs, comparators and operational amplifiers. |+| L2 | PC0 | bidirectional | Port C pin 0, I/O with 5V tolerant and analog I/O structure. |+| L3 | PF10 | bidirectional | Port F pin 10, I/O with 5V tolerant FM+ and analog I/O structure. |+| L4 | PF9 | bidirectional | Port F pin 9, I/O with 5V tolerant FM+ and analog I/O structure. |+| L5 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| L7 | VSS | power_in | Ground supply pin. |+| L8 | VSS | power_in | Ground supply pin. |+| L9 | VSS | power_in | Ground supply pin. |+| M1 | VREF+ | power_in | Reference voltage output for analog peripherals, ADCs and DACs. |+| M2 | PC1 | bidirectional | Port C pin 1, I/O with 5V tolerant FM+ and analog I/O structure. |+| M3 | PC2 | bidirectional | Port C pin 2, I/O with 5V tolerant and analog I/O structure. |+| M4 | PC3 | bidirectional | Port C pin 3, I/O with 5V tolerant and analog I/O structure. |+| M5 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| N1 | VREF- | power_in | Reference voltage negative, ground reference for analog peripherals. |+| N2 | PH2 | bidirectional | Port H pin 2, I/O with 5V tolerant FM+ and analog I/O structure. |+| N3 | PA2 | bidirectional | Port A pin 2, I/O with 5V tolerant and analog I/O structure. |+| N4 | PA1 | bidirectional | Port A pin 1, I/O with 5V tolerant FM+ and analog I/O structure. |+| N5 | PA0 | bidirectional | Port A pin 0, I/O with 5V tolerant and analog I/O structure. |+| N6 | PJ0 | bidirectional | Port J pin 0, I/O for LCD display control. |+| N7 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| N8 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| N9 | PE10 | bidirectional | Port E pin 10, I/O with 5V tolerant FM+ and analog I/O structure. |+| P1 | VSSA | power_in | Ground supply pin for analog circuits. |+| P2 | PH3 | bidirectional | Port H pin 3, I/O with 5V tolerant FM+ and analog I/O structure. |+| P3 | PH4 | bidirectional | Port H pin 4, I/O with 5V tolerant FM+ and analog I/O structure. |+| P4 | PH5 | bidirectional | Port H pin 5, I/O with 5V tolerant FM+ and analog I/O structure. |+| P5 | PI15 | bidirectional | Port I pin 15, I/O with 5V tolerant I/O structure. |+| P6 | PJ1 | bidirectional | Port J pin 1, I/O for LCD display control. |+| P7 | PF13 | bidirectional | Port F pin 13, I/O with 5V tolerant FM+ and analog I/O structure. |+| P8 | PF14 | bidirectional | Port F pin 14, I/O with 5V tolerant FM+ and analog I/O structure. |+| P9 | PE9 | bidirectional | Port E pin 9, I/O with 5V tolerant FM+ and analog I/O structure. |+| R1 | PC2_C | bidirectional | Port C pin 2 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |+| R2 | PC3_C | bidirectional | Port C pin 3 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |+| R3 | PA6 | bidirectional | Port A pin 6, I/O with 5V tolerant and analog I/O structure. |+| R4 | VSS | power_in | Ground supply pin. |+| R5 | PA7 | bidirectional | Port A pin 7, I/O with 3.3V tolerant and analog I/O structure. |+| R6 | PB2 | bidirectional | Port B pin 2, I/O with 5V tolerant FM+ and analog I/O structure. |+| R7 | PF12 | bidirectional | Port F pin 12, I/O with 5V tolerant FM+ and analog I/O structure. |+| R8 | VSS | power_in | Ground supply pin. |+| R9 | PF15 | bidirectional | Port F pin 15, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| T1 | PA0_C | bidirectional | Port A pin 0 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |+| T2 | PA1_C | bidirectional | Port A pin 1 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |+| T3 | PA5 | bidirectional | Port A pin 5, I/O with 3.3V tolerant FM+ and analog I/O structure. |+| T4 | PC4 | bidirectional | Port C pin 4, I/O with 3.3V tolerant and analog I/O structure. |+| T5 | PB1 | bidirectional | Port B pin 1, I/O with 3.3V tolerant and USB I/O structure. |+| T6 | PJ2 | bidirectional | Port J pin 2, I/O for LCD display control. |+| T7 | PF11 | bidirectional | Port F pin 11, I/O with 5V tolerant and analog I/O structure. |+| T8 | PG0 | bidirectional | Port G pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| T9 | PE8 | bidirectional | Port E pin 8, I/O with 3.3V tolerant FM+ and analog I/O structure. |+| U1 | VSS | power_in | Ground supply pin. |+| U2 | PA3 | bidirectional | Port A pin 3, I/O with 5V tolerant FM+ and analog I/O structure. |+| U3 | PA4 | bidirectional | Port A pin 4, I/O with 3.3V tolerant and analog I/O structure. |+| U4 | PC5 | bidirectional | Port C pin 5, I/O with 3.3V tolerant and analog I/O structure. |+| U5 | PB0 | bidirectional | Port B pin 0, I/O with 5V tolerant and analog I/O structure. |+| U6 | PJ3 | bidirectional | Port J pin 3, I/O for LCD display control. |+| U7 | PJ4 | bidirectional | Port J pin 4, I/O for LCD display control. |+| U8 | PG1 | bidirectional | Port G pin 1, I/O with 3.3V tolerant high-speed low-voltage I/O structure. |+| U9 | PE7 | bidirectional | Port E pin 7, I/O with 3.3V tolerant FM+ and analog I/O structure. |+| A10 | PG9 | bidirectional | Port G pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A11 | PD5 | bidirectional | Port D pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A12 | PD4 | bidirectional | Port D pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A13 | PC10 | bidirectional | Port C pin 10, I/O with 5V tolerant high-speed and analog I/O structure. |+| A14 | PA15 (JTDI) | bidirectional | Port A pin 15 JTDI, I/O with 5V tolerant I/O structure, JTAG debug interface. |+| A15 | PI1 | bidirectional | Port I pin 1, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A16 | PI0 | bidirectional | Port I pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| A17 | VSS | power_in | Ground supply pin. |+| B10 | PJ15 | bidirectional | Port J pin 15, I/O for LCD display control. |+| B11 | PD6 | bidirectional | Port D pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B12 | PD3 | bidirectional | Port D pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B13 | PC11 | bidirectional | Port C pin 11, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B14 | PA14 (JTCK/SWCLK) | bidirectional | Port A pin 14 JTCK/SWCLK, I/O with 5V tolerant I/O structure, debug interface. |+| B15 | PI2 | bidirectional | Port I pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B16 | PH15 | bidirectional | Port H pin 15, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| B17 | PH14 | bidirectional | Port H pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| C10 | VSS | power_in | Ground supply pin. |+| C11 | PD7 | bidirectional | Port D pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| C12 | PC12 | bidirectional | Port C pin 12, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| C13 | VSS | power_in | Ground supply pin. |+| C14 | PI3 | bidirectional | Port I pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| C15 | PA13 (JTMS/SWDIO) | bidirectional | |+| C16 | VSS | power_in | Ground supply pin. |+| C17 | VDDLDO | power_in | Supply voltage output from embedded LDO regulator. |+| D10 | PJ14 | bidirectional | Port J pin 14, I/O for LCD display control. |+| D11 | PJ12 | bidirectional | Port J pin 12, I/O for LCD display control. |+| D12 | PD2 | bidirectional | Port D pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D13 | PD0 | bidirectional | Port D pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D14 | PA10 | bidirectional | Port A pin 10, I/O with 5V tolerant and USB I/O structure. |+| D15 | PA9 | bidirectional | Port A pin 9, I/O with 5V tolerant and USB I/O structure. |+| D16 | PH13 | bidirectional | Port H pin 13, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| D17 | VCAP | power_in | External capacitor connection pin for main regulator stabilization. |+| E10 | PJ13 | bidirectional | Port J pin 13, I/O for LCD display control. |+| E11 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| E12 | PD1 | bidirectional | Port D pin 1, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| E13 | PC8 | bidirectional | Port C pin 8, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| E14 | PC9 | bidirectional | Port C pin 9, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| E15 | PA8 | bidirectional | Port A pin 8, I/O with 5V tolerant FM+, high-speed and analog I/O structure. |+| E16 | PA12 | bidirectional | Port A pin 12, I/O with 5V tolerant and USB I/O structure. |+| E17 | PA11 | bidirectional | Port A pin 11, I/O with 5V tolerant and USB I/O structure. |+| F13 | PC7 | bidirectional | Port C pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| F14 | PC6 | bidirectional | Port C pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| F15 | PG8 | bidirectional | Port G pin 8, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| F16 | PG7 | bidirectional | Port G pin 7, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| F17 | VDD33_USB | power_in | USB 3.3V power supply pin. |+| G10 | VSS | power_in | Ground supply pin. |+| G11 | VSS | power_in | Ground supply pin. |+| G13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| G14 | PG5 | bidirectional | Port G pin 5, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| G15 | PG6 | bidirectional | Port G pin 6, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| G16 | VSS | power_in | Ground supply pin. |+| G17 | VDD50_USB | power_in | USB 5V tolerant I/O power supply pin. |+| H10 | VSS | power_in | Ground supply pin. |+| H11 | VSS | power_in | Ground supply pin. |+| H13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| H14 | PG4 | bidirectional | Port G pin 4, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| H15 | PG3 | bidirectional | Port G pin 3, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| H16 | PG2 | bidirectional | Port G pin 2, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| H17 | PK2 | bidirectional | Port K pin 2, I/O for LCD display control. |+| J10 | VSS | power_in | Ground supply pin. |+| J11 | VSS | power_in | Ground supply pin. | | J13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| J14 | PK0 | output | Port K pin 0, I/O for LCD display control. |-| J15 | PK1 | output | Port K pin 1, I/O for LCD display control. |+| J14 | PK0 | bidirectional | Port K pin 0, I/O for LCD display control. |+| J15 | PK1 | bidirectional | Port K pin 1, I/O for LCD display control. | | J16 | VSS | power_in | Ground supply pin. | | J17 | VSS | power_in | Ground supply pin. |-| K1 | NRST | bidirectional | Reset pin with embedded pull-up resistor, bidirectional reset interface. |-| K2 | PF6 | output | Port F pin 6, I/O with 5V tolerant FM+ and analog I/O structure. |-| K3 | PF7 | output | Port F pin 7, I/O with 5V tolerant FM+ and analog I/O structure. |-| K4 | PF8 | output | Port F pin 8, I/O with 5V tolerant FM+ and analog I/O structure. |+| K10 | VSS | power_in | Ground supply pin. |+| K11 | VSS | power_in | Ground supply pin. | | K13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| K14 | PJ11 | output | Port J pin 11, I/O for LCD display control. |+| K14 | PJ11 | bidirectional | Port J pin 11, I/O for LCD display control. | | K15 | VSSDSI | power_in | DSI host ground supply pin. |-| K16 | DSI_D1P | output | DSI host data lane 1 positive signal line, differential pair. |-| K17 | DSI_D1N | output | DSI host data lane 1 negative signal line, differential pair. |-| L1 | VDDA | power_in | Analog power supply pin for ADCs, DACs, comparators and operational amplifiers. |-| L2 | PC0 | output | Port C pin 0, I/O with 5V tolerant and analog I/O structure. |-| L3 | PF10 | output | Port F pin 10, I/O with 5V tolerant FM+ and analog I/O structure. |-| L4 | PF9 | output | Port F pin 9, I/O with 5V tolerant FM+ and analog I/O structure. |-| L5 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |+| K16 | DSI_D1P | bidirectional | DSI host data lane 1 positive signal line, differential pair. |+| K17 | DSI_D1N | bidirectional | DSI host data lane 1 negative signal line, differential pair. |+| L10 | VSS | power_in | Ground supply pin. |+| L11 | VSS | power_in | Ground supply pin. | | L13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| L14 | PJ10 | output | Port J pin 10, I/O for LCD display control. |+| L14 | PJ10 | bidirectional | Port J pin 10, I/O for LCD display control. | | L15 | VSSDSI | power_in | DSI host ground supply pin. |-| L16 | DSI_CKP | output | DSI host clock lane positive signal line, differential pair. |-| L17 | DSI_CKN | output | DSI host clock lane negative signal line, differential pair. |-| M1 | VREF+ | power_in | Reference voltage output for analog peripherals, ADCs and DACs. |-| M2 | PC1 | output | Port C pin 1, I/O with 5V tolerant FM+ and analog I/O structure. |-| M3 | PC2 | output | Port C pin 2, I/O with 5V tolerant and analog I/O structure. |-| M4 | PC3 | output | Port C pin 3, I/O with 5V tolerant and analog I/O structure. |+| L16 | DSI_CKP | bidirectional | DSI host clock lane positive signal line, differential pair. |+| L17 | DSI_CKN | bidirectional | DSI host clock lane negative signal line, differential pair. | | M13 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| M14 | PJ9 | output | Port J pin 9, I/O for LCD display control. |+| M14 | PJ9 | bidirectional | Port J pin 9, I/O for LCD display control. | | M15 | VSSDSI | power_in | DSI host ground supply pin. |-| M16 | DSI_D0P | output | DSI host data lane 0 positive signal line, differential pair. |-| M17 | DSI_D0N | output | DSI host data lane 0 negative signal line, differential pair. |-| N1 | VREF- | power_in | Reference voltage negative, ground reference for analog peripherals. |-| N2 | PH2 | output | Port H pin 2, I/O with 5V tolerant FM+ and analog I/O structure. |-| N3 | PA2 | output | Port A pin 2, I/O with 5V tolerant and analog I/O structure. |-| N4 | PA1 | output | Port A pin 1, I/O with 5V tolerant FM+ and analog I/O structure. |-| N5 | PA0 | output | Port A pin 0, I/O with 5V tolerant and analog I/O structure. |-| N6 | PJ0 | output | Port J pin 0, I/O for LCD display control. |-| N7 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| N8 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| N9 | PE10 | output | Port E pin 10, I/O with 5V tolerant FM+ and analog I/O structure. |+| M16 | DSI_D0P | bidirectional | DSI host data lane 0 positive signal line, differential pair. |+| M17 | DSI_D0N | bidirectional | DSI host data lane 0 negative signal line, differential pair. | | N10 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. | | N11 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. | | N12 | VDD | power_in | Main positive power supply pin, 1.62 to 3.6 V. |-| N13 | PJ8 | output | Port J pin 8, I/O for LCD display control. |-| N14 | PJ7 | output | Port J pin 7, I/O for LCD display control. |-| N15 | PJ6 | output | Port J pin 6, I/O for LCD display control. |+| N13 | PJ8 | bidirectional | Port J pin 8, I/O for LCD display control. |+| N14 | PJ7 | bidirectional | Port J pin 7, I/O for LCD display control. |+| N15 | PJ6 | bidirectional | Port J pin 6, I/O for LCD display control. | | N16 | VSS | power_in | Ground supply pin. |-| N17 | VCAPDSI | passive | External capacitor connection pin for DSI regulator stabilization. |-| P1 | VSSA | power_in | Ground supply pin for analog circuits. |-| P2 | PH3 | output | Port H pin 3, I/O with 5V tolerant FM+ and analog I/O structure. |-| P3 | PH4 | output | Port H pin 4, I/O with 5V tolerant FM+ and analog I/O structure. |-| P4 | PH5 | output | Port H pin 5, I/O with 5V tolerant FM+ and analog I/O structure. |-| P5 | PI15 | output | Port I pin 15, I/O with 5V tolerant I/O structure. |-| P6 | PJ1 | output | Port J pin 1, I/O for LCD display control. |-| P7 | PF13 | output | Port F pin 13, I/O with 5V tolerant FM+ and analog I/O structure. |-| P8 | PF14 | output | Port F pin 14, I/O with 5V tolerant FM+ and analog I/O structure. |-| P9 | PE9 | output | Port E pin 9, I/O with 5V tolerant FM+ and analog I/O structure. |-| P10 | PE11 | output | Port E pin 11, I/O with 5V tolerant FM+ and analog I/O structure. |-| P11 | PB10 | output | Port B pin 10, I/O with 5V tolerant FM+ I/O structure. |-| P12 | PB11 | output | Port B pin 11, I/O with 5V tolerant FM+ I/O structure. |-| P13 | PH10 | output | Port H pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| P14 | PH11 | output | Port H pin 11, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| P15 | PD15 | output | Port D pin 15, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| P16 | PD14 | output | Port D pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| N17 | VCAPDSI | power_in | External capacitor connection pin for DSI regulator stabilization. |+| P10 | PE11 | bidirectional | Port E pin 11, I/O with 5V tolerant FM+ and analog I/O structure. |+| P11 | PB10 | bidirectional | Port B pin 10, I/O with 5V tolerant FM+ I/O structure. |+| P12 | PB11 | bidirectional | Port B pin 11, I/O with 5V tolerant FM+ I/O structure. |+| P13 | PH10 | bidirectional | Port H pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| P14 | PH11 | bidirectional | Port H pin 11, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| P15 | PD15 | bidirectional | Port D pin 15, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| P16 | PD14 | bidirectional | Port D pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. | | P17 | VDDDSI | power_in | DSI host power supply pin. |-| R1 | PC2_C | output | Port C pin 2 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |-| R2 | PC3_C | output | Port C pin 3 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |-| R3 | PA6 | output | Port A pin 6, I/O with 5V tolerant and analog I/O structure. |-| R4 | VSS | power_in | Ground supply pin. |-| R5 | PA7 | output | Port A pin 7, I/O with 3.3V tolerant and analog I/O structure. |-| R6 | PB2 | output | Port B pin 2, I/O with 5V tolerant FM+ and analog I/O structure. |-| R7 | PF12 | output | Port F pin 12, I/O with 5V tolerant FM+ and analog I/O structure. |-| R8 | VSS | power_in | Ground supply pin. |-| R9 | PF15 | output | Port F pin 15, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| R13 | PH9 | output | Port H pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| R14 | PH12 | output | Port H pin 12, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| R15 | PD11 | output | Port D pin 11, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| R16 | PD12 | output | Port D pin 12, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| R17 | PD13 | output | Port D pin 13, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |-| T1 | PA0_C | output | Port A pin 0 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |-| T2 | PA1_C | output | Port A pin 1 Complementary pad, analog-only I/O with 3.3V tolerant and analog structure. |-| T3 | PA5 | output | Port A pin 5, I/O with 3.3V tolerant FM+ and analog I/O structure. |-| T4 | PC4 | output | Port C pin 4, I/O with 3.3V tolerant and analog I/O structure. |-| T5 | PB1 | output | Port B pin 1, I/O with 3.3V tolerant and USB I/O structure. |-| T6 | PJ2 | output | Port J pin 2, I/O for LCD display control. |-| T7 | PF11 | output | Port F pin 11, I/O with 5V tolerant and analog I/O structure. |-| T8 | PG0 | output | Port G pin 0, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| T9 | PE8 | output | Port E pin 8, I/O with 3.3V tolerant FM+ and analog I/O structure. |-| T10 | PE13 | output | Port E pin 13, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| T11 | PH6 | output | Port H pin 6, I/O with 5V tolerant I/O structure. |+| R10 | PE12 | bidirectional | |+| R11 | PE15 | bidirectional | |+| R12 | PJ5 | bidirectional | |+| R13 | PH9 | bidirectional | Port H pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| R14 | PH12 | bidirectional | Port H pin 12, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| R15 | PD11 | bidirectional | Port D pin 11, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| R16 | PD12 | bidirectional | Port D pin 12, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| R17 | PD13 | bidirectional | Port D pin 13, I/O with 5V tolerant FM+ and high-speed low-voltage I/O structure. |+| T10 | PE13 | bidirectional | Port E pin 13, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| T11 | PH6 | bidirectional | Port H pin 6, I/O with 5V tolerant I/O structure. | | T12 | VSS | power_in | Ground supply pin. |-| T13 | PH8 | output | Port H pin 8, I/O with 5V tolerant FM+ and analog I/O structure. |-| T14 | PB12 | output | Port B pin 12, I/O with 5V tolerant and USB I/O structure. |-| T15 | PB15 | output | Port B pin 15, I/O with 5V tolerant and USB I/O structure. |-| T16 | PD10 | output | Port D pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| T17 | PD9 | output | Port D pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| U1 | VSS | power_in | Ground supply pin. |-| U2 | PA3 | output | Port A pin 3, I/O with 5V tolerant FM+ and analog I/O structure. |-| U3 | PA4 | output | Port A pin 4, I/O with 3.3V tolerant and analog I/O structure. |-| U4 | PC5 | output | Port C pin 5, I/O with 3.3V tolerant and analog I/O structure. |-| U5 | PB0 | output | Port B pin 0, I/O with 5V tolerant and analog I/O structure. |-| U6 | PJ3 | output | Port J pin 3, I/O for LCD display control. |-| U7 | PJ4 | output | Port J pin 4, I/O for LCD display control. |-| U8 | PG1 | output | Port G pin 1, I/O with 3.3V tolerant high-speed low-voltage I/O structure. |-| U9 | PE7 | output | Port E pin 7, I/O with 3.3V tolerant FM+ and analog I/O structure. |-| U10 | PE14 | output | Port E pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |-| U11 | VCAP | passive | External capacitor connection pin for main regulator stabilization. |+| T13 | PH8 | bidirectional | Port H pin 8, I/O with 5V tolerant FM+ and analog I/O structure. |+| T14 | PB12 | bidirectional | Port B pin 12, I/O with 5V tolerant and USB I/O structure. |+| T15 | PB15 | bidirectional | Port B pin 15, I/O with 5V tolerant and USB I/O structure. |+| T16 | PD10 | bidirectional | Port D pin 10, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| T17 | PD9 | bidirectional | Port D pin 9, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| U10 | PE14 | bidirectional | Port E pin 14, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| U11 | VCAP | power_in | External capacitor connection pin for main regulator stabilization. | | U12 | VDDLDO | power_in | Supply voltage output from embedded LDO regulator. |-| U13 | PH7 | output | Port H pin 7, I/O with 5V tolerant FM+ and analog I/O structure. |-| U14 | PB13 | output | Port B pin 13, I/O with 5V tolerant and USB I/O structure, USB VBUS monitoring. |-| U15 | PB14 | output | Port B pin 14, I/O with 5V tolerant and USB I/O structure. |-| U16 | PD8 | output | Port D pin 8, I/O with 5V tolerant high-speed low-voltage I/O structure. |+| U13 | PH7 | bidirectional | Port H pin 7, I/O with 5V tolerant FM+ and analog I/O structure. |+| U14 | PB13 | bidirectional | Port B pin 13, I/O with 5V tolerant and USB I/O structure, USB VBUS monitoring. |+| U15 | PB14 | bidirectional | Port B pin 14, I/O with 5V tolerant and USB I/O structure. |+| U16 | PD8 | bidirectional | Port D pin 8, I/O with 5V tolerant high-speed low-voltage I/O structure. | | U17 | VSS | power_in | Ground supply pin. | ## Key specifications
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TFBGA-265, 14.0x14.0mm, 265 Ball, 17x17 Layout, 0.8mm Pitch</description>@@ -339,248 +339,283 @@ </packages> <symbols> <symbol name="STM32H757XIH6">- <wire x1="-12.7" y1="147.32" x2="12.7" y2="147.32" width="0.254" layer="94"/>- <wire x1="12.7" y1="147.32" x2="12.7" y2="-149.86" width="0.254" layer="94"/>- <wire x1="12.7" y1="-149.86" x2="-12.7" y2="-149.86" width="0.254" layer="94"/>- <wire x1="-12.7" y1="-149.86" x2="-12.7" y2="147.32" width="0.254" layer="94"/>- <text x="0.0000" y="149.8600" size="1.27" layer="95" align="center">>NAME</text>- <text x="0.0000" y="-152.4000" size="1.27" layer="96" align="center">>VALUE</text>- <pin name="VSS" x="-17.78" y="144.78" length="middle" direction="pwr"/>- <pin name="PI6" x="-17.78" y="142.24" length="middle" direction="out"/>- <pin name="PI5" x="-17.78" y="139.7" length="middle" direction="out"/>- <pin name="PI4" x="-17.78" y="137.16" length="middle" direction="out"/>- <pin name="PB5" x="-17.78" y="134.62" length="middle" direction="out"/>- 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Pinout checked against ST's open pin data</description>+ <wire x1="-12.7" y1="170.18" x2="12.7" y2="170.18" width="0.254" layer="94"/>+ <wire x1="12.7" y1="170.18" x2="12.7" y2="-170.18" width="0.254" layer="94"/>+ <wire x1="12.7" y1="-170.18" x2="-12.7" y2="-170.18" width="0.254" layer="94"/>+ <wire x1="-12.7" y1="-170.18" x2="-12.7" y2="170.18" width="0.254" layer="94"/>+ <text x="0.0000" y="172.7200" size="1.27" layer="95" align="center">>NAME</text>+ <text x="0.0000" y="-172.7200" size="1.27" layer="96" align="center">>VALUE</text>+ <pin name="VSS" x="-17.78" y="167.64" length="middle" direction="pwr"/>+ <pin name="PI6" x="-17.78" y="165.1" length="middle" direction="io"/>+ <pin name="PI5" x="-17.78" y="162.56" length="middle" direction="io"/>+ <pin name="PI4" x="-17.78" y="160.02" length="middle" direction="io"/>+ <pin name="PB5" x="-17.78" y="157.48" length="middle" direction="io"/>+ <pin name="VDDLDO" x="-17.78" y="154.94" length="middle" direction="pwr"/>+ <pin name="VCAP" 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name="PDR_ON" x="-17.78" y="-20.32" length="middle" direction="pwr"/>+ <pin name="BOOT0" x="-17.78" y="-22.86" length="middle" direction="in"/>+ <pin name="VDD@2" x="-17.78" y="-25.4" length="middle" direction="pwr"/>+ <pin name="PJ13" x="-17.78" y="-27.94" length="middle" direction="io"/>+ <pin name="VDD@3" x="-17.78" y="-30.48" length="middle" direction="pwr"/>+ <pin name="PD1" x="-17.78" y="-33.02" length="middle" direction="io"/>+ <pin name="PC8" x="-17.78" y="-35.56" length="middle" direction="io"/>+ <pin name="PC9" x="-17.78" y="-38.1" length="middle" direction="io"/>+ <pin name="PA8" x="-17.78" y="-40.64" length="middle" direction="io"/>+ <pin name="PA12" x="-17.78" y="-43.18" length="middle" direction="io"/>+ <pin name="PA11" x="-17.78" y="-45.72" length="middle" direction="io"/>+ <pin name="VDDSMPS" x="-17.78" y="-48.26" length="middle" direction="pwr"/>+ <pin name="VSSSMPS" x="-17.78" y="-50.8" length="middle" direction="pwr"/>+ <pin name="PI10" x="-17.78" y="-53.34" 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name="VSS@9" x="-17.78" y="-88.9" length="middle" direction="pwr"/>+ <pin name="VSS@10" x="-17.78" y="-91.44" length="middle" direction="pwr"/>+ <pin name="VSS@11" x="-17.78" y="-93.98" length="middle" direction="pwr"/>+ <pin name="VSS@12" x="-17.78" y="-96.52" length="middle" direction="pwr"/>+ <pin name="VDD@6" x="-17.78" y="-99.06" length="middle" direction="pwr"/>+ <pin name="PG5" x="-17.78" y="-101.6" length="middle" direction="io"/>+ <pin name="PG6" x="-17.78" y="-104.14" length="middle" direction="io"/>+ <pin name="VSS@13" x="-17.78" y="-106.68" length="middle" direction="pwr"/>+ <pin name="VDD50_USB" x="-17.78" y="-109.22" length="middle" direction="pwr"/>+ <pin name="PI12" x="-17.78" y="-111.76" length="middle" direction="io"/>+ <pin name="PI13" x="-17.78" y="-114.3" length="middle" direction="io"/>+ <pin name="PI14" x="-17.78" y="-116.84" length="middle" direction="io"/>+ <pin name="PF3" x="-17.78" y="-119.38" length="middle" direction="io"/> <pin name="VDD@7" x="-17.78" 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name="PJ10" x="17.78" y="-83.82" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@16" x="17.78" y="-86.36" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@29" x="17.78" y="-88.9" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@30" x="17.78" y="-91.44" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@31" x="17.78" y="-93.98" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@32" x="17.78" y="-96.52" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@33" x="17.78" y="-99.06" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@17" x="17.78" y="-101.6" length="middle" direction="pwr" rot="R180"/>+ <pin name="PF9" x="17.78" y="-104.14" length="middle" direction="io" rot="R180"/>+ <pin name="PF10" x="17.78" y="-106.68" length="middle" direction="io" rot="R180"/>+ <pin name="PC0" x="17.78" y="-109.22" length="middle" direction="io" rot="R180"/>+ <pin name="VDDA" x="17.78" y="-111.76" length="middle" direction="pwr" rot="R180"/>+ <pin name="DSI_D1N" x="17.78" y="-114.3" length="middle" direction="io" rot="R180"/>+ <pin name="DSI_D1P" x="17.78" y="-116.84" length="middle" direction="io" rot="R180"/>+ <pin name="VSSDSI@3" x="17.78" y="-119.38" length="middle" direction="pwr" rot="R180"/>+ <pin name="PJ11" x="17.78" y="-121.92" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@18" x="17.78" y="-124.46" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@34" x="17.78" y="-127" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@35" x="17.78" y="-129.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@36" x="17.78" y="-132.08" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@37" x="17.78" y="-134.62" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@38" x="17.78" y="-137.16" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@19" x="17.78" y="-139.7" length="middle" direction="pwr" rot="R180"/>+ <pin name="PF8" x="17.78" y="-142.24" length="middle" direction="io" rot="R180"/>+ <pin name="PF7" x="17.78" y="-144.78" length="middle" direction="io" rot="R180"/>+ <pin name="PF6" x="17.78" y="-147.32" length="middle" direction="io" rot="R180"/>+ <pin name="NRST" x="17.78" y="-149.86" length="middle" direction="in" rot="R180"/>+ <pin name="VSS@39" x="17.78" y="-152.4" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@40" x="17.78" y="-154.94" length="middle" direction="pwr" rot="R180"/>+ <pin name="PK1" x="17.78" y="-157.48" length="middle" direction="io" rot="R180"/>+ <pin name="PK0" x="17.78" y="-160.02" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@20" x="17.78" y="-162.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@41" x="17.78" y="-165.1" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@42" x="17.78" y="-167.64" length="middle" direction="pwr" rot="R180"/> </symbol> </symbols> <devicesets> <deviceset name="STM32H757XIH6" prefix="U">- <description></description>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-265. Pinout checked against ST's open pin data</description> <gates> <gate name="G$1" symbol="STM32H757XIH6" x="0" y="0"/> </gates>@@ -600,42 +635,44 @@ <connect gate="G$1" pin="PD5" pad="A11"/> <connect gate="G$1" pin="PD4" pad="A12"/> <connect gate="G$1" pin="PC10" pad="A13"/>- <connect gate="G$1" pin="PA15" pad="A14"/>+ <connect gate="G$1" pin="PA15_JTDI" pad="A14"/> <connect gate="G$1" pin="PI1" pad="A15"/> <connect gate="G$1" pin="PI0" pad="A16"/>+ <connect gate="G$1" pin="VSS@2" pad="A17"/> <connect gate="G$1" pin="VBAT" pad="B1"/>+ <connect gate="G$1" pin="VSS@3" pad="B2"/> <connect gate="G$1" pin="PI7" pad="B3"/> <connect gate="G$1" pin="PE1" pad="B4"/> <connect gate="G$1" pin="PB6" pad="B5"/>- <connect gate="G$1" pin="VSS@2" pad="B6"/>- <connect gate="G$1" pin="PB4" pad="B7"/>+ <connect gate="G$1" pin="VSS@4" pad="B6"/>+ <connect gate="G$1" pin="PB4_NJTRST" pad="B7"/> <connect gate="G$1" pin="PK4" pad="B8"/> <connect gate="G$1" pin="PG11" pad="B9"/> <connect gate="G$1" pin="PJ15" pad="B10"/> <connect gate="G$1" pin="PD6" pad="B11"/> <connect gate="G$1" pin="PD3" pad="B12"/> <connect gate="G$1" pin="PC11" pad="B13"/>- <connect gate="G$1" pin="PA14" pad="B14"/>+ <connect gate="G$1" pin="PA14_JTCK/SWCLK" pad="B14"/> <connect gate="G$1" pin="PI2" pad="B15"/> <connect gate="G$1" pin="PH15" pad="B16"/> <connect gate="G$1" pin="PH14" pad="B17"/>- <connect gate="G$1" pin="PC15-OSC32_OUT" pad="C1"/>- <connect gate="G$1" pin="PC14-OSC32_IN" pad="C2"/>+ <connect gate="G$1" pin="PC15-OSC32_OUT_OSC32_OUT" pad="C1"/>+ <connect gate="G$1" pin="PC14-OSC32_IN_OSC32_IN" pad="C2"/> <connect gate="G$1" pin="PE2" pad="C3"/> <connect gate="G$1" pin="PE0" pad="C4"/> <connect gate="G$1" pin="PB7" pad="C5"/>- <connect gate="G$1" pin="PB3" pad="C6"/>+ <connect gate="G$1" pin="PB3_JTDO/TRACESWO" pad="C6"/> <connect gate="G$1" pin="PK6" pad="C7"/> <connect gate="G$1" pin="PK3" pad="C8"/> <connect gate="G$1" pin="PG12" pad="C9"/>- <connect gate="G$1" pin="VSS@3" pad="C10"/>+ <connect gate="G$1" pin="VSS@5" pad="C10"/> <connect gate="G$1" pin="PD7" pad="C11"/> <connect gate="G$1" pin="PC12" pad="C12"/>- <connect gate="G$1" pin="VSS@4" pad="C13"/>+ <connect gate="G$1" pin="VSS@6" pad="C13"/> <connect gate="G$1" pin="PI3" pad="C14"/>- <connect gate="G$1" pin="PA12" pad="C15"/>- <connect gate="G$1" pin="VSS@5" pad="C16"/>- <connect gate="G$1" pin="PA13" pad="C17"/>+ <connect gate="G$1" pin="PA13_JTMS/SWDIO" pad="C15"/>+ <connect gate="G$1" pin="VSS@7" pad="C16"/>+ <connect gate="G$1" pin="VDDLDO@2" pad="C17"/> <connect gate="G$1" pin="PE5" pad="D1"/> <connect gate="G$1" pin="PE4" pad="D2"/> <connect gate="G$1" pin="PE3" pad="D3"/>@@ -659,6 +696,7 @@ <connect gate="G$1" pin="PI8" pad="E4"/> <connect gate="G$1" pin="PE6" pad="E5"/> <connect gate="G$1" pin="VDD" pad="E6"/>+ <connect gate="G$1" pin="PDR_ON" pad="E7"/> <connect gate="G$1" pin="BOOT0" pad="E8"/> <connect gate="G$1" pin="VDD@2" pad="E9"/> <connect gate="G$1" pin="PJ13" pad="E10"/>@@ -667,8 +705,8 @@ <connect gate="G$1" pin="PC8" pad="E13"/> <connect gate="G$1" pin="PC9" pad="E14"/> <connect gate="G$1" pin="PA8" pad="E15"/>- <connect gate="G$1" pin="PA11" pad="E16"/>- <connect gate="G$1" pin="PA10@2" pad="E17"/>+ <connect gate="G$1" pin="PA12" pad="E16"/>+ <connect gate="G$1" pin="PA11" pad="E17"/> <connect gate="G$1" pin="VDDSMPS" pad="F1"/> <connect gate="G$1" pin="VSSSMPS" pad="F2"/> <connect gate="G$1" pin="PI10" pad="F3"/>@@ -678,37 +716,51 @@ <connect gate="G$1" pin="PC6" pad="F14"/> <connect gate="G$1" pin="PG8" pad="F15"/> <connect gate="G$1" pin="PG7" pad="F16"/>- <connect gate="G$1" pin="VDD50USB" pad="F17"/>+ <connect gate="G$1" pin="VDD33_USB" pad="F17"/> <connect gate="G$1" pin="PF2" pad="G1"/> <connect gate="G$1" pin="VFBSMPS" pad="G2"/> <connect gate="G$1" pin="PF1" pad="G3"/> <connect gate="G$1" pin="PF0" pad="G4"/> <connect gate="G$1" pin="VDD@5" pad="G5"/>+ <connect gate="G$1" pin="VSS@8" pad="G7"/>+ <connect gate="G$1" pin="VSS@9" pad="G8"/>+ <connect gate="G$1" pin="VSS@10" pad="G9"/>+ <connect gate="G$1" pin="VSS@11" pad="G10"/>+ <connect gate="G$1" pin="VSS@12" pad="G11"/> <connect gate="G$1" pin="VDD@6" pad="G13"/> <connect gate="G$1" pin="PG5" pad="G14"/> <connect gate="G$1" pin="PG6" pad="G15"/>- <connect gate="G$1" pin="VDD33USB" pad="G17"/>+ <connect gate="G$1" pin="VSS@13" pad="G16"/>+ <connect gate="G$1" pin="VDD50_USB" pad="G17"/> <connect gate="G$1" pin="PI12" pad="H1"/> <connect gate="G$1" pin="PI13" pad="H2"/> <connect gate="G$1" pin="PI14" pad="H3"/> <connect gate="G$1" pin="PF3" pad="H4"/> <connect gate="G$1" pin="VDD@7" pad="H5"/>+ <connect gate="G$1" pin="VSS@14" pad="H7"/>+ <connect gate="G$1" pin="VSS@15" pad="H8"/>+ <connect gate="G$1" pin="VSS@16" pad="H9"/>+ <connect gate="G$1" pin="VSS@17" pad="H10"/>+ <connect gate="G$1" pin="VSS@18" pad="H11"/> <connect gate="G$1" pin="VDD@8" pad="H13"/> <connect gate="G$1" pin="PG4" pad="H14"/> <connect gate="G$1" pin="PG3" pad="H15"/> <connect gate="G$1" pin="PG2" pad="H16"/> <connect gate="G$1" pin="PK2" pad="H17"/>- <connect gate="G$1" pin="PH1-OSC_OUT" pad="J1"/>- <connect gate="G$1" pin="PH0-OSC_IN" pad="J2"/>- <connect gate="G$1" pin="VSS@6" pad="J3"/>+ <connect gate="G$1" pin="PH1-OSC_OUT_PH1" pad="J1"/>+ <connect gate="G$1" pin="PH0-OSC_IN_PH0" pad="J2"/>+ <connect gate="G$1" pin="VSS@19" pad="J3"/> <connect gate="G$1" pin="PF5" pad="J4"/> <connect gate="G$1" pin="PF4" pad="J5"/>- <connect gate="G$1" pin="VSS@7" pad="U17"/>+ <connect gate="G$1" pin="VSS@20" pad="J7"/>+ <connect gate="G$1" pin="VSS@21" pad="J8"/>+ <connect gate="G$1" pin="VSS@22" pad="J9"/>+ <connect gate="G$1" pin="VSS@23" pad="U17"/> <connect gate="G$1" pin="PD8" pad="U16"/> <connect gate="G$1" pin="PB14" pad="U15"/> <connect gate="G$1" pin="PB13" pad="U14"/> <connect gate="G$1" pin="PH7" pad="U13"/>- <connect gate="G$1" pin="VDDLDO@2" pad="U12"/>+ <connect gate="G$1" pin="VDDLDO@3" pad="U12"/> <connect gate="G$1" pin="VCAP@3" pad="U11"/> <connect gate="G$1" pin="PE14" pad="U10"/> <connect gate="G$1" pin="PE7" pad="U9"/>@@ -719,13 +771,13 @@ <connect gate="G$1" pin="PC5" pad="U4"/> <connect gate="G$1" pin="PA4" pad="U3"/> <connect gate="G$1" pin="PA3" pad="U2"/>- <connect gate="G$1" pin="VSS@8" pad="U1"/>+ <connect gate="G$1" pin="VSS@24" pad="U1"/> <connect gate="G$1" pin="PD9" pad="T17"/> <connect gate="G$1" pin="PD10" pad="T16"/> <connect gate="G$1" pin="PB15" pad="T15"/> <connect gate="G$1" pin="PB12" pad="T14"/> <connect gate="G$1" pin="PH8" pad="T13"/>- <connect gate="G$1" pin="VSS@9" pad="T12"/>+ <connect gate="G$1" pin="VSS@25" pad="T12"/> <connect gate="G$1" pin="PH6" pad="T11"/> <connect gate="G$1" pin="PE13" pad="T10"/> <connect gate="G$1" pin="PE8" pad="T9"/>@@ -742,12 +794,15 @@ <connect gate="G$1" pin="PD11" pad="R15"/> <connect gate="G$1" pin="PH12" pad="R14"/> <connect gate="G$1" pin="PH9" pad="R13"/>+ <connect gate="G$1" pin="PJ5" pad="R12"/>+ <connect gate="G$1" pin="PE15" pad="R11"/>+ <connect gate="G$1" pin="PE12" pad="R10"/> <connect gate="G$1" pin="PF15" pad="R9"/>- <connect gate="G$1" pin="VSS@10" pad="R8"/>+ <connect gate="G$1" pin="VSS@26" pad="R8"/> <connect gate="G$1" pin="PF12" pad="R7"/> <connect gate="G$1" pin="PB2" pad="R6"/> <connect gate="G$1" pin="PA7" pad="R5"/>- <connect gate="G$1" pin="VSS@11" pad="R4"/>+ <connect gate="G$1" pin="VSS@27" pad="R4"/> <connect gate="G$1" pin="PA6" pad="R3"/> <connect gate="G$1" pin="PC3_C" pad="R2"/> <connect gate="G$1" pin="PC2_C" pad="R1"/>@@ -769,7 +824,7 @@ <connect gate="G$1" pin="PH3" pad="P2"/> <connect gate="G$1" pin="VSSA" pad="P1"/> <connect gate="G$1" pin="VCAPDSI" pad="N17"/>- <connect gate="G$1" pin="VSS@12" pad="N16"/>+ <connect gate="G$1" pin="VSS@28" pad="N16"/> <connect gate="G$1" pin="PJ6" pad="N15"/> <connect gate="G$1" pin="PJ7" pad="N14"/> <connect gate="G$1" pin="PJ8" pad="N13"/>@@ -790,6 +845,7 @@ <connect gate="G$1" pin="VSSDSI" pad="M15"/> <connect gate="G$1" pin="PJ9" pad="M14"/> <connect gate="G$1" pin="VDD@14" pad="M13"/>+ <connect gate="G$1" pin="VDD@15" pad="M5"/> <connect gate="G$1" pin="PC3" pad="M4"/> <connect gate="G$1" pin="PC2" pad="M3"/> <connect gate="G$1" pin="PC1" pad="M2"/>@@ -798,8 +854,13 @@ <connect gate="G$1" pin="DSI_CKP" pad="L16"/> <connect gate="G$1" pin="VSSDSI@2" pad="L15"/> <connect gate="G$1" pin="PJ10" pad="L14"/>- <connect gate="G$1" pin="VDD@15" pad="L13"/>- <connect gate="G$1" pin="VDD@16" pad="L5"/>+ <connect gate="G$1" pin="VDD@16" pad="L13"/>+ <connect gate="G$1" pin="VSS@29" pad="L11"/>+ <connect gate="G$1" pin="VSS@30" pad="L10"/>+ <connect gate="G$1" pin="VSS@31" pad="L9"/>+ <connect gate="G$1" pin="VSS@32" pad="L8"/>+ <connect gate="G$1" pin="VSS@33" pad="L7"/>+ <connect gate="G$1" pin="VDD@17" pad="L5"/> <connect gate="G$1" pin="PF9" pad="L4"/> <connect gate="G$1" pin="PF10" pad="L3"/> <connect gate="G$1" pin="PC0" pad="L2"/>@@ -808,18 +869,36 @@ <connect gate="G$1" pin="DSI_D1P" pad="K16"/> <connect gate="G$1" pin="VSSDSI@3" pad="K15"/> <connect gate="G$1" pin="PJ11" pad="K14"/>- <connect gate="G$1" pin="VDD@17" pad="K13"/>+ <connect gate="G$1" pin="VDD@18" pad="K13"/>+ <connect gate="G$1" pin="VSS@34" pad="K11"/>+ <connect gate="G$1" pin="VSS@35" pad="K10"/>+ <connect gate="G$1" pin="VSS@36" pad="K9"/>+ <connect gate="G$1" pin="VSS@37" pad="K8"/>+ <connect gate="G$1" pin="VSS@38" pad="K7"/>+ <connect gate="G$1" pin="VDD@19" pad="K5"/> <connect gate="G$1" pin="PF8" pad="K4"/> <connect gate="G$1" pin="PF7" pad="K3"/> <connect gate="G$1" pin="PF6" pad="K2"/> <connect gate="G$1" pin="NRST" pad="K1"/>- <connect gate="G$1" pin="VSS@13" pad="J17"/>- <connect gate="G$1" pin="VSS@14" pad="J16"/>+ <connect gate="G$1" pin="VSS@39" pad="J17"/>+ <connect gate="G$1" pin="VSS@40" pad="J16"/> <connect gate="G$1" pin="PK1" pad="J15"/> <connect gate="G$1" pin="PK0" pad="J14"/>- <connect gate="G$1" pin="VDD@18" pad="J13"/>+ <connect gate="G$1" pin="VDD@20" pad="J13"/>+ <connect gate="G$1" pin="VSS@41" pad="J11"/>+ <connect gate="G$1" pin="VSS@42" pad="J10"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="STM32H757XIH6" constant="no"/>+ <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897937518694400" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32h757xih6" constant="no"/>+ <attribute name="MOUSER_PN" value="511-STM32H757XIH6" constant="no"/>+ <attribute name="DIGIKEY_PN" value="STM32H757XIH6-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C1343741" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>