component
STM32H745ZIT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
5 files changed
+186−175
README.md+36−36@@ -17,14 +17,14 @@ STM32H745ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | 7 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. | | 8 | VBAT | power_in | Backup domain power supply, 1.2 to 3.6 V. | | 9 | PC13 | bidirectional | GPIO Port C pin 13, can function as EVENTOUT or RTC_TAMP1/RTC_TS/WKUP2 in alternate function modes. |-| 10 | PC14-OSC32_IN | bidirectional | GPIO Port C pin 14 for 32 kHz oscillator input, functions as OSC32_IN or EVENTOUT. |-| 11 | PC15-OSC32_OUT | bidirectional | GPIO Port C pin 15 for 32 kHz oscillator output, functions as OSC32_OUT or EVENTOUT. |+| 10 | PC14-OSC32_IN (OSC32_IN) | bidirectional | GPIO Port C pin 14 for 32 kHz oscillator input, functions as OSC32_IN or EVENTOUT. |+| 11 | PC15-OSC32_OUT (OSC32_OUT) | bidirectional | GPIO Port C pin 15 for 32 kHz oscillator output, functions as OSC32_OUT or EVENTOUT. | | 12 | VSS | power_in | Ground power supply connection. | | 13 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. | | 14 | VSSSMPS | power_in | SMPS step-down converter ground connection. |-| 15 | VLXSMPS | passive | SMPS step-down converter switching node (inductor connection). |+| 15 | VLXSMPS | power_in | SMPS step-down converter switching node (inductor connection). | | 16 | VDDSMPS | power_in | SMPS step-down converter power supply input. |-| 17 | VFBSMPS | passive | SMPS step-down converter feedback voltage pin. |+| 17 | VFBSMPS | power_in | SMPS step-down converter feedback voltage pin. | | 18 | VSS | power_in | Ground power supply connection. | | 19 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. | | 20 | PF6 | bidirectional | GPIO Port F pin 6, can function as TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, SAI4_SD_B, QUADSPI_BK1_IO3, or EVENTOUT in alternate function modes; supports analog inputs ADC3_INN4, ADC3_INP8. |@@ -32,9 +32,9 @@ STM32H745ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | 22 | PF8 | bidirectional | GPIO Port F pin 8, can function as TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE, SAI4_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, or EVENTOUT in alternate function modes; supports analog inputs ADC3_INN3, ADC3_INP7. | | 23 | PF9 | bidirectional | GPIO Port F pin 9, can function as TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, SAI4_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, or EVENTOUT in alternate function modes; supports analog input ADC3_INP2. | | 24 | PF10 | bidirectional | GPIO Port F pin 10, can function as TIM16_BKIN, SAI1_D3, QUADSPI_CLK, SAI4_D3, DCMI_D11, LCD_DE, or EVENTOUT in alternate function modes; supports analog inputs ADC3_INN2, ADC3_INP6. |-| 25 | PH0-OSC_IN | bidirectional | GPIO Port H pin 0 for main oscillator input, functions as OSC_IN or EVENTOUT. |-| 26 | PH1-OSC_OUT | bidirectional | GPIO Port H pin 1 for main oscillator output, functions as OSC_OUT or EVENTOUT. |-| 27 | NRST | bidirectional | Reset pin with embedded weak pull-up resistor, used for device reset control and status monitoring. |+| 25 | PH0-OSC_IN (PH0) | bidirectional | GPIO Port H pin 0 for main oscillator input, functions as OSC_IN or EVENTOUT. |+| 26 | PH1-OSC_OUT (PH1) | bidirectional | GPIO Port H pin 1 for main oscillator output, functions as OSC_OUT or EVENTOUT. |+| 27 | NRST | input | Reset pin with embedded weak pull-up resistor, used for device reset control and status monitoring. | | 28 | PC0 | bidirectional | GPIO Port C pin 0, can function as DFSDM1_CKIN0, DFSDM1_DATIN4, SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, LCD_R5, or EVENTOUT in alternate function modes; supports analog input ADC123_INP10. | | 29 | PC1 | bidirectional | GPIO Port C pin 1, can function as TRACED0, SAI1_D1, DFSDM1_DATIN0, DFSDM1_CKIN4, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, SAI4_SD_A, SDMMC2_CK, SAI4_D1, ETH_MDC, MDIOS_MDC, or EVENTOUT in alternate function modes; supports analog inputs and RTC_TAMP3/WKUP5. | | 30 | PC2_C | bidirectional | GPIO Port C pin 2 analog alternative pad, can function as C1DSLEEP, DFSDM1_CKIN1, SPI2_MISO/I2S2_SDI, DFSDM1_CKOUT, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, or EVENTOUT in alternate function modes; supports analog inputs ADC123_INN11, ADC123_INP12. |@@ -60,25 +60,25 @@ STM32H745ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | 50 | PB1 | bidirectional | GPIO Port B pin 1, can function as TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN1, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, or EVENTOUT in alternate function modes; supports analog input ADC12_INP5 and COMP1_INM. | | 51 | PB2 | bidirectional | GPIO Port B pin 2, can function as RTC_OUT, SAI1_D1, DFSDM1_CKIN1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, SAI4_SD_A, QUADSPI_CLK, SAI4_D1, or EVENTOUT in alternate function modes; supports COMP1_INP. | | 52 | PF11 | bidirectional | GPIO Port F pin 11, can function as SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, DCMI_D12, or EVENTOUT in alternate function modes; supports analog input ADC1_INP2. |-| 53 | PF12 | bidirectional | GPIO Port F pin 12, can function as FMC_A6 or EVENTOUT in alternate function modes; supports analog input ADC1_INN2, ADC1_INP6. |-| 54 | PF13 | bidirectional | GPIO Port F pin 13, can function as DFSDM1_DATIN6, I2C4_SMBA, FMC_A7, or EVENTOUT in alternate function modes; supports analog input ADC2_INP2. |-| 55 | PF14 | bidirectional | GPIO Port F pin 14, can function as DFSDM1_CKIN6, I2C4_SCL, FMC_A8, or EVENTOUT in alternate function modes; supports analog inputs ADC2_INN2, ADC2_INP6. |-| 56 | PF15 | bidirectional | GPIO Port F pin 15, can function as I2C4_SDA or FMC_A9, EVENTOUT in alternate function modes. |-| 57 | PG0 | bidirectional | GPIO Port G pin 0, can function as FMC_A10 or EVENTOUT in alternate function modes. |-| 58 | PE7 | bidirectional | GPIO Port E pin 7, can function as TIM1_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_D4/FMC_DA4, or EVENTOUT in alternate function modes; supports OPAMP2_VOUT and COMP2_INM. |-| 59 | PE8 | bidirectional | GPIO Port E pin 8, can function as TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, QUADSPI_BK2_IO1, FMC_D5/FMC_DA5, or EVENTOUT in alternate function modes; supports OPAMP2_VINM and COMP2_OUT. |-| 60 | PE9 | bidirectional | GPIO Port E pin 9, can function as TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_DE, QUADSPI_BK2_IO2, FMC_D6/FMC_DA6, or EVENTOUT in alternate function modes; supports OPAMP2_VINP and COMP2_INP. |-| 61 | PE10 | bidirectional | GPIO Port E pin 10, can function as TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7/FMC_DA7, or EVENTOUT in alternate function modes; supports COMP2_INM. |-| 62 | PE11 | bidirectional | GPIO Port E pin 11, can function as TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS, SAI2_SD_B, FMC_D8/FMC_DA8, LCD_G3, or EVENTOUT in alternate function modes; supports COMP2_INP. |-| 63 | PE12 | bidirectional | GPIO Port E pin 12, can function as TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_DA9, LCD_B4, or EVENTOUT in alternate function modes; supports COMP1_OUT. |-| 64 | PE13 | bidirectional | GPIO Port E pin 13, can function as TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_DA10, LCD_DE, or EVENTOUT in alternate function modes; supports COMP2_OUT. |-| 65 | PE14 | bidirectional | GPIO Port E pin 14, can function as TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11/FMC_DA11, LCD_CLK, or EVENTOUT in alternate function modes. |-| 66 | PE15 | bidirectional | GPIO Port E pin 15, can function as TIM1_BKIN, FMC_D12/FMC_DA12, TIM1_BKIN_COMP12/COMP_TIM1_BKIN, LCD_R7, or EVENTOUT in alternate function modes. |-| 67 | PB10 | bidirectional | GPIO Port B pin 10, can function as TIM2_CH3, HRTIM_SCOUT, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, QUADSPI_BK1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, or EVENTOUT in alternate function modes. |-| 68 | PB11 | bidirectional | GPIO Port B pin 11, can function as TIM2_CH4, HRTIM_SCIN, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_TX_EN, LCD_G5, or EVENTOUT in alternate function modes. |-| 69 | VCAP | passive | Decoupling capacitor connection for main regulator stabilization, requires 2.2 µF external capacitor with ESR < 100 mΩ. |-| 70 | VSS | power_in | Ground power supply connection. |-| 71 | VDDLDO | power_in | LDO regulator output power supply, approximately 3.3 V. |+| 53 | PF14 | bidirectional | GPIO Port F pin 14, can function as DFSDM1_CKIN6, I2C4_SCL, FMC_A8, or EVENTOUT in alternate function modes; supports analog inputs ADC2_INN2, ADC2_INP6. |+| 54 | PF15 | bidirectional | GPIO Port F pin 15, can function as I2C4_SDA or FMC_A9, EVENTOUT in alternate function modes. |+| 55 | VSS | power_in | Ground power supply connection. |+| 56 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. |+| 57 | PE7 | bidirectional | GPIO Port E pin 7, can function as TIM1_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_D4/FMC_DA4, or EVENTOUT in alternate function modes; supports OPAMP2_VOUT and COMP2_INM. |+| 58 | PE8 | bidirectional | GPIO Port E pin 8, can function as TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, QUADSPI_BK2_IO1, FMC_D5/FMC_DA5, or EVENTOUT in alternate function modes; supports OPAMP2_VINM and COMP2_OUT. |+| 59 | PE9 | bidirectional | GPIO Port E pin 9, can function as TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_DE, QUADSPI_BK2_IO2, FMC_D6/FMC_DA6, or EVENTOUT in alternate function modes; supports OPAMP2_VINP and COMP2_INP. |+| 60 | PE10 | bidirectional | GPIO Port E pin 10, can function as TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7/FMC_DA7, or EVENTOUT in alternate function modes; supports COMP2_INM. |+| 61 | PE11 | bidirectional | GPIO Port E pin 11, can function as TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS, SAI2_SD_B, FMC_D8/FMC_DA8, LCD_G3, or EVENTOUT in alternate function modes; supports COMP2_INP. |+| 62 | PE12 | bidirectional | GPIO Port E pin 12, can function as TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_DA9, LCD_B4, or EVENTOUT in alternate function modes; supports COMP1_OUT. |+| 63 | PE13 | bidirectional | GPIO Port E pin 13, can function as TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_DA10, LCD_DE, or EVENTOUT in alternate function modes; supports COMP2_OUT. |+| 64 | PE14 | bidirectional | GPIO Port E pin 14, can function as TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11/FMC_DA11, LCD_CLK, or EVENTOUT in alternate function modes. |+| 65 | PE15 | bidirectional | GPIO Port E pin 15, can function as TIM1_BKIN, FMC_D12/FMC_DA12, TIM1_BKIN_COMP12/COMP_TIM1_BKIN, LCD_R7, or EVENTOUT in alternate function modes. |+| 66 | PB10 | bidirectional | GPIO Port B pin 10, can function as TIM2_CH3, HRTIM_SCOUT, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, QUADSPI_BK1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, or EVENTOUT in alternate function modes. |+| 67 | PB11 | bidirectional | GPIO Port B pin 11, can function as TIM2_CH4, HRTIM_SCIN, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_TX_EN, LCD_G5, or EVENTOUT in alternate function modes. |+| 68 | VCAP | power_in | Decoupling capacitor connection for main regulator stabilization, requires 2.2 µF external capacitor with ESR < 100 mΩ. |+| 69 | VSS | power_in | Ground power supply connection. |+| 70 | VDDLDO | power_in | LDO regulator output power supply, approximately 3.3 V. |+| 71 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. | | 72 | PB12 | bidirectional | GPIO Port B pin 12, can function as TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1, USART3_CK, FDCAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OTG_HS_ID, TIM1_BKIN_COMP12, UART5_RX, or EVENTOUT in alternate function modes. | | 73 | PB13 | bidirectional | GPIO Port B pin 13, can function as TIM1_CH1N, LPTIM2_OUT, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS/USART3_NSS, FDCAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, UART5_TX, or EVENTOUT in alternate function modes; supports OTG_HS_VBUS. | | 74 | PB14 | bidirectional | GPIO Port B pin 14, can function as TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM1_DATIN2, USART3_RTS/USART3_DE, UART4_RTS/UART4_DE, SDMMC2_D0, OTG_HS_DM, or EVENTOUT in alternate function modes. |@@ -97,8 +97,8 @@ STM32H745ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | 87 | PG7 | bidirectional | GPIO Port G pin 7, can function as HRTIM_CHE2, SAI1_MCLK_A, USART6_CK, FMC_INT, DCMI_D13, LCD_CLK, or EVENTOUT in alternate function modes. | | 88 | PG8 | bidirectional | GPIO Port G pin 8, can function as TIM8_ETR, SPI6_NSS, USART6_RTS/USART6_DE, SPDIFRX1_IN3, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, or EVENTOUT in alternate function modes. | | 89 | VSS | power_in | Ground power supply connection. |-| 90 | VDD50USB | power_in | 5V power supply for USB OTG high-speed PHY, 4.5 to 5.5 V. |-| 91 | VDD33USB | power_in | 3.3V power supply for USB, 3.0 to 3.6 V with embedded 3.3V internal regulator. |+| 90 | VDD50_USB | power_in | 5V power supply for USB OTG high-speed PHY, 4.5 to 5.5 V. |+| 91 | VDD33_USB | power_in | 3.3V power supply for USB, 3.0 to 3.6 V with embedded 3.3V internal regulator. | | 92 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. | | 93 | PC6 | bidirectional | GPIO Port C pin 6, can function as HRTIM_CHA1, TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, SDMMC1_D6, DCMI_D0, LCD_HSYNC, or EVENTOUT in alternate function modes; supports SWPMI_IO. | | 94 | PC7 | bidirectional | GPIO Port C pin 7, can function as TRGIO, HRTIM_CHA2, TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, SWPMI_TX, SDMMC1_D7, DCMI_D1, LCD_G6, or EVENTOUT in alternate function modes. |@@ -109,13 +109,13 @@ STM32H745ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | 99 | PA10 | bidirectional | GPIO Port A pin 10, can function as TIM1_CH3, HRTIM_CHC2, LPUART1_RX, USART1_RX, FDCAN1_TXFD_MODE, OTG_FS_ID, MDIOS_MDIO, LCD_B4, DCMI_D1, LCD_B1, or EVENTOUT in alternate function modes. | | 100 | PA11 | bidirectional | GPIO Port A pin 11, can function as TIM1_CH4, HRTIM_CHD1, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX, OTG_FS_DM, LCD_R4, or EVENTOUT in alternate function modes. | | 101 | PA12 | bidirectional | GPIO Port A pin 12, can function as TIM1_ETR, HRTIM_CHD2, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE, SAI2_FS_B, FDCAN1_TX, OTG_FS_DP, LCD_R5, or EVENTOUT in alternate function modes. |-| 102 | PA13 | bidirectional | JTMS/SWDIO pin for JTAG/SWD debug interface with I/O capability, functions as JTMS-SWDIO or EVENTOUT. |-| 103 | VCAP | passive | Decoupling capacitor connection for main regulator stabilization, requires 2.2 µF external capacitor with ESR < 100 mΩ. |+| 102 | PA13 (JTMS/SWDIO) | bidirectional | JTMS/SWDIO pin for JTAG/SWD debug interface with I/O capability, functions as JTMS-SWDIO or EVENTOUT. |+| 103 | VCAP | power_in | Decoupling capacitor connection for main regulator stabilization, requires 2.2 µF external capacitor with ESR < 100 mΩ. | | 104 | VSS | power_in | Ground power supply connection. | | 105 | VDDLDO | power_in | LDO regulator output power supply, approximately 3.3 V. | | 106 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. |-| 107 | PA14 | bidirectional | JTCK/SWCLK pin for JTAG/SWD debug interface with I/O capability, functions as JTCK-SWCLK or EVENTOUT. |-| 108 | PA15 | bidirectional | JTDI pin for JTAG debug interface, can function as JTDI, TIM2_CH1/TIM2_ETR, HRTIM_FLT1, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/UART4_DE, UART7_TX, or EVENTOUT in alternate function modes. |+| 107 | PA14 (JTCK/SWCLK) | bidirectional | JTCK/SWCLK pin for JTAG/SWD debug interface with I/O capability, functions as JTCK-SWCLK or EVENTOUT. |+| 108 | PA15 (JTDI) | bidirectional | JTDI pin for JTAG debug interface, can function as JTDI, TIM2_CH1/TIM2_ETR, HRTIM_FLT1, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/UART4_DE, UART7_TX, or EVENTOUT in alternate function modes. | | 109 | PC10 | bidirectional | GPIO Port C pin 10, can function as HRTIM_EEV1, DFSDM1_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, DCMI_D8, LCD_R2, or EVENTOUT in alternate function modes. | | 110 | PC11 | bidirectional | GPIO Port C pin 11, can function as HRTIM_FLT2, DFSDM1_DATIN5, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, DCMI_D4, or EVENTOUT in alternate function modes. | | 111 | PC12 | bidirectional | GPIO Port C pin 12, can function as TRACED3, HRTIM_EEV2, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9, or EVENTOUT in alternate function modes. |@@ -137,8 +137,8 @@ STM32H745ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | 127 | PG14 | bidirectional | GPIO Port G pin 14, can function as TRACED1, LPTIM1_ETR, SPI6_MOSI, USART6_TX, QUADSPI_BK2_IO3, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_A25, LCD_B0, or EVENTOUT in alternate function modes. | | 128 | VSS | power_in | Ground power supply connection. | | 129 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. |-| 130 | PB3 | bidirectional | JTDO/TRACESWO pin for JTAG debug interface and trace output, can function as JTDO/TRACESWO, TIM2_CH2, HRTIM_FLT4, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, CRS_SYNC, UART7_RX, or EVENTOUT in alternate function modes. |-| 131 | PB4 | bidirectional | NJTRST pin for JTAG reset interface, can function as NJTRST, TIM16_BKIN, TIM3_CH1, HRTIM_EEV6, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, UART7_TX, or EVENTOUT in alternate function modes. |+| 130 | PB3 (JTDO/TRACESWO) | bidirectional | JTDO/TRACESWO pin for JTAG debug interface and trace output, can function as JTDO/TRACESWO, TIM2_CH2, HRTIM_FLT4, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, CRS_SYNC, UART7_RX, or EVENTOUT in alternate function modes. |+| 131 | PB4 (NJTRST) | bidirectional | NJTRST pin for JTAG reset interface, can function as NJTRST, TIM16_BKIN, TIM3_CH1, HRTIM_EEV6, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, UART7_TX, or EVENTOUT in alternate function modes. | | 132 | PB5 | bidirectional | GPIO Port B pin 5, can function as TIM17_BKIN, TIM3_CH2, HRTIM_EEV7, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, UART5_RX, or EVENTOUT in alternate function modes. | | 133 | PB6 | bidirectional | GPIO Port B pin 6, can function as TIM16_CH1N, TIM4_CH1, HRTIM_EEV8, I2C1_SCL, CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, QUADSPI_BK1_NCS, DFSDM1_DATIN5, FMC_SDNE1, DCMI_D5, UART5_TX, or EVENTOUT in alternate function modes. | | 134 | PB7 | bidirectional | GPIO Port B pin 7, can function as TIM17_CH1N, TIM4_CH2, HRTIM_EEV9, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, FDCAN2_TXFD_MODE, DFSDM1_CKIN5, FMC_NL, DCMI_VSYNC, or EVENTOUT in alternate function modes; supports PVD_IN. |@@ -147,9 +147,9 @@ STM32H745ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | 137 | PB9 | bidirectional | GPIO Port B pin 9, can function as TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, I2C4_SMBA, SDMMC1_D5, DCMI_D7, LCD_B7, or EVENTOUT in alternate function modes. | | 138 | PE0 | bidirectional | GPIO Port E pin 0, can function as LPTIM1_ETR, TIM4_ETR, HRTIM_SCIN, LPTIM2_ETR, UART8_RX, FDCAN1_RXFD_MODE, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, or EVENTOUT in alternate function modes. | | 139 | PE1 | bidirectional | GPIO Port E pin 1, can function as LPTIM1_IN2, HRTIM_SCOUT, UART8_TX, FDCAN1_TXFD_MODE, FMC_NBL1, DCMI_D3, or EVENTOUT in alternate function modes. |-| 140 | VCAP | passive | Decoupling capacitor connection for main regulator stabilization, requires 2.2 µF external capacitor with ESR < 100 mΩ. |+| 140 | VCAP | power_in | Decoupling capacitor connection for main regulator stabilization, requires 2.2 µF external capacitor with ESR < 100 mΩ. | | 141 | VSS | power_in | Ground power supply connection. |-| 142 | PDR_ON | input | Power domain regulator ON control input; when pulled low, disables the regulator for external VCORE supply. |+| 142 | PDR_ON | power_in | Power domain regulator ON control input; when pulled low, disables the regulator for external VCORE supply. | | 143 | VDDLDO | power_in | LDO regulator output power supply, approximately 3.3 V. | | 144 | VDD | power_in | Main 1.62 to 3.6 V power supply pin. |
package.json+2−2@@ -1,6 +1,6 @@ { "slug": "stm32h745zit6",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.", "tags": [@@ -949,4 +949,4 @@ "footprint": "viewers/footprint.html" } }-}+}
page.json+4−4@@ -4,7 +4,7 @@ "slug": "stm32h745zit6", "title": "STM32H745ZIT6", "brief": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -976,7 +976,7 @@ "viewers/symbol.html", "viewers/footprint.html" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "org": "adom" }
stm32h745zit6.kicad_sym+40−40@@ -45,11 +45,11 @@ (number "9" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 66.04 0) (length 5.08)- (name "PC14-OSC32_IN" (effects (font (size 1.27 1.27))))+ (name "PC14-OSC32_IN (OSC32_IN)" (effects (font (size 1.27 1.27)))) (number "10" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 63.50 0) (length 5.08)- (name "PC15-OSC32_OUT" (effects (font (size 1.27 1.27))))+ (name "PC15-OSC32_OUT (OSC32_OUT)" (effects (font (size 1.27 1.27)))) (number "11" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at -17.78 60.96 0) (length 5.08)@@ -64,7 +64,7 @@ (name "VSSSMPS" (effects (font (size 1.27 1.27)))) (number "14" (effects (font (size 1.27 1.27)))) )- (pin passive line (at -17.78 53.34 0) (length 5.08)+ (pin power_in line (at -17.78 53.34 0) (length 5.08) (name "VLXSMPS" (effects (font (size 1.27 1.27)))) (number "15" (effects (font (size 1.27 1.27)))) )@@ -72,7 +72,7 @@ (name "VDDSMPS" (effects (font (size 1.27 1.27)))) (number "16" (effects (font (size 1.27 1.27)))) )- (pin passive line (at -17.78 48.26 0) (length 5.08)+ (pin power_in line (at -17.78 48.26 0) (length 5.08) (name "VFBSMPS" (effects (font (size 1.27 1.27)))) (number "17" (effects (font (size 1.27 1.27)))) )@@ -105,14 +105,14 @@ (number "24" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 27.94 0) (length 5.08)- (name "PH0-OSC_IN" (effects (font (size 1.27 1.27))))+ (name "PH0-OSC_IN (PH0)" (effects (font (size 1.27 1.27)))) (number "25" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 25.40 0) (length 5.08)- (name "PH1-OSC_OUT" (effects (font (size 1.27 1.27))))+ (name "PH1-OSC_OUT (PH1)" (effects (font (size 1.27 1.27)))) (number "26" (effects (font (size 1.27 1.27)))) )- (pin bidirectional line (at -17.78 22.86 0) (length 5.08)+ (pin input line (at -17.78 22.86 0) (length 5.08) (name "NRST" (effects (font (size 1.27 1.27)))) (number "27" (effects (font (size 1.27 1.27)))) )@@ -217,79 +217,79 @@ (number "52" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -43.18 0) (length 5.08)- (name "PF12" (effects (font (size 1.27 1.27))))+ (name "PF14" (effects (font (size 1.27 1.27)))) (number "53" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -45.72 0) (length 5.08)- (name "PF13" (effects (font (size 1.27 1.27))))+ (name "PF15" (effects (font (size 1.27 1.27)))) (number "54" (effects (font (size 1.27 1.27)))) )- (pin bidirectional line (at -17.78 -48.26 0) (length 5.08)- (name "PF14" (effects (font (size 1.27 1.27))))+ (pin power_in line (at -17.78 -48.26 0) (length 5.08)+ (name "VSS" (effects (font (size 1.27 1.27)))) (number "55" (effects (font (size 1.27 1.27)))) )- (pin bidirectional line (at -17.78 -50.80 0) (length 5.08)- (name "PF15" (effects (font (size 1.27 1.27))))+ (pin power_in line (at -17.78 -50.80 0) (length 5.08)+ (name "VDD" (effects (font (size 1.27 1.27)))) (number "56" (effects (font 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(number "61" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -66.04 0) (length 5.08)- (name "PE11" (effects (font (size 1.27 1.27))))+ (name "PE12" (effects (font (size 1.27 1.27)))) (number "62" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -68.58 0) (length 5.08)- (name "PE12" (effects (font (size 1.27 1.27))))+ (name "PE13" (effects (font (size 1.27 1.27)))) (number "63" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -71.12 0) (length 5.08)- (name "PE13" (effects (font (size 1.27 1.27))))+ (name "PE14" (effects (font (size 1.27 1.27)))) (number "64" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -73.66 0) (length 5.08)- (name "PE14" (effects (font (size 1.27 1.27))))+ (name "PE15" (effects (font (size 1.27 1.27)))) (number "65" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -76.20 0) (length 5.08)- (name "PE15" (effects (font (size 1.27 1.27))))+ (name "PB10" (effects (font (size 1.27 1.27)))) (number "66" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -78.74 0) (length 5.08)- (name "PB10" (effects (font (size 1.27 1.27))))+ (name "PB11" (effects (font (size 1.27 1.27)))) (number "67" (effects (font (size 1.27 1.27)))) )- (pin bidirectional line (at -17.78 -81.28 0) (length 5.08)- (name "PB11" (effects (font (size 1.27 1.27))))+ (pin power_in line (at -17.78 -81.28 0) (length 5.08)+ (name "VCAP" (effects (font (size 1.27 1.27)))) (number "68" (effects (font (size 1.27 1.27)))) )- (pin passive line (at -17.78 -83.82 0) (length 5.08)- (name "VCAP" (effects (font (size 1.27 1.27))))+ (pin power_in line (at -17.78 -83.82 0) (length 5.08)+ (name "VSS" (effects (font (size 1.27 1.27)))) (number "69" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at -17.78 -86.36 0) (length 5.08)- (name "VSS" (effects (font (size 1.27 1.27))))+ (name "VDDLDO" (effects (font (size 1.27 1.27)))) (number "70" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at -17.78 -88.90 0) (length 5.08)- (name "VDDLDO" (effects (font (size 1.27 1.27))))+ (name "VDD" (effects (font (size 1.27 1.27)))) (number "71" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at -17.78 -91.44 0) (length 5.08)@@ -304,7 +304,7 @@ (name "VDDLDO" (effects (font (size 1.27 1.27)))) (number "143" (effects (font (size 1.27 1.27)))) )- (pin input line (at 17.78 83.82 180) (length 5.08)+ (pin power_in line (at 17.78 83.82 180) (length 5.08) (name "PDR_ON" (effects (font (size 1.27 1.27)))) (number "142" (effects (font (size 1.27 1.27)))) )@@ -312,7 +312,7 @@ (name "VSS" (effects (font (size 1.27 1.27)))) (number "141" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 78.74 180) (length 5.08)+ (pin power_in line (at 17.78 78.74 180) (length 5.08) (name "VCAP" (effects (font (size 1.27 1.27)))) (number "140" (effects (font (size 1.27 1.27)))) )@@ -349,11 +349,11 @@ (number "132" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at 17.78 55.88 180) (length 5.08)- (name "PB4" (effects (font (size 1.27 1.27))))+ (name "PB4 (NJTRST)" (effects (font (size 1.27 1.27)))) (number "131" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at 17.78 53.34 180) (length 5.08)- (name "PB3" (effects (font (size 1.27 1.27))))+ (name "PB3 (JTDO/TRACESWO)" (effects (font (size 1.27 1.27)))) (number "130" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at 17.78 50.80 180) (length 5.08)@@ -441,11 +441,11 @@ (number "109" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at 17.78 -2.54 180) (length 5.08)- (name "PA15" (effects (font (size 1.27 1.27))))+ (name "PA15 (JTDI)" (effects (font (size 1.27 1.27)))) (number "108" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at 17.78 -5.08 180) (length 5.08)- (name "PA14" (effects (font (size 1.27 1.27))))+ (name "PA14 (JTCK/SWCLK)" (effects (font (size 1.27 1.27)))) (number "107" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at 17.78 -7.62 180) (length 5.08)@@ -460,12 +460,12 @@ (name "VSS" (effects (font (size 1.27 1.27)))) (number "104" (effects (font (size 1.27 1.27)))) )- (pin passive line (at 17.78 -15.24 180) (length 5.08)+ (pin power_in line (at 17.78 -15.24 180) (length 5.08) (name "VCAP" (effects (font (size 1.27 1.27)))) (number "103" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at 17.78 -17.78 180) (length 5.08)- (name "PA13" (effects (font (size 1.27 1.27))))+ (name "PA13 (JTMS/SWDIO)" (effects (font (size 1.27 1.27)))) (number "102" (effects (font (size 1.27 1.27)))) ) (pin bidirectional line (at 17.78 -20.32 180) (length 5.08)@@ -509,11 +509,11 @@ (number "92" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at 17.78 -45.72 180) (length 5.08)- (name "VDD33USB" (effects (font (size 1.27 1.27))))+ (name "VDD33_USB" (effects (font (size 1.27 1.27)))) (number "91" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at 17.78 -48.26 180) (length 5.08)- (name "VDD50USB" (effects (font (size 1.27 1.27))))+ (name "VDD50_USB" (effects (font (size 1.27 1.27)))) (number "90" (effects (font (size 1.27 1.27)))) ) (pin power_in line (at 17.78 -50.80 180) (length 5.08)
stm32h745zit6.lbr+104−93@@ -50,7 +50,7 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data</description> <packages> <package name="LQFP-144_20x20mm_P0.5mm"> <description>LQFP-144, 20 x 20 mm, 0.5 mm pitch</description>@@ -224,6 +224,7 @@ </packages> <symbols> <symbol name="STM32H745ZIT6">+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data</description> <wire x1="-12.7" y1="91.44" x2="12.7" y2="91.44" width="0.254" layer="94"/> <wire x1="12.7" y1="91.44" x2="12.7" y2="-93.98" width="0.254" layer="94"/> <wire x1="12.7" y1="-93.98" x2="-12.7" y2="-93.98" width="0.254" layer="94"/>@@ -239,14 +240,14 @@ <pin name="VDD" x="-17.78" y="73.66" length="middle" direction="pwr"/> <pin name="VBAT" x="-17.78" y="71.12" length="middle" direction="pwr"/> <pin name="PC13" x="-17.78" y="68.58" length="middle" direction="io"/>- <pin name="PC14-OSC32_IN" x="-17.78" y="66.04" length="middle" direction="io"/>- <pin name="PC15-OSC32_OUT" x="-17.78" y="63.5" length="middle" direction="io"/>+ <pin name="PC14-OSC32_IN_OSC32_IN" x="-17.78" y="66.04" length="middle" direction="io"/>+ <pin name="PC15-OSC32_OUT_OSC32_OUT" x="-17.78" y="63.5" length="middle" direction="io"/> <pin name="VSS@2" x="-17.78" y="60.96" length="middle" direction="pwr"/> <pin name="VDD@2" x="-17.78" y="58.42" length="middle" direction="pwr"/> <pin name="VSSSMPS" x="-17.78" y="55.88" length="middle" direction="pwr"/>- <pin name="VLXSMPS" x="-17.78" y="53.34" length="middle" direction="pas"/>+ <pin name="VLXSMPS" x="-17.78" y="53.34" length="middle" direction="pwr"/> <pin name="VDDSMPS" x="-17.78" y="50.8" length="middle" direction="pwr"/>- <pin name="VFBSMPS" x="-17.78" y="48.26" length="middle" direction="pas"/>+ <pin name="VFBSMPS" x="-17.78" y="48.26" length="middle" direction="pwr"/> <pin name="VSS@3" x="-17.78" y="45.72" length="middle" direction="pwr"/> <pin name="VDD@3" x="-17.78" y="43.18" length="middle" direction="pwr"/> <pin name="PF6" x="-17.78" y="40.64" length="middle" direction="io"/>@@ -254,9 +255,9 @@ <pin name="PF8" x="-17.78" y="35.56" length="middle" direction="io"/> <pin name="PF9" x="-17.78" y="33.02" length="middle" direction="io"/> <pin name="PF10" x="-17.78" y="30.48" length="middle" direction="io"/>- <pin name="PH0-OSC_IN" x="-17.78" y="27.94" length="middle" direction="io"/>- <pin name="PH1-OSC_OUT" x="-17.78" y="25.4" length="middle" direction="io"/>- <pin name="NRST" x="-17.78" y="22.86" length="middle" direction="io"/>+ <pin name="PH0-OSC_IN_PH0" x="-17.78" y="27.94" length="middle" direction="io"/>+ <pin name="PH1-OSC_OUT_PH1" x="-17.78" y="25.4" length="middle" direction="io"/>+ <pin name="NRST" x="-17.78" y="22.86" length="middle" direction="in"/> <pin name="PC0" x="-17.78" y="20.32" length="middle" direction="io"/> <pin name="PC1" x="-17.78" y="17.78" length="middle" direction="io"/> <pin name="PC2_C" x="-17.78" y="15.24" length="middle" direction="io"/>@@ -282,31 +283,31 @@ <pin name="PB1" x="-17.78" y="-35.56" length="middle" direction="io"/> <pin name="PB2" x="-17.78" y="-38.1" length="middle" direction="io"/> <pin name="PF11" x="-17.78" y="-40.64" length="middle" direction="io"/>- <pin name="PF12" x="-17.78" y="-43.18" length="middle" direction="io"/>- <pin name="PF13" x="-17.78" y="-45.72" length="middle" direction="io"/>- <pin name="PF14" x="-17.78" y="-48.26" length="middle" direction="io"/>- <pin name="PF15" x="-17.78" y="-50.8" length="middle" direction="io"/>- <pin name="PG0" x="-17.78" y="-53.34" length="middle" direction="io"/>- <pin name="PE7" x="-17.78" y="-55.88" length="middle" direction="io"/>- <pin name="PE8" x="-17.78" y="-58.42" length="middle" direction="io"/>- <pin name="PE9" x="-17.78" y="-60.96" length="middle" direction="io"/>- <pin name="PE10" x="-17.78" y="-63.5" length="middle" direction="io"/>- <pin name="PE11" x="-17.78" y="-66.04" length="middle" direction="io"/>- <pin name="PE12" x="-17.78" y="-68.58" length="middle" direction="io"/>- <pin name="PE13" x="-17.78" y="-71.12" length="middle" direction="io"/>- <pin name="PE14" x="-17.78" y="-73.66" length="middle" direction="io"/>- <pin name="PE15" x="-17.78" y="-76.2" length="middle" direction="io"/>- <pin name="PB10" x="-17.78" y="-78.74" length="middle" direction="io"/>- <pin name="PB11" x="-17.78" y="-81.28" length="middle" direction="io"/>- <pin name="VCAP" x="-17.78" y="-83.82" length="middle" direction="pas"/>- <pin name="VSS@6" x="-17.78" y="-86.36" length="middle" direction="pwr"/>- <pin name="VDDLDO" x="-17.78" y="-88.9" length="middle" direction="pwr"/>+ <pin name="PF14" x="-17.78" y="-43.18" length="middle" direction="io"/>+ <pin name="PF15" x="-17.78" y="-45.72" length="middle" direction="io"/>+ <pin name="VSS@6" x="-17.78" y="-48.26" length="middle" direction="pwr"/>+ <pin name="VDD@6" x="-17.78" y="-50.8" length="middle" direction="pwr"/>+ <pin name="PE7" x="-17.78" y="-53.34" length="middle" direction="io"/>+ <pin name="PE8" x="-17.78" y="-55.88" length="middle" direction="io"/>+ <pin name="PE9" x="-17.78" y="-58.42" length="middle" direction="io"/>+ <pin name="PE10" x="-17.78" y="-60.96" length="middle" direction="io"/>+ <pin name="PE11" x="-17.78" y="-63.5" length="middle" direction="io"/>+ <pin name="PE12" x="-17.78" y="-66.04" length="middle" direction="io"/>+ <pin name="PE13" x="-17.78" y="-68.58" length="middle" direction="io"/>+ <pin name="PE14" x="-17.78" y="-71.12" length="middle" direction="io"/>+ <pin name="PE15" x="-17.78" y="-73.66" length="middle" direction="io"/>+ <pin name="PB10" x="-17.78" y="-76.2" length="middle" direction="io"/>+ <pin name="PB11" x="-17.78" y="-78.74" length="middle" direction="io"/>+ <pin name="VCAP" x="-17.78" y="-81.28" length="middle" direction="pwr"/>+ <pin name="VSS@7" x="-17.78" y="-83.82" length="middle" direction="pwr"/>+ <pin name="VDDLDO" x="-17.78" y="-86.36" length="middle" direction="pwr"/>+ <pin name="VDD@7" x="-17.78" y="-88.9" length="middle" direction="pwr"/> <pin name="PB12" x="-17.78" y="-91.44" length="middle" direction="io"/>- <pin name="VDD@6" x="17.78" y="88.9" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@8" x="17.78" y="88.9" length="middle" direction="pwr" rot="R180"/> <pin name="VDDLDO@2" x="17.78" y="86.36" length="middle" direction="pwr" rot="R180"/>- <pin name="PDR_ON" x="17.78" y="83.82" length="middle" direction="in" rot="R180"/>- <pin name="VSS@7" x="17.78" y="81.28" length="middle" direction="pwr" rot="R180"/>- <pin name="VCAP@2" x="17.78" y="78.74" length="middle" direction="pas" rot="R180"/>+ <pin name="PDR_ON" x="17.78" y="83.82" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@8" x="17.78" y="81.28" length="middle" direction="pwr" rot="R180"/>+ <pin name="VCAP@2" x="17.78" y="78.74" length="middle" direction="pwr" rot="R180"/> <pin name="PE1" x="17.78" y="76.2" length="middle" direction="io" rot="R180"/> <pin name="PE0" x="17.78" y="73.66" length="middle" direction="io" rot="R180"/> <pin name="PB9" x="17.78" y="71.12" length="middle" direction="io" rot="R180"/>@@ -315,10 +316,10 @@ <pin name="PB7" x="17.78" y="63.5" length="middle" direction="io" rot="R180"/> <pin name="PB6" x="17.78" y="60.96" length="middle" direction="io" rot="R180"/> <pin name="PB5" x="17.78" y="58.42" length="middle" direction="io" rot="R180"/>- <pin name="PB4" x="17.78" y="55.88" length="middle" direction="io" rot="R180"/>- <pin name="PB3" x="17.78" y="53.34" length="middle" direction="io" rot="R180"/>- <pin name="VDD@7" x="17.78" y="50.8" length="middle" direction="pwr" rot="R180"/>- <pin name="VSS@8" x="17.78" y="48.26" length="middle" direction="pwr" rot="R180"/>+ <pin name="PB4_NJTRST" x="17.78" y="55.88" length="middle" direction="io" rot="R180"/>+ <pin name="PB3_JTDO/TRACESWO" x="17.78" y="53.34" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@9" x="17.78" y="50.8" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@9" x="17.78" y="48.26" length="middle" direction="pwr" rot="R180"/> <pin name="PG14" x="17.78" y="45.72" length="middle" direction="io" rot="R180"/> <pin name="PG13" x="17.78" y="43.18" length="middle" direction="io" rot="R180"/> <pin name="PG12" x="17.78" y="40.64" length="middle" direction="io" rot="R180"/>@@ -327,8 +328,8 @@ <pin name="PG9" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/> <pin name="PD7" x="17.78" y="30.48" length="middle" direction="io" rot="R180"/> <pin name="PD6" x="17.78" y="27.94" length="middle" direction="io" rot="R180"/>- <pin name="VDD@8" x="17.78" y="25.4" length="middle" direction="pwr" rot="R180"/>- <pin name="VSS@9" x="17.78" y="22.86" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@10" x="17.78" y="25.4" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@10" x="17.78" y="22.86" length="middle" direction="pwr" rot="R180"/> <pin name="PD5" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/> <pin name="PD4" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/> <pin name="PD3" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>@@ -338,13 +339,13 @@ <pin name="PC12" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/> <pin name="PC11" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/> <pin name="PC10" x="17.78" y="0" length="middle" direction="io" rot="R180"/>- <pin name="PA15" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>- <pin name="PA14" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>- <pin name="VDD@9" x="17.78" y="-7.62" length="middle" direction="pwr" rot="R180"/>+ <pin name="PA15_JTDI" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PA14_JTCK/SWCLK" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@11" x="17.78" y="-7.62" length="middle" direction="pwr" rot="R180"/> <pin name="VDDLDO@3" x="17.78" y="-10.16" length="middle" direction="pwr" rot="R180"/>- <pin name="VSS@10" x="17.78" y="-12.7" length="middle" direction="pwr" rot="R180"/>- <pin name="VCAP@3" x="17.78" y="-15.24" length="middle" direction="pas" rot="R180"/>- <pin name="PA13" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="VSS@11" x="17.78" y="-12.7" length="middle" direction="pwr" rot="R180"/>+ <pin name="VCAP@3" x="17.78" y="-15.24" length="middle" direction="pwr" rot="R180"/>+ <pin name="PA13_JTMS/SWDIO" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/> <pin name="PA12" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/> <pin name="PA11" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/> <pin name="PA10" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>@@ -354,10 +355,10 @@ <pin name="PC8" x="17.78" y="-35.56" length="middle" direction="io" rot="R180"/> <pin name="PC7" x="17.78" y="-38.1" length="middle" direction="io" rot="R180"/> <pin name="PC6" x="17.78" y="-40.64" length="middle" direction="io" rot="R180"/>- <pin name="VDD@10" x="17.78" y="-43.18" length="middle" direction="pwr" rot="R180"/>- <pin name="VDD33USB" x="17.78" y="-45.72" length="middle" direction="pwr" rot="R180"/>- <pin name="VDD50USB" x="17.78" y="-48.26" length="middle" direction="pwr" rot="R180"/>- <pin name="VSS@11" x="17.78" y="-50.8" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@12" x="17.78" y="-43.18" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD33_USB" x="17.78" y="-45.72" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD50_USB" x="17.78" y="-48.26" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@12" x="17.78" y="-50.8" length="middle" direction="pwr" rot="R180"/> <pin name="PG8" x="17.78" y="-53.34" length="middle" direction="io" rot="R180"/> <pin name="PG7" x="17.78" y="-55.88" length="middle" direction="io" rot="R180"/> <pin name="PG6" x="17.78" y="-58.42" length="middle" direction="io" rot="R180"/>@@ -366,8 +367,8 @@ <pin name="PD13" x="17.78" y="-66.04" length="middle" direction="io" rot="R180"/> <pin name="PD12" x="17.78" y="-68.58" length="middle" direction="io" rot="R180"/> <pin name="PD11" x="17.78" y="-71.12" length="middle" direction="io" rot="R180"/>- <pin name="VSS@12" x="17.78" y="-73.66" length="middle" direction="pwr" rot="R180"/>- <pin name="VDD@11" x="17.78" y="-76.2" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@13" x="17.78" y="-73.66" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@13" x="17.78" y="-76.2" length="middle" direction="pwr" rot="R180"/> <pin name="PD10" x="17.78" y="-78.74" length="middle" direction="io" rot="R180"/> <pin name="PD9" x="17.78" y="-81.28" length="middle" direction="io" rot="R180"/> <pin name="PD8" x="17.78" y="-83.82" length="middle" direction="io" rot="R180"/>@@ -378,7 +379,7 @@ </symbols> <devicesets> <deviceset name="STM32H745ZIT6" prefix="U">- <description></description>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data</description> <gates> <gate name="G$1" symbol="STM32H745ZIT6" x="0" y="0"/> </gates>@@ -394,8 +395,8 @@ <connect gate="G$1" pin="VDD" pad="7"/> <connect gate="G$1" pin="VBAT" pad="8"/> <connect gate="G$1" pin="PC13" pad="9"/>- <connect gate="G$1" pin="PC14-OSC32_IN" pad="10"/>- <connect gate="G$1" pin="PC15-OSC32_OUT" pad="11"/>+ <connect gate="G$1" pin="PC14-OSC32_IN_OSC32_IN" pad="10"/>+ <connect gate="G$1" pin="PC15-OSC32_OUT_OSC32_OUT" pad="11"/> <connect gate="G$1" pin="VSS@2" pad="12"/> <connect gate="G$1" pin="VDD@2" pad="13"/> <connect gate="G$1" pin="VSSSMPS" pad="14"/>@@ -409,8 +410,8 @@ <connect gate="G$1" pin="PF8" pad="22"/> <connect gate="G$1" pin="PF9" pad="23"/> <connect gate="G$1" pin="PF10" pad="24"/>- <connect gate="G$1" pin="PH0-OSC_IN" pad="25"/>- <connect gate="G$1" pin="PH1-OSC_OUT" pad="26"/>+ <connect gate="G$1" pin="PH0-OSC_IN_PH0" pad="25"/>+ <connect gate="G$1" pin="PH1-OSC_OUT_PH1" pad="26"/> <connect gate="G$1" pin="NRST" pad="27"/> <connect gate="G$1" pin="PC0" pad="28"/> <connect gate="G$1" pin="PC1" pad="29"/>@@ -437,30 +438,30 @@ <connect gate="G$1" pin="PB1" pad="50"/> <connect gate="G$1" pin="PB2" pad="51"/> <connect gate="G$1" pin="PF11" pad="52"/>- <connect gate="G$1" pin="PF12" pad="53"/>- <connect gate="G$1" pin="PF13" pad="54"/>- <connect gate="G$1" pin="PF14" pad="55"/>- <connect gate="G$1" pin="PF15" pad="56"/>- <connect gate="G$1" pin="PG0" pad="57"/>- <connect gate="G$1" pin="PE7" pad="58"/>- <connect gate="G$1" pin="PE8" pad="59"/>- <connect gate="G$1" pin="PE9" pad="60"/>- <connect gate="G$1" pin="PE10" pad="61"/>- <connect gate="G$1" pin="PE11" pad="62"/>- <connect gate="G$1" pin="PE12" pad="63"/>- <connect gate="G$1" pin="PE13" pad="64"/>- <connect gate="G$1" pin="PE14" pad="65"/>- <connect gate="G$1" pin="PE15" pad="66"/>- <connect gate="G$1" pin="PB10" pad="67"/>- <connect gate="G$1" pin="PB11" pad="68"/>- <connect gate="G$1" pin="VCAP" pad="69"/>- <connect gate="G$1" pin="VSS@6" pad="70"/>- <connect gate="G$1" pin="VDDLDO" pad="71"/>+ <connect gate="G$1" pin="PF14" pad="53"/>+ <connect gate="G$1" pin="PF15" pad="54"/>+ <connect gate="G$1" pin="VSS@6" pad="55"/>+ <connect gate="G$1" pin="VDD@6" pad="56"/>+ <connect gate="G$1" pin="PE7" pad="57"/>+ <connect gate="G$1" pin="PE8" pad="58"/>+ <connect gate="G$1" pin="PE9" pad="59"/>+ <connect gate="G$1" pin="PE10" pad="60"/>+ <connect gate="G$1" pin="PE11" pad="61"/>+ <connect gate="G$1" pin="PE12" pad="62"/>+ <connect gate="G$1" pin="PE13" pad="63"/>+ <connect gate="G$1" pin="PE14" pad="64"/>+ <connect gate="G$1" pin="PE15" pad="65"/>+ <connect gate="G$1" pin="PB10" pad="66"/>+ <connect gate="G$1" pin="PB11" pad="67"/>+ <connect gate="G$1" pin="VCAP" pad="68"/>+ <connect gate="G$1" pin="VSS@7" pad="69"/>+ <connect gate="G$1" pin="VDDLDO" pad="70"/>+ <connect gate="G$1" pin="VDD@7" pad="71"/> <connect gate="G$1" pin="PB12" pad="72"/>- <connect gate="G$1" pin="VDD@6" pad="144"/>+ <connect gate="G$1" pin="VDD@8" pad="144"/> <connect gate="G$1" pin="VDDLDO@2" pad="143"/> <connect gate="G$1" pin="PDR_ON" pad="142"/>- <connect gate="G$1" pin="VSS@7" pad="141"/>+ <connect gate="G$1" pin="VSS@8" pad="141"/> <connect gate="G$1" pin="VCAP@2" pad="140"/> <connect gate="G$1" pin="PE1" pad="139"/> <connect gate="G$1" pin="PE0" pad="138"/>@@ -470,10 +471,10 @@ <connect gate="G$1" pin="PB7" pad="134"/> <connect gate="G$1" pin="PB6" pad="133"/> <connect gate="G$1" pin="PB5" pad="132"/>- <connect gate="G$1" pin="PB4" pad="131"/>- <connect gate="G$1" pin="PB3" pad="130"/>- <connect gate="G$1" pin="VDD@7" pad="129"/>- <connect gate="G$1" pin="VSS@8" pad="128"/>+ <connect gate="G$1" pin="PB4_NJTRST" pad="131"/>+ <connect gate="G$1" pin="PB3_JTDO/TRACESWO" pad="130"/>+ <connect gate="G$1" pin="VDD@9" pad="129"/>+ <connect gate="G$1" pin="VSS@9" pad="128"/> <connect gate="G$1" pin="PG14" pad="127"/> <connect gate="G$1" pin="PG13" pad="126"/> <connect gate="G$1" pin="PG12" pad="125"/>@@ -482,8 +483,8 @@ <connect gate="G$1" pin="PG9" pad="122"/> <connect gate="G$1" pin="PD7" pad="121"/> <connect gate="G$1" pin="PD6" pad="120"/>- <connect gate="G$1" pin="VDD@8" pad="119"/>- <connect gate="G$1" pin="VSS@9" pad="118"/>+ <connect gate="G$1" pin="VDD@10" pad="119"/>+ <connect gate="G$1" pin="VSS@10" pad="118"/> <connect gate="G$1" pin="PD5" pad="117"/> <connect gate="G$1" pin="PD4" pad="116"/> <connect gate="G$1" pin="PD3" pad="115"/>@@ -493,13 +494,13 @@ <connect gate="G$1" pin="PC12" pad="111"/> <connect gate="G$1" pin="PC11" pad="110"/> <connect gate="G$1" pin="PC10" pad="109"/>- <connect gate="G$1" pin="PA15" pad="108"/>- <connect gate="G$1" pin="PA14" pad="107"/>- <connect gate="G$1" pin="VDD@9" pad="106"/>+ <connect gate="G$1" pin="PA15_JTDI" pad="108"/>+ <connect gate="G$1" pin="PA14_JTCK/SWCLK" pad="107"/>+ <connect gate="G$1" pin="VDD@11" pad="106"/> <connect gate="G$1" pin="VDDLDO@3" pad="105"/>- <connect gate="G$1" pin="VSS@10" pad="104"/>+ <connect gate="G$1" pin="VSS@11" pad="104"/> <connect gate="G$1" pin="VCAP@3" pad="103"/>- <connect gate="G$1" pin="PA13" pad="102"/>+ <connect gate="G$1" pin="PA13_JTMS/SWDIO" pad="102"/> <connect gate="G$1" pin="PA12" pad="101"/> <connect gate="G$1" pin="PA11" pad="100"/> <connect gate="G$1" pin="PA10" pad="99"/>@@ -509,10 +510,10 @@ <connect gate="G$1" pin="PC8" pad="95"/> <connect gate="G$1" pin="PC7" pad="94"/> <connect gate="G$1" pin="PC6" pad="93"/>- <connect gate="G$1" pin="VDD@10" pad="92"/>- <connect gate="G$1" pin="VDD33USB" pad="91"/>- <connect gate="G$1" pin="VDD50USB" pad="90"/>- <connect gate="G$1" pin="VSS@11" pad="89"/>+ <connect gate="G$1" pin="VDD@12" pad="92"/>+ <connect gate="G$1" pin="VDD33_USB" pad="91"/>+ <connect gate="G$1" pin="VDD50_USB" pad="90"/>+ <connect gate="G$1" pin="VSS@12" pad="89"/> <connect gate="G$1" pin="PG8" pad="88"/> <connect gate="G$1" pin="PG7" pad="87"/> <connect gate="G$1" pin="PG6" pad="86"/>@@ -521,8 +522,8 @@ <connect gate="G$1" pin="PD13" pad="83"/> <connect gate="G$1" pin="PD12" pad="82"/> <connect gate="G$1" pin="PD11" pad="81"/>- <connect gate="G$1" pin="VSS@12" pad="80"/>- <connect gate="G$1" pin="VDD@11" pad="79"/>+ <connect gate="G$1" pin="VSS@13" pad="80"/>+ <connect gate="G$1" pin="VDD@13" pad="79"/> <connect gate="G$1" pin="PD10" pad="78"/> <connect gate="G$1" pin="PD9" pad="77"/> <connect gate="G$1" pin="PD8" pad="76"/>@@ -530,7 +531,17 @@ <connect gate="G$1" pin="PB14" pad="74"/> <connect gate="G$1" pin="PB13" pad="73"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="STM32H745ZIT6" constant="no"/>+ <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886235171459072" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32h745zit6" constant="no"/>+ <attribute name="MOUSER_PN" value="511-STM32H745ZIT6" constant="no"/>+ <attribute name="DIGIKEY_PN" value="497-19501-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C730193" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>