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STM32H742ZIT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32H742ZIT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

STM32H742ZIT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 output GPIO port E pin 2; configurable for TRACECLK, SAI1 audio interface, SPI4 clock, FMC address line, or QUADSPI interface functions.
2 PE3 output GPIO port E pin 3; configurable for TRACED0, TIM15 break-in, SAI1 serial audio interface, or FMC functions.
3 PE4 output GPIO port E pin 4; configurable for TRACED1, SAI1 digital interface, DFSDM modulator input, TIM15 channel 1N, or DCMI camera interface.
4 PE5 output GPIO port E pin 5; configurable for TRACED2, SAI1 clock, DFSDM clock input, TIM15 channel 1, or FMC address line.
5 PE6 output GPIO port E pin 6; configurable for TRACED3, TIM1 break-in with comparator, SAI1 data, TIM15 channel 2, or DCMI interface.
6 VBAT power_in Backup domain power supply input for RTC, backup SRAM, and backup registers; accepts 1.2 to 3.6 V.
7 PC13 output GPIO port C pin 13; general-purpose I/O with RTC tamper input and wake-up capability.
8 PC14-OSC32_IN bidirectional GPIO port C pin 14 / 32 kHz oscillator input; default function is LSE crystal oscillator input, configurable as GPIO.
9 PC15-OSC32_OUT bidirectional GPIO port C pin 15 / 32 kHz oscillator output; default function is LSE crystal oscillator output, configurable as GPIO.
10 PF0 output GPIO port F pin 0; configurable for I2C2 SDA or FMC address line 0.
11 PF1 output GPIO port F pin 1; configurable for I2C2 SCL or FMC address line 1.
12 PF2 output GPIO port F pin 2; configurable for I2C2 SMBA or FMC address line 2.
13 PF3 output GPIO port F pin 3; configurable for FMC address line 3 or analog input to ADC3 channel 5.
14 PF4 output GPIO port F pin 4; configurable for FMC address line 4 or analog input to ADC3 channels 5N/9.
15 PF5 output GPIO port F pin 5; configurable for FMC address line 5 or analog input to ADC3 channel 4.
16 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
17 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
18 PF6 output GPIO port F pin 6; configurable for TIM16 channel 1, SPI5 NSS, SAI1 serial audio, UART7, or QUADSPI interface; analog input ADC3.
19 PF7 output GPIO port F pin 7; configurable for TIM17 channel 1, SPI5 clock, SAI1 audio MCLK, UART7 TX, or QUADSPI; analog input ADC3.
20 PF8 output GPIO port F pin 8; configurable for TIM16 channel 1N, SPI5 MISO, SAI1 clock, UART7 RTS, or QUADSPI; analog input ADC3.
21 PF9 output GPIO port F pin 9; configurable for TIM17 channel 1N, SPI5 MOSI, SAI1 frame sync, UART7 CTS, or QUADSPI; analog input ADC3.
22 PF10 output GPIO port F pin 10; configurable for TIM16 break-in, SAI1 data, QUADSPI clock, DCMI data, or LCD control; analog input ADC3.
23 PH0-OSC_IN bidirectional GPIO port H pin 0 / HSE oscillator input; default function is main oscillator input (4-48 MHz), configurable as GPIO.
24 PH1-OSC_OUT bidirectional GPIO port H pin 1 / HSE oscillator output; default function is main oscillator output, configurable as GPIO.
25 NRST input System reset input with internal pull-up and Schmitt trigger; assert low for minimum 1 µs to reset device.
26 PC0 output GPIO port C pin 0; configurable for DFSDM clock, SAI2 frame sync, OTG HS ULPI, FMC SDRAM WE, or LCD; analog input ADC1/2/3.
27 PC1 output GPIO port C pin 1; configurable for SAI1 data, DFSDM input, SPI2/I2S2, SDMMC2 clock, ETH MDC, or LCD; analog input ADC1/2/3.
28 PC2_C output Analog-only input pad for ADC3 channels 1N/0 with internal analog switch to PC2; not available in GPIO mode.
29 PC3_C output Analog-only input pad for ADC3 channel 1 with internal analog switch to PC3; not available in GPIO mode.
30 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
31 VSSA power_in Ground reference for analog circuits; must be connected to VSS external ground plane with star connection.
32 VREF+ power_in Analog reference voltage input for ADC/DAC/COMP; must be decoupled with 100 nF capacitor and equals VDDA or external source.
33 VDDA power_in Analog power supply; accepts 1.62 to 3.6 V for ADC operation and must be decoupled with 100 nF + 1 µF capacitors.
34 PA0 bidirectional GPIO port A pin 0; configurable for TIM2/TIM5 channels, USART2 CTS, UART4/SDMMC2, SAI2, ETH MII, or LCD; analog input ADC1.
35 PA1 bidirectional GPIO port A pin 1; configurable for TIM2/TIM5 channels, USART2 RTS, UART4, QUADSPI, SAI2 MCLK, ETH RMII, or LCD; analog input ADC1.
36 PA2 bidirectional GPIO port A pin 2; configurable for TIM2 channel 3, USART2 TX, SAI2 clock, ETH MDIO/MDIOS, or LCD; analog input ADC1/2.
37 PA3 bidirectional GPIO port A pin 3; configurable for TIM2 channel 4, USART2 RX, LCD, OTG HS ULPI, or ETH MII; analog input ADC1/2.
38 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
39 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
40 PA4 bidirectional GPIO port A pin 4; configurable for SPI1/SPI3 NSS, USART2 clock, DCMI HSYNC, LCD VSYNC; analog input ADC1/2 channel 18, DAC1 output 1.
41 PA5 bidirectional GPIO port A pin 5; configurable for TIM2 ETR, SPI1 clock, OTG HS ULPI clock, LCD; analog input ADC1/2, DAC1 output 2; no positive injection.
42 PA6 bidirectional GPIO port A pin 6; configurable for TIM1/TIM3/TIM8/TIM13 channels, SPI1 MISO, MDIOS, DCMI PIXCLK, or LCD; analog input ADC1/2.
43 PA7 bidirectional GPIO port A pin 7; configurable for TIM1/TIM3/TIM8/TIM14 channels, SPI1 MOSI, ETH MII/RMII CRS, FMC SDNWE; analog input ADC1/2, OPAMP1 inverting input.
44 PC4 bidirectional GPIO port C pin 4; configurable for DFSDM clock, I2S1 MCLK, SPDIFRX, ETH MII/RMII RXD0, FMC SDNE0; analog input ADC1/2, OPAMP1 output.
45 PC5 bidirectional GPIO port C pin 5; configurable for SAI1 data, DFSDM data, SPDIFRX, SAI4, ETH MII/RMII RXD1, FMC SDCKE0; analog input ADC1/2, OPAMP1 inverting input.
46 PB0 bidirectional GPIO port B pin 0; configurable for TIM1/TIM3/TIM8 channels, DFSDM output, LCD, OTG HS ULPI, or ETH MII; analog input ADC1/2, OPAMP1 non-inverting input.
47 PB1 bidirectional GPIO port B pin 1; configurable for TIM1/TIM3/TIM8 channels, DFSDM, LCD, OTG HS ULPI, or ETH MII; analog input ADC1/2, OPAMP1 comparator input.
48 PB2 bidirectional GPIO port B pin 2; configurable for RTC output, SAI1 data, DFSDM clock, SPI3/I2S3 MOSI, QUADSPI clock, or LCD; OPAMP1 non-inverting input.
49 PF11 bidirectional GPIO port F pin 11; configurable for SPI5 MOSI, SAI2 data, FMC SDNRAS, or DCMI data line 12; analog input ADC1.
50 PF12 bidirectional GPIO port F pin 12; configurable for FMC address line 6; analog input ADC1 channels 2N/6.
51 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
52 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
53 PF13 bidirectional GPIO port F pin 13; configurable for DFSDM data input, I2C4 SMBA, or FMC address line 7; analog input ADC2.
54 PF14 bidirectional GPIO port F pin 14; configurable for DFSDM clock, I2C4 SCL, or FMC address line 8; analog input ADC2 channels 2N/6.
55 PF15 bidirectional GPIO port F pin 15; configurable for I2C4 SDA or FMC address line 9; high-speed low-voltage I/O.
56 PG0 bidirectional GPIO port G pin 0; configurable for FMC address line 10; high-speed low-voltage I/O.
57 PG1 bidirectional GPIO port G pin 1; configurable for FMC address line 11; analog input OPAMP2 non-inverting input; 3.3 V tolerant.
58 PE7 bidirectional GPIO port E pin 7; configurable for TIM1 ETR, DFSDM data, UART7 RX, QUADSPI, or FMC data; OPAMP2 output, COMP2 inverting input.
59 PE8 bidirectional GPIO port E pin 8; configurable for TIM1 channel 1N, DFSDM clock, UART7 TX, QUADSPI, or FMC data; OPAMP2 inverting input, COMP2 output.
60 PE9 bidirectional GPIO port E pin 9; configurable for TIM1 channel 1, DFSDM output, UART7 RTS, QUADSPI, or FMC data; OPAMP2 non-inverting input.
61 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
62 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
63 PE10 bidirectional GPIO port E pin 10; configurable for TIM1 channel 2N, DFSDM data, UART7 CTS, QUADSPI, or FMC data; COMP2 inverting input.
64 PE11 bidirectional GPIO port E pin 11; configurable for TIM1 channel 2, DFSDM clock, SPI4 NSS, SAI2, FMC, or LCD; COMP2 non-inverting input.
65 PE12 bidirectional GPIO port E pin 12; configurable for TIM1 channel 3N, DFSDM data, SPI4 clock, SAI2, FMC, or LCD B4; high-speed low-voltage I/O.
66 PE13 bidirectional GPIO port E pin 13; configurable for TIM1 channel 3, DFSDM clock, SPI4 MISO, SAI2, FMC, or LCD DE; COMP2 output; high-speed.
67 PE14 bidirectional GPIO port E pin 14; configurable for TIM1 channel 4, SPI4 MOSI, SAI2 MCLK, FMC, or LCD clock; high-speed low-voltage I/O.
68 PE15 bidirectional GPIO port E pin 15; configurable for TIM1 break-in with comparator, FMC data, TIM1 comparator output, or LCD R7; high-speed I/O.
69 PB10 bidirectional GPIO port B pin 10; configurable for TIM2 channel 3, I2C2 SCL, SPI2/I2S2 clock, USART3 TX, QUADSPI, or LCD G4; 5 V tolerant with FM+ I2C.
70 PB11 bidirectional GPIO port B pin 11; configurable for TIM2 channel 4, I2C2 SDA, DFSDM, USART3 RX, OTG HS ULPI, or LCD G5; 5 V tolerant with FM+ I2C.
71 VCAP passive Main regulator output stabilization capacitor pin; connect two 2.2 µF capacitors with ESR < 100 mΩ to this pin and VSS.
72 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
73 PB12 bidirectional GPIO port B pin 12; configurable for TIM1 break-in, I2C2 SMBA, SPI2/I2S2 NSS, USART3 clock, FDCAN2 RX, OTG HS ULPI, or ETH MII TXD0; USB tolerant.
74 PB13 bidirectional GPIO port B pin 13; configurable for TIM1 channel 1N, LPTIM2 output, SPI2/I2S2 clock, USART3 CTS, FDCAN2 TX, OTG HS ULPI, or ETH MII; USB VBUS.
75 PB14 bidirectional GPIO port B pin 14; configurable for TIM1/TIM12/TIM8 channels, USART1 TX, SPI2/I2S2 MISO, USART3 RTS, UART4, SDMMC2, or OTG HS DM; USB tolerant.
76 PB15 bidirectional GPIO port B pin 15; configurable for RTC reference, TIM1/TIM12/TIM8 channels, USART1 RX, SPI2/I2S2 MOSI, UART4 CTS, SDMMC2, or OTG HS DP; USB.
77 PD8 bidirectional GPIO port D pin 8; configurable for DFSDM clock, SAI3 clock, USART3 TX, SPDIFRX, or FMC data; high-speed low-voltage I/O.
78 PD9 bidirectional GPIO port D pin 9; configurable for DFSDM data, SAI3 data, USART3 RX, FDCAN2 RXFD mode, or FMC data; high-speed I/O.
79 PD10 bidirectional GPIO port D pin 10; configurable for DFSDM output, SAI3 frame sync, USART3 clock, FDCAN2 TXFD mode, FMC data, or LCD B3; high-speed.
80 PD11 bidirectional GPIO port D pin 11; configurable for LPTIM2 input, I2C4 SMBA, USART3 CTS, QUADSPI, SAI2, or FMC address line A16; high-speed I/O.
81 PD12 bidirectional GPIO port D pin 12; configurable for LPTIM1 input, TIM4 channel 1, LPTIM2 input, I2C4 SCL, USART3 RTS, QUADSPI, or SAI2; high-speed I/O.
82 PD13 bidirectional GPIO port D pin 13; configurable for LPTIM1 output, TIM4 channel 2, I2C4 SDA, QUADSPI BK1 IO3, or SAI2 clock; high-speed I/O.
83 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
84 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
85 PD14 bidirectional GPIO port D pin 14; configurable for TIM4 channel 3, SAI3 MCLK, UART8 CTS, or FMC data D0; high-speed I/O.
86 PD15 bidirectional GPIO port D pin 15; configurable for TIM4 channel 4, SAI3 MCLK, UART8 RTS, or FMC data D1; high-speed I/O.
87 PG2 bidirectional GPIO port G pin 2; configurable for TIM8 break-in with comparator or FMC address line A12; high-speed low-voltage I/O.
88 PG3 bidirectional GPIO port G pin 3; configurable for TIM8 break-in 2 with comparator or FMC address line A13; high-speed I/O.
89 PG4 bidirectional GPIO port G pin 4; configurable for TIM1 break-in 2 with comparator or FMC address line A14/BA0; high-speed I/O.
90 PG5 bidirectional GPIO port G pin 5; configurable for TIM1 ETR or FMC address line A15/BA1; high-speed I/O.
91 PG6 bidirectional GPIO port G pin 6; configurable for TIM17 break-in, HRTIM channel E1, QUADSPI, FMC NE3, DCMI, or LCD R7; high-speed I/O.
92 PG7 bidirectional GPIO port G pin 7; configurable for HRTIM channel E2, SAI1 MCLK, USART6 clock, FMC INT, DCMI, or LCD clock; high-speed I/O.
93 PG8 bidirectional GPIO port G pin 8; configurable for TIM8 ETR, SPI6 NSS, USART6 RTS, SPDIFRX, ETH PPS, FMC SDCLK, or LCD G7; high-speed I/O.
94 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
95 VDD33USB power_in 3.3 V USB power supply for OTG_HS internal PHY and comparators; accepts 3.0 to 3.6 V with 100 nF decoupling.
96 PC6 bidirectional GPIO port C pin 6; configurable for HRTIM channel A1, TIM3 channel 1, TIM8 channel 1, I2S2 MCLK, USART6 TX, SDMMC1, FMC NWAIT, or DCMI; high-speed I/O.
97 PC7 bidirectional GPIO port C pin 7; configurable for HRTIM channel A2, TIM3/TIM8 channels, I2S3 MCLK, USART6 RX, SDMMC1, FMC NE1, SWPMI TX, or DCMI; high-speed I/O.
98 PC8 bidirectional GPIO port C pin 8; configurable for TRACED1, HRTIM channel B1, TIM3/TIM8 channels, USART6 clock, FMC NE2/NCE, SWPMI RX, or SDMMC1; high-speed I/O.
99 PC9 bidirectional GPIO port C pin 9; configurable for MCO2, TIM3/TIM8 channels, I2C3 SDA, I2S clock input, UART5 CTS, QUADSPI, or LCD B2; high-speed I/O.
100 PA8 bidirectional GPIO port A pin 8; configurable for MCO1, TIM1 channel 1, HRTIM channel B2, TIM8 break-in 2, I2C3 SCL, USART1 clock, OTG FS SOF, UART7, or LCD; 5 V tolerant.
101 PA9 bidirectional GPIO port A pin 9; configurable for TIM1 channel 2, HRTIM channel C1, LPUART1 TX, I2C3 SMBA, SPI2/I2S2 clock, USART1 TX, FDCAN1, or DCMI; USB VBUS; 5 V tolerant.
102 PA10 bidirectional GPIO port A pin 10; configurable for TIM1 channel 3, HRTIM channel C2, LPUART1 RX, USART1 RX, FDCAN1 TXFD mode, OTG FS ID, MDIOS, or LCD; USB tolerant.
103 PA11 bidirectional GPIO port A pin 11; configurable for TIM1 channel 4, HRTIM channel D1, LPUART1 CTS, SPI2/I2S2 NSS, UART4 RX, USART1 CTS, FDCAN1 RX, or OTG FS DM; USB.
104 PA12 bidirectional GPIO port A pin 12; configurable for TIM1 ETR, HRTIM channel D2, LPUART1 RTS, SPI2/I2S2 clock, UART4 TX, USART1 RTS, SAI2, FDCAN1 TX, or OTG FS DP; USB.
105 PA13 input JTAG TMS / SWD DIO pin; JTAG/SWD debug interface input for microcontroller programming and debugging; pull-up configured.
106 VCAP passive Main regulator output stabilization capacitor pin; connect two 2.2 µF capacitors with ESR < 100 mΩ to this pin and VSS.
107 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
108 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
109 PA14 input JTAG TCK / SWD clock pin; JTAG/SWD debug interface clock input for microcontroller programming; pull-up configured.
110 PA15 input JTAG TDI pin; configurable for TIM2 ETR, HRTIM filter 1, CEC, SPI1/SPI3/SPI6 NSS, UART4/UART7, or GPIO; JTAG debug function.
111 PC10 bidirectional GPIO port C pin 10; configurable for HRTIM EEV1, DFSDM clock, SPI3/I2S3 clock, USART3/UART4 TX, QUADSPI, SDMMC1 D2, or DCMI; high-speed I/O.
112 PC11 bidirectional GPIO port C pin 11; configurable for HRTIM filter 2, DFSDM data, SPI3/I2S3 MISO, USART3/UART4 RX, QUADSPI BK2 NCS, SDMMC1 D3, or DCMI; high-speed.
113 PC12 bidirectional GPIO port C pin 12; configurable for TRACED3, HRTIM EEV2, SPI3/I2S3 MOSI, USART3 clock, UART5 TX, SDMMC1 clock, or DCMI D9; high-speed I/O.
114 PD0 bidirectional GPIO port D pin 0; configurable for DFSDM clock, SAI3 clock, UART4 RX, FDCAN1 RX, or FMC data D2; high-speed I/O.
115 PD1 bidirectional GPIO port D pin 1; configurable for DFSDM data, SAI3 data, UART4 TX, FDCAN1 TX, or FMC data D3; high-speed I/O.
116 PD2 bidirectional GPIO port D pin 2; configurable for TRACED2, TIM3 ETR, UART5 RX, SDMMC1 command, DCMI D11; high-speed I/O.
117 PD3 bidirectional GPIO port D pin 3; configurable for DFSDM output, SPI2/I2S2 clock, USART2 CTS, FMC clock, or DCMI D5 LCD G7; high-speed I/O.
118 PD4 bidirectional GPIO port D pin 4; configurable for HRTIM filter 3, SAI3 frame sync, USART2 RTS, FDCAN1 RXFD mode, or FMC NOE; high-speed I/O.
119 PD5 bidirectional GPIO port D pin 5; configurable for HRTIM EEV3, USART2 TX, FDCAN1 TXFD mode, or FMC NWE; high-speed I/O.
120 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
121 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
122 PD6 bidirectional GPIO port D pin 6; configurable for SAI1 data, DFSDM, SPI3/I2S3 MOSI, SAI1 data, USART2 RX, SAI4, FDCAN2 RXFD, SDMMC2 clock, or DCMI; high-speed.
123 PD7 bidirectional GPIO port D pin 7; configurable for DFSDM data, SPI1/I2S1 MOSI, USART2 clock, SPDIFRX, or SDMMC2 command FMC NE1; high-speed I/O.
124 PG9 bidirectional GPIO port G pin 9; configurable for SPI1/I2S1 MISO, USART6 RX, SPDIFRX, QUADSPI BK2 IO2, SAI2, FMC NE2/NCE, or DCMI VSYNC; high-speed.
125 PG10 bidirectional GPIO port G pin 10; configurable for HRTIM filter 5, SPI1/I2S1 NSS, LCD G3, SAI2 data, FMC NE3, DCMI D2, or LCD B2; high-speed I/O.
126 PG11 bidirectional GPIO port G pin 11; configurable for LPTIM1 input, HRTIM EEV4, SPI1/I2S1 clock, SPDIFRX, SDMMC2 D2, ETH MII TX, DCMI D3, or LCD B3; high-speed.
127 PG12 bidirectional GPIO port G pin 12; configurable for LPTIM1 input, HRTIM EEV5, SPI6 MISO, USART6 RTS, SPDIFRX, LCD B4, ETH MII TXD1, FMC NE4, or LCD B1; high-speed.
128 PG13 bidirectional GPIO port G pin 13; configurable for TRACED0, LPTIM1 output, HRTIM EEV10, SPI6 clock, USART6 CTS, ETH MII TXD0, FMC A24, or LCD R0; high-speed.
129 PG14 bidirectional GPIO port G pin 14; configurable for TRACED1, LPTIM1 ETR, SPI6 MOSI, USART6 TX, QUADSPI BK2 IO3, ETH MII TXD1, FMC A25, or LCD B0; high-speed.
130 VSS power_in Ground reference for digital logic and I/O blocks; must be connected to external ground plane.
131 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.
132 PG15 bidirectional GPIO port G pin 15; configurable for USART6 CTS, FMC SDNCAS, DCMI D13; high-speed I/O.
133 PB3 output JTAG TDO / SWD trace output pin; configurable for TIM2 channel 2, HRTIM filter 4, SPI1/I2S1 clock, SPI3/I2S3 clock, SPI6, SDMMC2 D2, CRS SYNC, UART7.
134 PB4 output NJTRST pin; JTAG nTRST (negative reset) configurable for TIM16 break, TIM3 channel 1, HRTIM EEV6, SPI1/I2S1/SPI3/SPI6 MISO, SDMMC2 D3, or UART7.
135 PB5 bidirectional GPIO port B pin 5; configurable for TIM17 break, TIM3 channel 2, HRTIM EEV7, I2C1/I2C4 SMBA, SPI1/I2S1/SPI3/SPI6 MOSI, FDCAN2 RX, OTG HS ULPI, FMC, or DCMI.
136 PB6 bidirectional GPIO port B pin 6; configurable for TIM16 channel 1N, TIM4 channel 1, HRTIM EEV8, I2C1 SCL, CEC, I2C4 SCL, USART1 TX, LPUART1 TX, FDCAN2 TX, QUADSPI, or DFSDM; 5 V tolerant.
137 PB7 bidirectional GPIO port B pin 7; configurable for TIM17 channel 1N, TIM4 channel 2, HRTIM EEV9, I2C1 SDA, I2C4 SDA, USART1 RX, LPUART1 RX, FDCAN2 TXFD, DFSDM, or FMC NL; 5 V tolerant.
138 BOOT0 input Boot pin for selecting boot mode; accepts 0-9 V input; selects between main Flash boot (low) or system memory boot (high); must be tied low for normal operation.
139 PB8 bidirectional GPIO port B pin 8; configurable for TIM16 channel 1, TIM4 channel 3, DFSDM input, I2C1 SCL, I2C4 SCL, SDMMC1 CKIN, UART4 RX, FDCAN1 RX, SDMMC2 D4, or ETH; high-speed.
140 PB9 bidirectional GPIO port B pin 9; configurable for TIM17 channel 1, TIM4 channel 4, DFSDM data, I2C1 SDA, SPI2/I2S2 NSS, I2C4 SDA, SDMMC1 CDIR, UART4 TX, FDCAN1 TX, SDMMC2 D5; high-speed.
141 PE0 bidirectional GPIO port E pin 0; configurable for LPTIM1 ETR, TIM4 ETR, HRTIM SCIN, LPTIM2 ETR, UART8 RX, FDCAN1 RXFD mode, SAI2 MCLK, FMC NBL0, or DCMI; high-speed I/O.
142 PE1 bidirectional GPIO port E pin 1; configurable for LPTIM1 input, HRTIM SCOUT, UART8 TX, FDCAN1 TXFD mode, or FMC NBL1 DCMI D3; high-speed I/O.
143 PDR_ON input Power domain ready output enable pin; input to enable external power regulator bypass logic when internal regulator is ON.
144 VDD power_in Main power supply input for digital circuitry; accepts 1.62 to 3.6 V and must be decoupled with 100 nF + 4.7 µF capacitors.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: STM32H742ZIT6
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: stm32h742zit6-etched.step / stm32h742zit6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32h742zit6.step / stm32h742zit6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (357 pp, sha256 9c74d2015445f7c3, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF