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STM32H573VIT6

Public Made by Adom

by adom

STMICROELECTRONICS Global Sourcing Parts, LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32H573VIT6

STMICROELECTRONICS · Global Sourcing Parts · LQFP-100(14x14)

STM32H573VIT6 from STMICROELECTRONICS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional FT_h 5 V-tolerant GPIO with TRACECLK, LPTIM1_IN2, SAI1_CK1, SPI4_SCK, USART10_RX, OCTOSPI1_IO2, ETH_MII_TXD3, FMC_A23, DCMI_D3 and EVENTOUT alternate functions.
2 PE3 bidirectional FT_h 5 V-tolerant GPIO with TRACED0, TIM15_BKIN, SAI1_SD_B, USART10_TX, FMC_A19 and EVENTOUT alternate functions, and TAMP_IN6/TAMP_OUT3 additional functions.
3 PE4 bidirectional FT_h 5 V-tolerant GPIO with TRACED1, SAI1_D2, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4 and EVENTOUT alternate functions, and TAMP_IN7/TAMP_OUT8 additional functions.
4 PE5 bidirectional FT_h 5 V-tolerant GPIO with TRACED2, SAI1_CK2, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6 and EVENTOUT alternate functions, and TAMP_IN8/TAMP_OUT7 additional functions.
5 PE6 bidirectional FT_h 5 V-tolerant GPIO with TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCLK_B, FMC_A22, DCMI_D7 and EVENTOUT alternate functions, and TAMP_IN3/TAMP_OUT6 additional functions.
6 VBAT power_in Supply pin for the RTC, backup registers and backup domain when VDD is not present.
7 PC13 bidirectional FT_t GPIO supplied through the VSW power switch, so output speed must not exceed 2 MHz with a maximum 30 pF load and it must not source current; additional functions TAMP_IN1/TAMP_OUT2/TAMP_OUT3, RTC_OUT1/RTC_TS and WKUP4.
8 PC14-OSC32_IN bidirectional FT GPIO supplied through the VSW power switch (2 MHz and 30 pF output limit) that also serves as the OSC32_IN LSE crystal input.
9 PC15-OSC32_OUT bidirectional FT GPIO supplied through the VSW power switch (2 MHz and 30 pF output limit) that also serves as the OSC32_OUT LSE crystal output.
10 VSS power_in Digital ground supply pin.
11 VDD power_in Main digital supply pin, 1.71 V to 3.6 V with HSLV = 0 (1.71 V to 2.7 V with HSLV = 1).
12 PH0-OSC_IN bidirectional FT GPIO that also serves as the OSC_IN 4-50 MHz HSE oscillator input.
13 PH1-OSC_OUT bidirectional FT GPIO that also serves as the OSC_OUT 4-50 MHz HSE oscillator output.
14 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
15 PC0 bidirectional FT_a GPIO with TIM16_BKIN, SAI1_MCLK_A, SPI2_RDY, SAI2_FS_B, FMC_A25, OCTOSPI1_IO7, FMC_SDNWE and EVENTOUT alternate functions, and ADC12_INP10 additional function.
16 PC1 bidirectional FT_ah GPIO with TRACED0, SAI1_D1, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, USART11_RTS/DE, SAI2_SD_A, SDMMC2_CK, OCTOSPI1_IO4, ETH_MDC alternate functions, and ADC12_INP11/INN10, TAMP_IN3/TAMP_OUT5, WKUP6 additional functions.
17 PC2 bidirectional FT_a GPIO with PWR_CSLEEP, TIM17_CH1, TIM4_CH4, SPI2_MISO/I2S2_SDI, OCTOSPI1_IO5/IO2, ETH_MII_TXD2, FMC_SDNE0 alternate functions, and ADC12_INP12/INN11 additional functions.
18 PC3 bidirectional FT_a GPIO with PWR_CSTOP, SAI1_D3, LPTIM3_CH1, SPI2_MOSI/I2S2_SDO, OCTOSPI1_IO6/IO0, ETH_MII_TX_CLK, FMC_SDCKE0 alternate functions, and ADC12_INP13/INN12 additional functions.
19 VSSA power_in Analog ground supply pin.
20 VREF- power_in Negative reference voltage pin for the ADC and DAC.
21 VREF+ power_in Positive reference voltage pin, also the internal VREFBUF output; VREF+ must not exceed VDDA by more than 0.4 V.
22 VDDA power_in Analog supply pin for ADC, DAC and other analog blocks.
23 PA0 bidirectional FT_at GPIO with TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SPI6_NSS, SPI3_RDY, USART2_CTS/NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH_MII_CRS alternate functions, and ADC12_INP0/INN1, TAMP_IN2/TAMP_OUT1, WKUP1 additional functions.
24 PA1 bidirectional FT_aht GPIO with TIM2_CH2, TIM5_CH2, TIM15_CH1N, LPTIM1_IN1, OCTOSPI1_DQS, USART2_RTS/DE, UART4_RX, OCTOSPI1_IO3, SAI2_MCLK_B, ETH_MII_RX_CLK/RMII_REF_CLK alternate functions, and ADC12_INP1, TAMP_IN5/TAMP_OUT4 additional functions.
25 PA2 bidirectional FT_hat GPIO with TIM2_CH3, TIM5_CH3, TIM15_CH1, LPTIM1_IN2, USART2_TX, SAI2_SCK_B, ETH_MDIO alternate functions, and ADC12_INP14, TAMP_IN4/TAMP_OUT3, WKUP2 additional functions.
26 PA3 bidirectional FT_ah GPIO with TIM2_CH4, TIM5_CH4, OCTOSPI1_CLK, TIM15_CH2, SPI2_NSS/I2S2_WS, SAI1_SD_B, USART2_RX, ETH_MII_COL alternate functions, and ADC12_INP15 additional function.
27 VSS power_in Digital ground supply pin.
28 VDD power_in Main digital supply pin, 1.71 V to 3.6 V with HSLV = 0.
29 PA4 bidirectional TT_a 3.6 V-tolerant GPIO with TIM5_ETR, LPTIM2_CH1, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, DCMI_HSYNC alternate functions, and ADC12_INP18, DAC1_OUT1 additional functions.
30 PA5 bidirectional TT_ah 3.6 V-tolerant GPIO with TIM2_CH1, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI6_SCK, ETH_MII_TX_EN/RMII_TX_EN, PSSI_D14 alternate functions, and ADC12_INP19/INN18, DAC1_OUT2 additional functions.
31 PA6 bidirectional FT_ah GPIO with TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, OCTOSPI1_IO3, USART11_TX, SPI6_MISO, TIM13_CH1, DCMI_PIXCLK alternate functions, and ADC12_INP3 additional function.
32 PA7 bidirectional FT_ah GPIO with TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, USART11_RX, SPI6_MOSI, TIM14_CH1, OCTOSPI1_IO2, ETH_MII_RX_DV, FMC_SDNWE/NWE alternate functions, and ADC12_INP7/INN3 additional functions.
33 PC4 bidirectional FT_a GPIO with TIM2_CH4, SAI1_CK1, LPTIM2_ETR, I2S1_MCK, USART3_RX, ETH_MII_RXD0/RMII_RXD0, FMC_SDNE0 alternate functions, and ADC12_INP4 additional function.
34 PC5 bidirectional FT_ah GPIO with TIM1_CH4N, SAI1_D3, PSSI_D15, SAI1_FS_A, UART12_RTS/DE, OCTOSPI1_DQS, ETH_MII_RXD1/RMII_RXD1, FMC_SDCKE0 alternate functions, and ADC12_INP8/INN4 additional functions.
35 PB0 bidirectional FT_ah GPIO with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, OCTOSPI1_IO1, USART11_CK, UART4_CTS, ETH_MII_RXD2, LPTIM3_CH1 alternate functions, and ADC12_INP9/INN5 additional functions.
36 PB1 bidirectional FT_ah GPIO with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OCTOSPI1_IO0, ETH_MII_RXD3, LPTIM3_CH2 alternate functions, and ADC12_INP5 additional function.
37 PB2 bidirectional FT_ah GPIO with RTC_OUT2, SAI1_D1, TIM8_CH4N, SPI1_RDY, LPTIM1_CH1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, OCTOSPI1_CLK/DQS, SDMMC1_CMD, LPTIM5_ETR alternate functions, and LSCO additional function.
38 PE7 bidirectional FT_ah GPIO with TIM1_ETR, UART12_RTS/DE, UART7_RX, OCTOSPI1_IO4, FMC_D4/AD4 alternate functions.
39 PE8 bidirectional FT_ah GPIO with TIM1_CH1N, UART12_CTS/NSS, UART7_TX, OCTOSPI1_IO5, FMC_D5/AD5 alternate functions.
40 PE9 bidirectional FT_ah GPIO with TIM1_CH1, UART12_RX, UART7_RTS/DE, OCTOSPI1_IO6, FMC_D6/AD6 alternate functions.
41 PE10 bidirectional FT_ah GPIO with TIM1_CH2N, UART12_TX, UART7_CTS, OCTOSPI1_IO7, FMC_D7/AD7 alternate functions.
42 PE11 bidirectional FT_ah GPIO with TIM1_CH2, SPI1_RDY, SPI4_NSS, OCTOSPI1_NCS, SAI2_SD_B, FMC_D8/AD8 alternate functions.
43 PE12 bidirectional FT_h 5 V-tolerant GPIO with TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9/AD9 alternate functions.
44 PE13 bidirectional FT_h 5 V-tolerant GPIO with TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10/AD10 alternate functions.
45 PE14 bidirectional FT_h 5 V-tolerant GPIO with TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11/AD11 alternate functions.
46 PE15 bidirectional FT_h 5 V-tolerant GPIO with TIM1_BKIN, TIM1_CH4N, USART10_CK, FMC_D12/AD12 alternate functions.
47 PB10 bidirectional FT_f Fm+ capable GPIO with TIM2_CH3, LPTIM3_CH1, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OCTOSPI1_NCS, ETH_MII_RX_ER alternate functions.
48 VCAP passive Pin for the external capacitor that stabilizes the embedded core voltage regulator (LDO); two VCAP capacitors are required per AN5711.
49 VSS power_in Digital ground supply pin.
50 VDD power_in Main digital supply pin, 1.71 V to 3.6 V with HSLV = 0.
51 PB12 bidirectional FT_fh Fm+ capable GPIO with TIM1_BKIN, OCTOSPI1_NCLK, I2C2_SDA, SPI2_NSS/I2S2_WS, UCPD1_FRSTX, USART3_CK, FDCAN2_RX, ETH_MII_TXD0/RMII_TXD0, UART5_RX alternate functions.
52 PB13 bidirectional FT_c GPIO with USB Type-C PD function, TIM1_CH1N, LPTIM3_IN1, LPTIM2_CH1, I2C2_SMBA, SPI2_SCK/I2S2_CK, USART3_CTS/NSS, FDCAN2_TX, SDMMC1_D0, UART5_TX alternate functions, and UCPD1_CC1 additional function.
53 PB14 bidirectional FT_c GPIO with USB Type-C PD function, TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS/DE, UART4_RTS/DE, SDMMC2_D0, LPTIM3_ETR alternate functions, and UCPD1_CC2 additional function.
54 PB15 bidirectional FT_h GPIO with RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, USART11_CTS/NSS, UART4_CTS, SDMMC2_D1, OCTOSPI1_CLK, ETH_MII_TXD1/RMII_TXD1, DCMI_D2, UART5_RX alternate functions, and PVD_IN additional function.
55 PD8 bidirectional FT_h 5 V-tolerant GPIO with USART3_TX, FMC_D13/AD13 alternate functions.
56 PD9 bidirectional FT_h 5 V-tolerant GPIO with USART3_RX, FDCAN2_RX, FMC_D14/AD14 alternate functions.
57 PD10 bidirectional FT_h 5 V-tolerant GPIO with LPTIM2_CH2, USART3_CK, FMC_D15/AD15 alternate functions.
58 PD11 bidirectional FT_h 5 V-tolerant GPIO with SAI1_CK1, LPTIM2_IN2, I2C4_SMBA, USART3_CTS/NSS, UART4_RX, OCTOSPI1_IO0, SAI2_SD_A, FMC_A16/CLE alternate functions.
59 PD12 bidirectional FT_fh Fm+ capable GPIO with LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, I3C1_SCL, SAI1_D1, USART3_RTS/DE, UART4_TX, OCTOSPI1_IO1, SAI2_FS_A, FMC_A17/ALE, DCMI_D12 alternate functions.
60 PD13 bidirectional FT_fh Fm+ capable GPIO with LPTIM1_CH1, TIM4_CH2, LPTIM2_CH1, I2C4_SDA, I3C1_SDA, OCTOSPI1_IO3, SAI2_SCK_A, UART9_RTS/DE, FMC_A18, DCMI_D13, LPTIM4_IN1 alternate functions.
61 PD14 bidirectional FT_h 5 V-tolerant GPIO with TIM4_CH3, UART8_CTS, UART9_RX, FMC_D0/AD0 alternate functions.
62 PD15 bidirectional FT_h 5 V-tolerant GPIO with TIM4_CH4, UART8_RTS/DE, UART9_TX, FMC_D1/AD1 alternate functions.
63 PC6 bidirectional FT_h GPIO with TIM3_CH1, TIM8_CH1, I2S2_MCK, SAI1_SCK_A, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, OCTOSPI1_IO5, SDMMC1_D6, DCMI_D0 alternate functions.
64 PC7 bidirectional FT_h GPIO with TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, OCTOSPI1_IO6, SDMMC1_D7, DCMI_D1 alternate functions.
65 PC8 bidirectional FT_h GPIO with TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/DE, FMC_NE2/NCE, FMC_INT, FMC_ALE, SDMMC1_D0, DCMI_D2 alternate functions.
66 PC9 bidirectional FT_fh Fm+ capable GPIO with MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK, UART5_CTS, OCTOSPI1_IO0, FMC_CLE, SDMMC1_D1, DCMI_D3 alternate functions, and UCPD1_DB2 additional function.
67 PA8 bidirectional FT_fh Fm+ capable GPIO with MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, SPI1_RDY, USART1_CK, USB_SOF, UART7_RX, FMC_NOE, DCMI_D3 alternate functions.
68 PA9 bidirectional FT_d GPIO with USB Type-C dead battery function, TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, ETH_MII_TX_ER, FMC_NWE, DCMI_D0 alternate functions, and UCPD1_DB1 additional function.
69 PA10 bidirectional FT_h GPIO with TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX, FDCAN2_TX, SDMMC1_D0, DCMI_D1 alternate functions.
70 PA11 bidirectional FT_u GPIO supplied by VDDUSB with TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/NSS, FDCAN1_RX and USB_DM alternate functions.
71 PA12 bidirectional FT_u GPIO supplied by VDDUSB with TIM1_ETR, LPUART1_RTS/DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/DE, SAI2_FS_B, FDCAN1_TX and USB_DP alternate functions.
72 PA13 bidirectional FT GPIO that is JTMS/SWDIO after reset with the internal pull-up activated.
73 VDDUSB power_in Independent supply pin for the USB FS I/Os.
74 VSS power_in Digital ground supply pin.
75 VDD power_in Main digital supply pin, 1.71 V to 3.6 V with HSLV = 0.
76 PA14 bidirectional FT GPIO that is JTCK/SWCLK after reset with the internal pull-down activated.
77 PA15 bidirectional FT GPIO that is JTDI after reset with the internal pull-up activated, with TIM2_CH1, LPTIM3_IN2, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/DE, UART7_TX, FMC_NBL1, DCMI_D11 alternate functions.
78 PC10 bidirectional FT_h GPIO with LPTIM3_ETR, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1, ETH_MII_TXD0/RMII_TXD0, SDMMC1_D2, DCMI_D8 alternate functions.
79 PC11 bidirectional FT_h GPIO with LPTIM3_IN1, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS, SDMMC1_D3, DCMI_D4 alternate functions.
80 PC12 bidirectional FT_h GPIO with TRACED3, TIM15_CH1, SPI6_SCK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9 alternate functions.
81 PD0 bidirectional FT_h GPIO with TIM8_CH4N, UART4_RX, FDCAN1_RX, UART9_CTS, FMC_D2/AD2 alternate functions.
82 PD1 bidirectional FT_h GPIO with UART4_TX, FDCAN1_TX, FMC_D3/AD3 alternate functions.
83 PD2 bidirectional FT_h GPIO with TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD, DCMI_D11, LPTIM4_ETR alternate functions, and WKUP7 additional function.
84 PD3 bidirectional FT_h GPIO with SPI2_SCK/I2S2_CK, USART2_CTS/NSS, FMC_CLK, DCMI_D5 alternate functions, and WKUP8 additional function.
85 PD4 bidirectional FT_h GPIO with USART2_RTS/DE, OCTOSPI1_IO4, FMC_NOE alternate functions.
86 PD5 bidirectional FT_h GPIO with TIM1_CH4N, SPI2_RDY, USART2_TX, FDCAN1_TX, OCTOSPI1_IO5, FMC_NWE alternate functions.
87 PD6 bidirectional FT_sh GPIO supplied only by VDDIO2 with SAI1_D1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, OCTOSPI1_IO6, SDMMC2_CK, FMC_NWAIT, DCMI_D10 alternate functions.
88 PD7 bidirectional FT_sh GPIO supplied only by VDDIO2 with SPI1_MOSI/I2S1_SDO, USART2_CK, OCTOSPI1_IO7, SDMMC2_CMD, FMC_NE1/NCE, LPTIM4_OUT alternate functions.
89 PB3 bidirectional FT_fh Fm+ capable GPIO that is JTDO/TRACESWO after reset, with TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, UART12_CTS/NSS, SPI6_SCK, SDMMC2_D2, CRS_SYNC, UART7_RX, LPTIM6_ETR alternate functions.
90 PB4 bidirectional FT_h GPIO that is NJTRST after reset with the internal pull-up activated, with TIM16_BKIN, TIM3_CH1, OCTOSPI1_CLK, LPTIM1_CH2, SPI1/3 MISO, SPI2_NSS, SPI6_MISO, SDMMC2_D3, UART7_TX, DCMI_D7 alternate functions.
91 PB5 bidirectional FT_h GPIO with TIM17_BKIN, TIM3_CH2, OCTOSPI1_NCLK, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, UART5_RX alternate functions.
92 PB6 bidirectional FT_f Fm+ capable GPIO with TIM16_CH1N, TIM4_CH1, I3C1_SCL, I2C1_SCL, HDMI_CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPI1_NCS, FMC_SDNE1, DCMI_D5, UART5_TX alternate functions.
93 PB7 bidirectional FT_fa Fm+ capable GPIO with TIM17_CH1N, TIM4_CH2, I3C1_SDA, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, FDCAN1_TX, SDMMC2_D5/CKIN, FMC_NL, DCMI_VSYNC alternate functions, and WKUP5 additional function.
94 BOOT0 input Boot mode selection input pin.
95 PB8 bidirectional FT_fhs Fm+ capable GPIO supplied only by VDDIO2 with TIM16_CH1, TIM4_CH3, I3C1_SCL, I2C1_SCL, SPI4_RDY, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6 alternate functions.
96 PB9 bidirectional FT_fhs Fm+ capable GPIO supplied only by VDDIO2 with TIM17_CH1, TIM4_CH4, I3C1_SDA, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5/CKIN, SDMMC1_D5, DCMI_D7 alternate functions.
97 PE0 bidirectional FT_h GPIO with LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2, LPTIM2_ETR, SPI3_RDY, UART8_RX, FDCAN1_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2 alternate functions.
98 VCAP passive Pin for the external capacitor that stabilizes the embedded core voltage regulator (LDO); two VCAP capacitors are required per AN5711.
99 VSS power_in Digital ground supply pin.
100 VDD power_in Main digital supply pin, 1.71 V to 3.6 V with HSLV = 0.

Key specifications

Parameter Value
Manufacturer STMICROELECTRONICS
Package LQFP-100(14x14)
Category Global Sourcing Parts
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VDDx - VSS -0.3 4 V including VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT, VREF+ 127
I/O supply, HSLV = 0 VDDIOx - VSS -0.3 4 V HSLV = 0 127
I/O supply, HSLV = 1 VDDIOx - VSS -0.3 2.75 V HSLV = 1 127
Input voltage on FT_c pins VIN -0.3 5.5 V FT_c pins 127
Input voltage on TT_xx pins VIN -0.3 4 V TT_xx pins 127
Allowed voltage difference VREF+ > VDDA VREF+-VDDA 0.4 V 127
Variations between VDDx power pins /ΔVDDx/ 50 mV same domain 127
Variations between ground pins /VSSx-VSS/ 50 mV 127
Total current into all VDD lines ΣIVDD 350 mA source 128
Total current out of all VSS lines ΣIVSS 350 mA sink 128
Max current into each VDD pin IVDD 100 mA source 128
Max current out of each VSS pin IVSS 100 mA sink 128
Output current per I/O pin IIO(PIN) 20 mA sunk/sourced 128
Total output current sunk by all I/Os ΣIIO(PIN) 140 mA sink 128
Total output current sourced by all I/Os ΣIIO(PIN) 140 mA source 128
Injected current on FT_xxx, TT_xx, NRST pins IINJ(PIN) -5 0 mA 128
Total injected current Σ/IINJ(PIN)/ -25 25 mA sum of all I/Os and control pins 128
Storage temperature range TSTG -65 150 °C 128
Maximum junction temperature TJ 130 °C limited to 105 °C in VOS0 128
Standard operating voltage VDD 1.71 3.6 V HSLV = 0 128
Standard operating voltage HSLV VDD 1.71 2.7 V HSLV = 1 128
VDDIO2 supply voltage VDDIO2 1.08 3.6 V at least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used, HSLV = 0 129
VDDIO2 supply voltage HSLV VDDIO2 1.08 2.7 V at least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used, HSLV = 1 129
USB supply voltage VDDUSB 3 3.6 V USB is used 129
Analog supply voltage, ADC used VDDA 1.62 3.6 V ADC is used 129
Backup domain supply voltage VBAT 1.2 3.6 V 129
Core voltage VOS0 VCORE 1.3 1.35 1.4 V Internal regulator ON, VOS0 130
Core voltage VOS1 VCORE 1.15 1.2 1.26 V Internal regulator ON, VOS1 130
Core voltage VOS2 VCORE 1.05 1.1 1.15 V Internal regulator ON, VOS2 130
Core voltage VOS3 VCORE 0.95 1 1.05 V Internal regulator ON, VOS3 130
AHB clock frequency VOS0 fHCLK 250 MHz VOS0 130
Ambient temperature, suffix 6 TA -40 85 °C Maximum power dissipation 131
Junction temperature range VOS1-3 TJ -40 130 °C VOS1, VOS2, and VOS3 131
Junction temperature range VOS0 TJ -40 105 °C VOS0 131
POR/PDR threshold rising VPOR/PDR 1.62 1.67 1.71 V BORH_EN = 0, rising edge 136
POR/PDR threshold falling VPOR/PDR 1.58 1.62 1.68 V BORH_EN = 0, falling edge 136
Reset temporization after BOR0 tRSTTEMPO 377 550 μs VDD rising 136
Internal reference voltage VREFINT 1.18 1.216 1.255 V -40 °C < TJ < +130 °C 138
Reference voltage spread ΔVREFINT 5 15 mV -40 °C < TJ < +130 °C 138
Average temperature coefficient TCoeff 20 70 ppm/°C Average temperature coefficient 138
Run mode supply current IDD(Run) 32.1 37 mA All peripherals disabled, VOS0, 250 MHz, TJ = 25 °C, typ LDO 139
Cext LDO external capacitor CEXT 2.2 μF LDO enabled; ±20% tolerated 133

CAD (KiCad official)

  • Symbol: STM32H573VIT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32h573vit6-etched.step / stm32h573vit6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32h573vit6.step / stm32h573vit6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMICROELECTRONICS datasheet (273 pp, sha256 e66d535f5a5fcb6d, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF