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STM32H523RET6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32h523ret6factory-2.0.0extractor-text
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STM32H523RET6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32H523RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply for the RTC and backup registers, 1.2 V to 3.6 V.
2 PC13 bidirectional 5 V-tolerant GPIO (FT_t) with tamper function (TAMP_IN1/TAMP_OUT2/TAMP_OUT3), RTC_OUT1/RTC_TS and WKUP4; supplied through the power switch, so output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source.
3 PC14-OSC32_IN bidirectional 5 V-tolerant GPIO (FT) that serves as LSE oscillator input OSC32_IN; supplied through the power switch, so output use is limited to 2 MHz at 30 pF and no current sourcing.
4 PC15-OSC32_OUT bidirectional 5 V-tolerant GPIO (FT) that serves as LSE oscillator output OSC32_OUT; supplied through the power switch, so output use is limited to 2 MHz at 30 pF and no current sourcing.
5 PH0-OSC_IN bidirectional 5 V-tolerant GPIO (FT) that serves as HSE oscillator input OSC_IN for the 4-50 MHz HSE.
6 PH1-OSC_OUT bidirectional 5 V-tolerant GPIO (FT) that serves as HSE oscillator output OSC_OUT for the 4-50 MHz HSE.
7 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
8 PC0 bidirectional 5 V-tolerant GPIO (FT_a) with analog-switch function supplied by VDDA and ADC12_INP10 analog input; alternate functions include SPI4_MISO and OCTOSPI1_IO7.
9 PC1 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA, ADC12_INP11/ADC12_INN10 inputs, TAMP_IN3/TAMP_OUT5 and WKUP6 functions.
10 PC2 bidirectional 5 V-tolerant GPIO (FT_a) with analog-switch function supplied by VDDA, ADC12_INP12/ADC12_INN11 analog inputs and PWR_CSLEEP alternate function.
11 PC3 bidirectional 5 V-tolerant GPIO (FT_a) with analog-switch function supplied by VDDA, ADC12_INP13/ADC12_INN12 analog inputs and PWR_CSTOP alternate function.
12 VSSA power_in Analog ground pin that must always be connected to the external power supply within the permitted range.
13 VDDA power_in Analog supply: 1.62 V to 3.6 V when the ADC is used, 1.8 V minimum when the DAC is used and 2.1 V minimum when VREFBUF is used.
14 PA0 bidirectional 5 V-tolerant GPIO (FT_at) with analog-switch function supplied by VDDA, ADC12_INP0/ADC12_INN1 inputs, WKUP1 and a tamper input (TAMP_IN2) functional in Standby and VBAT mode.
15 PA1 bidirectional 5 V-tolerant GPIO (FT_aht) with analog-switch function supplied by VDDA, high-speed low-voltage capability, ADC12_INP1 input and TAMP_OUT4 tamper output functional in Standby and VBAT mode.
16 PA2 bidirectional 5 V-tolerant GPIO (FT_at) with analog-switch function supplied by VDDA, ADC12_INP14 input, WKUP2 and TAMP_IN4/TAMP_OUT3 tamper functions.
17 PA3 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA and ADC12_INP15 analog input.
18 VSS power_in Ground reference pin; all voltages are referenced to VSS.
19 VDD power_in Main supply: 1.71 V to 3.6 V with HSLV = 0, or 1.71 V to 2.7 V with HSLV = 1.
20 PA4 bidirectional 3.6 V-tolerant GPIO (TT_a) with analog-switch function supplied by VDDA, ADC12_INP18 input and DAC1_OUT1 output.
21 PA5 bidirectional 3.6 V-tolerant GPIO (TT_ah) with analog-switch function supplied by VDDA, ADC12_INP19/ADC12_INN18 inputs and DAC1_OUT2 output.
22 PA6 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA and ADC12_INP3 analog input.
23 PA7 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA and ADC12_INP7/ADC12_INN3 analog inputs.
24 PC4 bidirectional 5 V-tolerant GPIO (FT_a) with analog-switch function supplied by VDDA and ADC12_INP4 analog input.
25 PC5 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA and ADC12_INP8/ADC12_INN4 analog inputs.
26 PB0 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA and ADC12_INP9/ADC12_INN5 analog inputs.
27 PB1 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA and ADC12_INP5 analog input.
28 PB2 bidirectional 5 V-tolerant GPIO (FT_ah) with analog-switch function supplied by VDDA; LSCO is an additional function.
29 PB10 bidirectional 5 V-tolerant Fm+-capable GPIO (FT_f) with alternate functions including I2C2_SCL, SPI2_SCK and USART3_TX.
30 VCAP power_in VCORE regulator connection; when the internal regulator is OFF, VCORE must be supplied from an external regulator on the VCAP pins.
31 VSS power_in Ground reference pin; all voltages are referenced to VSS.
32 VDD power_in Main supply: 1.71 V to 3.6 V with HSLV = 0, or 1.71 V to 2.7 V with HSLV = 1.
33 PB12 bidirectional 5 V-tolerant GPIO (FT_h) with high-speed low-voltage mode capability and alternate functions including TIM1_BKIN and I2C2_SDA.
34 PB13 bidirectional 5 V-tolerant USB Type-C/PD I/O (FT_c) with UCPD1_CC1 function and input range -0.3 V to 5.0 V.
35 PB14 bidirectional 5 V-tolerant USB Type-C/PD I/O (FT_c) with UCPD1_CC2 function and input range -0.3 V to 5.0 V.
36 PB15 bidirectional 5 V-tolerant GPIO (FT_h) with PVD_IN additional function and alternate functions including RTC_REFIN and TIM1_CH3N.
37 PC6 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including TIM3_CH1, FMC_NWAIT and DCMI_D0/PSSI_D0.
38 PC7 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including TIM3_CH2, FMC_NE1 and DCMI_D1/PSSI_D1.
39 PC8 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including TIM3_CH3, FMC_NE2/FMC_NCE and DCMI_D2/PSSI_D2.
40 PC9 bidirectional 5 V-tolerant Fm+-capable GPIO (FT_fh) with alternate functions including MCO2, I2C3_SDA and AUDIOCLK, and UCPD1_DB2 additional function.
41 PA8 bidirectional 5 V-tolerant Fm+-capable GPIO (FT_fh) with alternate functions including MCO1, I2C3_SCL, USB_SOF and TIM1_CH1.
42 PA9 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including TIM1_CH2, LPUART1_TX and USART1_TX, and UCPD1_DB1 additional function.
43 PA10 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including TIM1_CH3, LPUART1_RX, USART1_RX and UCPD1_FRSTX.
44 PA11 bidirectional 5 V-tolerant I/O (FT_u) with USB function (USB_DM) supplied by VDDUSB, plus TIM1_CH4 and USART1_CTS alternate functions.
45 PA12 bidirectional 5 V-tolerant I/O (FT_u) with USB function (USB_DP) supplied by VDDUSB, plus TIM1_ETR and USART1_RTS alternate functions.
46 PA13 bidirectional 5 V-tolerant I/O (FT) that is configured as JTMS/SWDIO after reset, with the internal pull-up activated.
47 VSS power_in Ground reference pin; all voltages are referenced to VSS.
48 VDD power_in Main supply: 1.71 V to 3.6 V with HSLV = 0, or 1.71 V to 2.7 V with HSLV = 1.
49 PA14 bidirectional 5 V-tolerant I/O (FT) that is configured as JTCK/SWCLK after reset, with the internal pull-down activated.
50 PA15 bidirectional 5 V-tolerant I/O (FT) that is configured as JTDI after reset, with the internal pull-up activated; also TIM2_CH1 and DCMI_D11/PSSI_D11 alternate functions.
51 PC10 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including I3C2_SCL, USART3_TX and DCMI_D8/PSSI_D8.
52 PC11 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including I3C2_SDA, USART3_RX and SDMMC1_D3.
53 PC12 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including TRACED3, TIM15_CH1 and USART3_CK.
54 PD2 bidirectional 5 V-tolerant GPIO (FT_h) with WKUP7 wake-up function and alternate functions including TRACED2 and SDMMC1_CMD.
55 PB3 bidirectional 5 V-tolerant GPIO (FT_h) with JTDO/TRACESWO function and alternate functions including TIM2_CH2 and LPUART1_TX.
56 PB4 bidirectional 5 V-tolerant GPIO (FT_h) that is configured as NJTRST after reset, with the internal pull-up activated; also TIM3_CH1 and OCTOSPI1_CLK alternate functions.
57 PB5 bidirectional 5 V-tolerant GPIO (FT_h) with alternate functions including TIM3_CH2, I2C1_SMBA and USART6_TX.
58 PB6 bidirectional 5 V-tolerant Fm+-capable GPIO (FT_f) with alternate functions including I3C1_SCL, I2C1_SCL and USART6_RX.
59 PB7 bidirectional 5 V-tolerant Fm+-capable GPIO (FT_fa) with analog-switch function supplied by VDDA, WKUP5 wake-up function and I2C1_SDA alternate function.
60 BOOT0 input Boot input whose voltage must stay between VSS and min(min(VDD, VDDA, VDDUSB, VDDIO2) + 4.0 V, 6.0 V), per Table 16.
61 PB8 bidirectional 5 V-tolerant I/O (FT_fsh) with high-speed low-voltage and Fm+ capability, supplied only by VDDIO2 (_s).
62 VCAP power_in VCORE regulator connection; when the internal regulator is OFF, VCORE must be supplied from an external regulator on the VCAP pins.
63 VSS power_in Ground reference pin; all voltages are referenced to VSS.
64 VDD power_in Main supply: 1.71 V to 3.6 V with HSLV = 0, or 1.71 V to 2.7 V with HSLV = 1.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (VDDA, VDDUSB, VDDIO2, VBAT, VREF+) VDDx - VSS -0.3 4 V 95
I/O supply voltage, HSLV = 0 VDDIOx - VSS -0.3 4 V HSLV = 0 95
I/O supply voltage, HSLV = 1 VDDIOx - VSS -0.3 2.75 V HSLV = 1 95
Input voltage on FT_xxx pins except FT_c VIN -0.3 V Referenced to VSS; max is formula min(min(VDD,VDDA,VDDUSB,VDDIO2)+4.0, 6.0 V) 95
Input voltage on FT_t in VBAT mode VIN -0.3 V Referenced to VSS; max is formula min(min(VBAT,VDDA,VDDUSB,VDDIO2)+4.0 V, 6.0 V) 95
Input voltage on TT_xx pins VIN -0.3 4 V Referenced to VSS 95
Input voltage on FT_c pins VIN -0.3 5.5 V 95
Input voltage on any other pins VIN -0.3 4 V 95
Allowed voltage difference for VREF+ > VDDA VREF+-VDDA 0.4 V 95
Variations between different VDDX power pins of the same domain /ΔVDDx/ 50 mV 95
Variations between all the different ground pins /VSSx-VSS/ 50 mV 95
Total current into sum of all VDD power lines (source) ΣIVDD 350 mA 96
Total current out of sum of all VSS ground lines (sink) ΣIVSS 350 mA 96
Maximum current into each VDD power pin (source) IVDD 100 mA 96
Maximum current out of each VSS ground pin (sink) IVSS 100 mA 96
Output current sunk/sourced by any I/O and control pin IIO(PIN) 20 mA 96
Total output current sunk by sum of all I/Os and control pins ΣIIO(PIN) 140 mA 96
Total output current sourced by sum of all I/Os and control pins ΣIIO(PIN) 140 mA 96
Injected current on FT_xxx, TT_xx, NRST pins IINJ(PIN) -5 0 mA 96
Total injected current (sum of all I/Os and control pins) ∑/IINJ(PIN)/ -25 25 mA Printed ±25 96
Storage temperature range TSTG -65 150 °C 96
Maximum junction temperature TJ 130 °C Limited to 105 °C in VOS0 voltage range 96
Standard operating voltage VDD 1.71 3.6 V HSLV = 0 96
Standard operating voltage VDD 1.71 2.7 V HSLV = 1 96
I/O supply voltage, at least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used VDDIO2 1.08 3.6 V HSLV = 0 96
I/O supply voltage, at least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used VDDIO2 1.08 2.7 V HSLV = 1 96
I/O supply voltage, PB8, PB9, PD6, PD7, PG[9:14] not used VDDIO2 0 3.6 V 96
USB supply voltage, USB used VDDUSB 3 3.6 V USB is used 97
USB supply voltage, USB not used VDDUSB 0 3.6 V USB is not used 97
Analog supply voltage, ADC used VDDA 1.62 3.6 V ADC is used 97
Analog supply voltage, DAC used VDDA 1.8 V DAC is used 97
Analog supply voltage, VREFBUF used VDDA 2.1 V VREFBUF is used 97
Analog supply voltage, ADC, DAC and VREFBUF not used VDDA 0 V ADC, DAC, and VREFBUF are not used 97
Backup domain supply voltage VBAT 1.2 3.6 V 97
I/O input voltage, all I/Os except FT_c and TT_xx VIN -0.3 V Max is formula min(min(VDD,VDDA,VDDUSB,VDDIO2)+3.6 V, 5.5 V) 97
Input voltage on FT_t in VBAT mode VIN -0.3 V Max is formula min(min(VBAT,VDDA,VDDUSB,VDDIO2)+3.6 V, 5.5 V) 97
FT_c I/O input voltage VIN -0.3 5 V 97
TT_xx I/O input voltage VIN -0.3 V Max is VDDIOx + 0.3 V 97
Internal regulator ON, VOS0 VCORE 1.3 1.35 1.4 V Max frequency for AHB and APB 250 MHz 97
Internal regulator ON, VOS1 VCORE 1.15 1.2 1.26 V Max frequency for AHB and APB 200 MHz 97
Internal regulator ON, VOS2 VCORE 1.05 1.1 1.15 V Max frequency for AHB and APB 150 MHz 97
Internal regulator ON, VOS3 VCORE 0.95 1 1.05 V Max frequency for AHB and APB 100 MHz 97
Regulator OFF, external VCORE on VCAP pins, VOS0 VCORE 1.32 1.35 1.4 V Regulator OFF 97
Regulator OFF, external VCORE on VCAP pins, VOS1 VCORE 1.17 1.2 1.26 V Regulator OFF 97
Regulator OFF, external VCORE on VCAP pins, VOS2 VCORE 1.07 1.1 1.15 V Regulator OFF 97
Regulator OFF, external VCORE on VCAP pins, VOS3 VCORE 0.97 1 1.05 V Regulator OFF 97
AHB clock frequency, VOS0 fHCLK 250 MHz VOS0 98
AHB clock frequency, VOS1 fHCLK 200 MHz VOS1 98
AHB clock frequency, VOS2 fHCLK 150 MHz VOS2 98
AHB clock frequency, VOS3 fHCLK 100 MHz VOS3 98
Ambient temperature, suffix 6 version TA -40 85 °C Maximum power dissipation 98
Junction temperature range, VOS0 TJ -40 105 °C VOS0 98
Junction temperature range, VOS1, VOS2, VOS3 TJ -40 130 °C VOS1, VOS2, and VOS3 98
Power-on/down reset threshold, rising edge VPOR/PDR 1.62 1.67 1.71 V BORH_EN = 0, rising edge 101
Power-on/down reset threshold, falling edge VPOR/PDR 1.58 1.62 1.68 V BORH_EN = 0, falling edge 101
Internal reference voltage VREFINT 1.18 1.216 1.255 V -40 °C < TJ < +130 °C 102
Average temperature coefficient (VREFINT) TCoeff 20 70 ppm/°C 102
Average voltage coefficient (VREFINT) VDDcoeff 10 1370 ppm/V 3.0 V < VDD < 3.6 V 102
Internal reference voltage spread over temperature range ∆VREFINT 5 15 mV -40 °C < TJ < +130 °C 102

CAD (KiCad official)

  • Symbol: STM32H523RET6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32h523ret6-etched.step / stm32h523ret6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32h523ret6.step / stm32h523ret6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (226 pp, sha256 196eff2d8315b480, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF