STM32H523RCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32H523RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup domain supply for RTC and backup registers, 1.2 V to 3.6 V.
2	PC13	bidirectional	FT_t I/O supplied via the VSW power switch, output speed limited to 2 MHz with max 30 pF load and not usable as a current source; additional functions TAMP_IN1/TAMP_OUT2/TAMP_OUT3, RTC_OUT1/RTC_TS, WKUP4.
3	PC14-OSC32_IN	bidirectional	FT I/O supplied via the VSW power switch (2 MHz, 30 pF output limit) that also serves as the 32.768 kHz LSE oscillator input OSC32_IN.
4	PC15-OSC32_OUT	bidirectional	FT I/O supplied via the VSW power switch (2 MHz, 30 pF output limit) that also serves as the 32.768 kHz LSE oscillator output OSC32_OUT.
5	PH0-OSC_IN	bidirectional	FT I/O (PH0) that also serves as the 4-50 MHz HSE oscillator input OSC_IN.
6	PH1-OSC_OUT	bidirectional	FT I/O (PH1) that also serves as the 4-50 MHz HSE oscillator output OSC_OUT.
7	NRST	bidirectional	Bidirectional reset pin (RST structure) with embedded weak pull-up resistor.
8	PC0	bidirectional	FT_a I/O with SPI4_MISO, SPI2_RDY, FMC_A25, OCTOSPI1_IO7 alternate functions and ADC12_INP10 analog input.
9	PC1	bidirectional	FT_ah I/O with TRACED0, SPI2_MOSI/I2S2_SDO, SPI4_MOSI, OCTOSPI1_IO4 alternates; ADC12_INP11, ADC12_INN10, TAMP_IN3/TAMP_OUT5, WKUP6.
10	PC2	bidirectional	FT_a I/O with PWR_CSLEEP, TIM4_CH4, SPI2_MISO/I2S2_SDI, OCTOSPI1_IO5/IO2 alternates; ADC12_INP12, ADC12_INN11.
11	PC3	bidirectional	FT_a I/O with PWR_CSTOP, LPUART1_TX, SPI2_MOSI/I2S2_SDO, OCTOSPI1_IO6/IO0 alternates; ADC12_INP13, ADC12_INN12.
12	VSSA	power_in	Analog ground (VSSA/VREF- on the LQFP64 pinout); must always be connected to the external supply ground.
13	VDDA	power_in	Analog supply (VDDA/VREF+ on the LQFP64 pinout): 1.62 V min when ADC used, 1.8 V min with DAC, 2.1 V min with VREFBUF, max 3.6 V.
14	PA0	bidirectional	FT_at I/O with TIM2_CH1, TIM5_CH1, USART2_CTS, UART4_TX, FDCAN2_RX alternates; ADC12_INP0, TAMP_IN2/TAMP_OUT1, WKUP1; tamper input functional in Standby and VBAT mode.
15	PA1	bidirectional	FT_aht I/O with TIM2_CH2, TIM5_CH2, OCTOSPI1_DQS, USART2_RTS/DE, UART4_RX alternates; ADC12_INP1, TAMP_IN5/TAMP_OUT4; tamper functional in Standby and VBAT mode.
16	PA2	bidirectional	FT_at I/O with TIM2_CH3, TIM5_CH3, LPUART1_TX, USART2_TX alternates; ADC12_INP14, TAMP_IN4/TAMP_OUT3, WKUP2.
17	PA3	bidirectional	FT_ah I/O with TIM2_CH4, TIM5_CH4, OCTOSPI1_CLK, SPI2_NSS/I2S2_WS, USART2_RX alternates; ADC12_INP15.
18	VSS	power_in	Digital ground pin; all VSS pins must be connected to ground.
19	VDD	power_in	Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor.
20	PA4	bidirectional	TT_a I/O (3.6 V tolerant) with TIM5_ETR, LPTIM2_CH1, SPI1_NSS/I2S1_WS, SPI3_NSS, USART2_CK alternates; ADC12_INP18, DAC1_OUT1.
21	PA5	bidirectional	TT_ah I/O (3.6 V tolerant) with TIM2_CH1, TIM8_CH1N, SPI1_SCK/I2S1_CK alternates; ADC12_INP19, ADC12_INN18, DAC1_OUT2.
22	PA6	bidirectional	FT_ah I/O with TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, OCTOSPI1_IO3 alternates; ADC12_INP3.
23	PA7	bidirectional	FT_ah I/O with TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, OCTOSPI1_IO2, FMC_NWE alternates; ADC12_INP7, ADC12_INN3.
24	PC4	bidirectional	FT_a I/O with TIM2_CH4, LPTIM2_ETR, I2S1_MCK, USART3_RX alternates; ADC12_INP4.
25	PC5	bidirectional	FT_ah I/O with TIM1_CH4N, PSSI_D15, SPI4_SCK, OCTOSPI1_DQS alternates; ADC12_INP8, ADC12_INN4.
26	PB0	bidirectional	FT_ah I/O with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MISO/I2S3_SDI, OCTOSPI1_IO1, USART2_TX, UART4_CTS alternates; ADC12_INP9, ADC12_INN5.
27	PB1	bidirectional	FT_ah I/O with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI3_SCK, SPI2_NSS/I2S2_WS, OCTOSPI1_IO0, USART3_RX alternates; ADC12_INP5.
28	PB2	bidirectional	FT_ah I/O with RTC_OUT2, TIM8_CH4N, SPI1_RDY, LPTIM1_CH1, SPI2_SCK, OCTOSPI1_CLK/DQS, SDMMC1_CMD alternates; additional function LSCO.
29	PB10	bidirectional	FT_f (Fm+ capable) I/O with TIM2_CH3, TIM8_CH1, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OCTOSPI1_NCS alternates.
30	VCAP	passive	Core voltage (VCORE) regulator external capacitor pin; with regulator off, external VCORE of 0.97 V to 1.40 V depending on VOS range is supplied here.
31	VSS	power_in	Digital ground pin; all VSS pins must be connected to ground.
32	VDD	power_in	Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor.
33	PB12	bidirectional	FT_h I/O with TIM1_BKIN, TIM8_CH3, OCTOSPI1_NCLK, I2C2_SDA, SPI2_NSS/I2S2_WS, UCPD1_FRSTX, USART3_CK, FDCAN2_RX, UART5_RX alternates.
34	PB13	bidirectional	FT_c I/O (5.0 V max input) with TIM1_CH1N, TIM8_CH2, LPTIM2_CH1, I2C2_SMBA, SPI2_SCK, USART3_CTS, LPUART1_RX, FDCAN2_TX, SDMMC1_D0, UART5_TX alternates; UCPD1_CC1.
35	PB14	bidirectional	FT_c I/O (5.0 V max input) with TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO, USART3_RTS/DE, UART4_RTS/DE alternates; UCPD1_CC2.
36	PB15	bidirectional	FT_h I/O with RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI, SPI1_MOSI, UART4_CTS, OCTOSPI1_CLK, UART5_RX alternates; PVD_IN.
37	PC6	bidirectional	FT_h I/O with TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, I3C2_SCL, OCTOSPI1_IO5, SDMMC1_D6, DCMI_D0/PSSI_D0 alternates.
38	PC7	bidirectional	FT_h I/O with TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, I3C2_SDA, OCTOSPI1_IO6, SDMMC1_D7, DCMI_D1/PSSI_D1 alternates.
39	PC8	bidirectional	FT_h I/O with TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/DE, FMC_NE2/NCE, FMC_INT, FMC_ALE, SDMMC1_D0, DCMI_D2/PSSI_D2 alternates.
40	PC9	bidirectional	FT_fh I/O with MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK, UART5_CTS, OCTOSPI1_IO0, FMC_CLE, SDMMC1_D1, DCMI_D3/PSSI_D3 alternates; UCPD1_DB2.
41	PA8	bidirectional	FT_fh I/O with MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, SPI1_RDY, SPI4_MOSI, USART1_CK, I3C2_SCL, USB_SOF, FMC_NOE, DCMI_D3/PSSI_D3 alternates.
42	PA9	bidirectional	FT_h I/O with TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, FMC_NWE, DCMI_D0/PSSI_D0 alternates; UCPD1_DB1.
43	PA10	bidirectional	FT_h I/O with TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX, FDCAN2_TX, SDMMC1_D0, DCMI_D1/PSSI_D1 alternates.
44	PA11	bidirectional	FT_u I/O supplied by VDDUSB with TIM1_CH4, LPUART1_CTS, SPI2_NSS, UART4_RX, USART1_CTS, FDCAN1_RX alternates and USB_DM function.
45	PA12	bidirectional	FT_u I/O supplied by VDDUSB with TIM1_ETR, LPUART1_RTS/DE, SPI2_SCK, UART4_TX, USART1_RTS/DE, FDCAN1_TX alternates and USB_DP function.
46	PA13(JTMS/SWDIO)	bidirectional	FT I/O configured after reset as JTMS/SWDIO debug function with internal pull-up active.
47	VSS	power_in	Digital ground pin; all VSS pins must be connected to ground.
48	VDD	power_in	Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor.
49	PA14(JTCK/SWCLK)	bidirectional	FT I/O configured after reset as JTCK/SWCLK debug function with internal pull-down active.
50	PA15 (JTDI)	bidirectional	FT I/O configured after reset as JTDI with internal pull-up active; alternates include TIM2_CH1, HDMI_CEC, SPI1_NSS, SPI3_NSS, USART1_TX, UART4_RTS/DE, OCTOSPI1_NCS, FMC_NBL1.
51	PC10	bidirectional	FT_h I/O with I3C2_SCL, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1, SDMMC1_D2, DCMI_D8/PSSI_D8 alternates.
52	PC11	bidirectional	FT_h I/O with I3C2_SDA, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS, SDMMC1_D3, DCMI_D4/PSSI_D4 alternates.
53	PC12	bidirectional	FT_h I/O with TRACED3, TIM15_CH1, LPTIM2_CH2, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9 alternates.
54	PD2	bidirectional	FT_h I/O with TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD, DCMI_D11/PSSI_D11 alternates; WKUP7.
55	PB3(JTDO/TRACESWO)	bidirectional	FT_h I/O configured after reset as JTDO/TRACESWO; alternates include TIM2_CH2, I3C2_SCL, I2C2_SDA, SPI1_SCK, SPI3_SCK, LPUART1_TX, FDCAN2_TX, CRS_SYNC, UART5_TX.
56	PB4 (NJTRST)	bidirectional	FT_h I/O configured after reset as NJTRST with internal pull-up active; alternates include TIM3_CH1, OCTOSPI1_CLK, LPTIM1_CH2, SPI1_MISO, SPI3_MISO, I2C3_SDA, I3C2_SDA.
57	PB5	bidirectional	FT_h I/O with TIM3_CH2, OCTOSPI1_NCLK, I2C1_SMBA, SPI1_MOSI, USART6_TX, SPI3_MOSI, FDCAN2_RX, I3C2_SCL, UART5_RX alternates.
58	PB6	bidirectional	FT_f (Fm+ capable) I/O with TIM4_CH1, I3C1_SCL, I2C1_SCL, HDMI_CEC, USART6_RX, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPI1_NCS, UART5_TX alternates.
59	PB7	bidirectional	FT_fa (Fm+ capable) I/O with TIM4_CH2, I3C1_SDA, I2C1_SDA, SPI4_MISO, USART6_CTS, USART1_RX, LPUART1_RX, FDCAN1_TX, FMC_NL alternates; WKUP5.
60	BOOT0	input	Boot mode selection input (B structure); input voltage up to min(min(VDD, VDDA, VDDUSB, VDDIO2) + 3.6 V, 5.5 V) per operating conditions.
61	PB8	bidirectional	FT_fsh (Fm+ capable) I/O supplied by VDDIO2 with TIM4_CH3, I3C1_SCL, I2C1_SCL, SPI4_RDY, SPI3_NSS, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC1_D4 alternates.
62	VCAP	passive	Core voltage (VCORE) regulator external capacitor pin; with regulator off, external VCORE of 0.97 V to 1.40 V depending on VOS range is supplied here.
63	VSS	power_in	Digital ground pin; all VSS pins must be connected to ground.
64	VDD	power_in	Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

CAD (KiCad official)

Symbol: STM32H523RCT6
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: stm32h523rct6-etched.step / stm32h523rct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32h523rct6.step / stm32h523rct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (226 pp, sha256 196eff2d8315b480, retrieved 2026-10-01, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# STM32H523RCT6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32H523RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup domain supply for RTC and backup registers, 1.2 V to 3.6 V. |
| 2 | PC13 | bidirectional | FT_t I/O supplied via the VSW power switch, output speed limited to 2 MHz with max 30 pF load and not usable as a current source; additional functions TAMP_IN1/TAMP_OUT2/TAMP_OUT3, RTC_OUT1/RTC_TS, WKUP4. |
| 3 | PC14-OSC32_IN | bidirectional | FT I/O supplied via the VSW power switch (2 MHz, 30 pF output limit) that also serves as the 32.768 kHz LSE oscillator input OSC32_IN. |
| 4 | PC15-OSC32_OUT | bidirectional | FT I/O supplied via the VSW power switch (2 MHz, 30 pF output limit) that also serves as the 32.768 kHz LSE oscillator output OSC32_OUT. |
| 5 | PH0-OSC_IN | bidirectional | FT I/O (PH0) that also serves as the 4-50 MHz HSE oscillator input OSC_IN. |
| 6 | PH1-OSC_OUT | bidirectional | FT I/O (PH1) that also serves as the 4-50 MHz HSE oscillator output OSC_OUT. |
| 7 | NRST | bidirectional | Bidirectional reset pin (RST structure) with embedded weak pull-up resistor. |
| 8 | PC0 | bidirectional | FT_a I/O with SPI4_MISO, SPI2_RDY, FMC_A25, OCTOSPI1_IO7 alternate functions and ADC12_INP10 analog input. |
| 9 | PC1 | bidirectional | FT_ah I/O with TRACED0, SPI2_MOSI/I2S2_SDO, SPI4_MOSI, OCTOSPI1_IO4 alternates; ADC12_INP11, ADC12_INN10, TAMP_IN3/TAMP_OUT5, WKUP6. |
| 10 | PC2 | bidirectional | FT_a I/O with PWR_CSLEEP, TIM4_CH4, SPI2_MISO/I2S2_SDI, OCTOSPI1_IO5/IO2 alternates; ADC12_INP12, ADC12_INN11. |
| 11 | PC3 | bidirectional | FT_a I/O with PWR_CSTOP, LPUART1_TX, SPI2_MOSI/I2S2_SDO, OCTOSPI1_IO6/IO0 alternates; ADC12_INP13, ADC12_INN12. |
| 12 | VSSA | power_in | Analog ground (VSSA/VREF- on the LQFP64 pinout); must always be connected to the external supply ground. |
| 13 | VDDA | power_in | Analog supply (VDDA/VREF+ on the LQFP64 pinout): 1.62 V min when ADC used, 1.8 V min with DAC, 2.1 V min with VREFBUF, max 3.6 V. |
| 14 | PA0 | bidirectional | FT_at I/O with TIM2_CH1, TIM5_CH1, USART2_CTS, UART4_TX, FDCAN2_RX alternates; ADC12_INP0, TAMP_IN2/TAMP_OUT1, WKUP1; tamper input functional in Standby and VBAT mode. |
| 15 | PA1 | bidirectional | FT_aht I/O with TIM2_CH2, TIM5_CH2, OCTOSPI1_DQS, USART2_RTS/DE, UART4_RX alternates; ADC12_INP1, TAMP_IN5/TAMP_OUT4; tamper functional in Standby and VBAT mode. |
| 16 | PA2 | bidirectional | FT_at I/O with TIM2_CH3, TIM5_CH3, LPUART1_TX, USART2_TX alternates; ADC12_INP14, TAMP_IN4/TAMP_OUT3, WKUP2. |
| 17 | PA3 | bidirectional | FT_ah I/O with TIM2_CH4, TIM5_CH4, OCTOSPI1_CLK, SPI2_NSS/I2S2_WS, USART2_RX alternates; ADC12_INP15. |
| 18 | VSS | power_in | Digital ground pin; all VSS pins must be connected to ground. |
| 19 | VDD | power_in | Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor. |
| 20 | PA4 | bidirectional | TT_a I/O (3.6 V tolerant) with TIM5_ETR, LPTIM2_CH1, SPI1_NSS/I2S1_WS, SPI3_NSS, USART2_CK alternates; ADC12_INP18, DAC1_OUT1. |
| 21 | PA5 | bidirectional | TT_ah I/O (3.6 V tolerant) with TIM2_CH1, TIM8_CH1N, SPI1_SCK/I2S1_CK alternates; ADC12_INP19, ADC12_INN18, DAC1_OUT2. |
| 22 | PA6 | bidirectional | FT_ah I/O with TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, OCTOSPI1_IO3 alternates; ADC12_INP3. |
| 23 | PA7 | bidirectional | FT_ah I/O with TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, OCTOSPI1_IO2, FMC_NWE alternates; ADC12_INP7, ADC12_INN3. |
| 24 | PC4 | bidirectional | FT_a I/O with TIM2_CH4, LPTIM2_ETR, I2S1_MCK, USART3_RX alternates; ADC12_INP4. |
| 25 | PC5 | bidirectional | FT_ah I/O with TIM1_CH4N, PSSI_D15, SPI4_SCK, OCTOSPI1_DQS alternates; ADC12_INP8, ADC12_INN4. |
| 26 | PB0 | bidirectional | FT_ah I/O with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI3_MISO/I2S3_SDI, OCTOSPI1_IO1, USART2_TX, UART4_CTS alternates; ADC12_INP9, ADC12_INN5. |
| 27 | PB1 | bidirectional | FT_ah I/O with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI3_SCK, SPI2_NSS/I2S2_WS, OCTOSPI1_IO0, USART3_RX alternates; ADC12_INP5. |
| 28 | PB2 | bidirectional | FT_ah I/O with RTC_OUT2, TIM8_CH4N, SPI1_RDY, LPTIM1_CH1, SPI2_SCK, OCTOSPI1_CLK/DQS, SDMMC1_CMD alternates; additional function LSCO. |
| 29 | PB10 | bidirectional | FT_f (Fm+ capable) I/O with TIM2_CH3, TIM8_CH1, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OCTOSPI1_NCS alternates. |
| 30 | VCAP | passive | Core voltage (VCORE) regulator external capacitor pin; with regulator off, external VCORE of 0.97 V to 1.40 V depending on VOS range is supplied here. |
| 31 | VSS | power_in | Digital ground pin; all VSS pins must be connected to ground. |
| 32 | VDD | power_in | Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor. |
| 33 | PB12 | bidirectional | FT_h I/O with TIM1_BKIN, TIM8_CH3, OCTOSPI1_NCLK, I2C2_SDA, SPI2_NSS/I2S2_WS, UCPD1_FRSTX, USART3_CK, FDCAN2_RX, UART5_RX alternates. |
| 34 | PB13 | bidirectional | FT_c I/O (5.0 V max input) with TIM1_CH1N, TIM8_CH2, LPTIM2_CH1, I2C2_SMBA, SPI2_SCK, USART3_CTS, LPUART1_RX, FDCAN2_TX, SDMMC1_D0, UART5_TX alternates; UCPD1_CC1. |
| 35 | PB14 | bidirectional | FT_c I/O (5.0 V max input) with TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO, USART3_RTS/DE, UART4_RTS/DE alternates; UCPD1_CC2. |
| 36 | PB15 | bidirectional | FT_h I/O with RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI, SPI1_MOSI, UART4_CTS, OCTOSPI1_CLK, UART5_RX alternates; PVD_IN. |
| 37 | PC6 | bidirectional | FT_h I/O with TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, I3C2_SCL, OCTOSPI1_IO5, SDMMC1_D6, DCMI_D0/PSSI_D0 alternates. |
| 38 | PC7 | bidirectional | FT_h I/O with TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, I3C2_SDA, OCTOSPI1_IO6, SDMMC1_D7, DCMI_D1/PSSI_D1 alternates. |
| 39 | PC8 | bidirectional | FT_h I/O with TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/DE, FMC_NE2/NCE, FMC_INT, FMC_ALE, SDMMC1_D0, DCMI_D2/PSSI_D2 alternates. |
| 40 | PC9 | bidirectional | FT_fh I/O with MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK, UART5_CTS, OCTOSPI1_IO0, FMC_CLE, SDMMC1_D1, DCMI_D3/PSSI_D3 alternates; UCPD1_DB2. |
| 41 | PA8 | bidirectional | FT_fh I/O with MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, SPI1_RDY, SPI4_MOSI, USART1_CK, I3C2_SCL, USB_SOF, FMC_NOE, DCMI_D3/PSSI_D3 alternates. |
| 42 | PA9 | bidirectional | FT_h I/O with TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, FMC_NWE, DCMI_D0/PSSI_D0 alternates; UCPD1_DB1. |
| 43 | PA10 | bidirectional | FT_h I/O with TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX, FDCAN2_TX, SDMMC1_D0, DCMI_D1/PSSI_D1 alternates. |
| 44 | PA11 | bidirectional | FT_u I/O supplied by VDDUSB with TIM1_CH4, LPUART1_CTS, SPI2_NSS, UART4_RX, USART1_CTS, FDCAN1_RX alternates and USB_DM function. |
| 45 | PA12 | bidirectional | FT_u I/O supplied by VDDUSB with TIM1_ETR, LPUART1_RTS/DE, SPI2_SCK, UART4_TX, USART1_RTS/DE, FDCAN1_TX alternates and USB_DP function. |
| 46 | PA13(JTMS/SWDIO) | bidirectional | FT I/O configured after reset as JTMS/SWDIO debug function with internal pull-up active. |
| 47 | VSS | power_in | Digital ground pin; all VSS pins must be connected to ground. |
| 48 | VDD | power_in | Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor. |
| 49 | PA14(JTCK/SWCLK) | bidirectional | FT I/O configured after reset as JTCK/SWCLK debug function with internal pull-down active. |
| 50 | PA15 (JTDI) | bidirectional | FT I/O configured after reset as JTDI with internal pull-up active; alternates include TIM2_CH1, HDMI_CEC, SPI1_NSS, SPI3_NSS, USART1_TX, UART4_RTS/DE, OCTOSPI1_NCS, FMC_NBL1. |
| 51 | PC10 | bidirectional | FT_h I/O with I3C2_SCL, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1, SDMMC1_D2, DCMI_D8/PSSI_D8 alternates. |
| 52 | PC11 | bidirectional | FT_h I/O with I3C2_SDA, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS, SDMMC1_D3, DCMI_D4/PSSI_D4 alternates. |
| 53 | PC12 | bidirectional | FT_h I/O with TRACED3, TIM15_CH1, LPTIM2_CH2, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9 alternates. |
| 54 | PD2 | bidirectional | FT_h I/O with TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD, DCMI_D11/PSSI_D11 alternates; WKUP7. |
| 55 | PB3(JTDO/TRACESWO) | bidirectional | FT_h I/O configured after reset as JTDO/TRACESWO; alternates include TIM2_CH2, I3C2_SCL, I2C2_SDA, SPI1_SCK, SPI3_SCK, LPUART1_TX, FDCAN2_TX, CRS_SYNC, UART5_TX. |
| 56 | PB4 (NJTRST) | bidirectional | FT_h I/O configured after reset as NJTRST with internal pull-up active; alternates include TIM3_CH1, OCTOSPI1_CLK, LPTIM1_CH2, SPI1_MISO, SPI3_MISO, I2C3_SDA, I3C2_SDA. |
| 57 | PB5 | bidirectional | FT_h I/O with TIM3_CH2, OCTOSPI1_NCLK, I2C1_SMBA, SPI1_MOSI, USART6_TX, SPI3_MOSI, FDCAN2_RX, I3C2_SCL, UART5_RX alternates. |
| 58 | PB6 | bidirectional | FT_f (Fm+ capable) I/O with TIM4_CH1, I3C1_SCL, I2C1_SCL, HDMI_CEC, USART6_RX, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPI1_NCS, UART5_TX alternates. |
| 59 | PB7 | bidirectional | FT_fa (Fm+ capable) I/O with TIM4_CH2, I3C1_SDA, I2C1_SDA, SPI4_MISO, USART6_CTS, USART1_RX, LPUART1_RX, FDCAN1_TX, FMC_NL alternates; WKUP5. |
| 60 | BOOT0 | input | Boot mode selection input (B structure); input voltage up to min(min(VDD, VDDA, VDDUSB, VDDIO2) + 3.6 V, 5.5 V) per operating conditions. |
| 61 | PB8 | bidirectional | FT_fsh (Fm+ capable) I/O supplied by VDDIO2 with TIM4_CH3, I3C1_SCL, I2C1_SCL, SPI4_RDY, SPI3_NSS, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC1_D4 alternates. |
| 62 | VCAP | passive | Core voltage (VCORE) regulator external capacitor pin; with regulator off, external VCORE of 0.97 V to 1.40 V depending on VOS range is supplied here. |
| 63 | VSS | power_in | Digital ground pin; all VSS pins must be connected to ground. |
| 64 | VDD | power_in | Digital supply, 1.71 V to 3.6 V (HSLV=0) or 1.71 V to 2.7 V (HSLV=1); must be decoupled with 100 nF ceramic capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `STM32H523RCT6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm32h523rct6-etched.step` / `stm32h523rct6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32h523rct6.step` / `stm32h523rct6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm32h523rct6.pdf) (226 pp, sha256 `196eff2d8315b480`, retrieved 2026-10-01, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32h523rct6-datasheet.pdf)