STM32H503CBT6

STMICROELECTRONICS · Global Sourcing Parts · LQFP-48(7x7)

STM32H503CBT6 from STMICROELECTRONICS, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup-domain supply for the RTC and backup registers, with a backup operating voltage of 1.2 V to 3.6 V.
2	PC13	bidirectional	5 V-tolerant (FT_t) GPIO powered through the VSW power switch and functional in VBAT mode with tamper function; output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source.
3	PC14-OSC32_IN	bidirectional	5 V-tolerant GPIO powered through the VSW power switch, limited to 2 MHz output speed at 30 pF with no current sourcing; also the LSE oscillator input OSC32_IN.
4	PC15-OSC32_OUT	bidirectional	5 V-tolerant GPIO powered through the VSW power switch, limited to 2 MHz output speed at 30 pF with no current sourcing; also the LSE oscillator output OSC32_OUT.
5	PH0-OSC_IN	bidirectional	5 V-tolerant (FT) GPIO; also the HSE oscillator input OSC_IN.
6	PH1-OSC_OUT	bidirectional	5 V-tolerant (FT) GPIO; also the HSE oscillator output OSC_OUT.
7	NRST	bidirectional	Bidirectional reset pin with an embedded weak pull-up resistor.
8	VSSA	power_in	Analog ground pin, shared with the VREF- function in the LQFP48 pinout.
9	VDDA	power_in	Analog supply, shared with the VREF+ function; minimum 1.62 V when ADC or COMP is used, 1.8 V with DAC, 2.0 V with OPAMP, up to 3.6 V.
10	PA0	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP0 analog input and WKUP1 wakeup.
11	PA1	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP1 analog input.
12	PA2	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP14 analog input and WKUP2 wakeup.
13	PA3	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP15 analog input.
14	PA4	bidirectional	3.6 V-tolerant (TT) I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP18 and DAC1_OUT1.
15	PA5	bidirectional	3.6 V-tolerant (TT) I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP19, DAC1_OUT2 and COMP1_INM3.
16	PA6	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP3 analog input.
17	PA7	bidirectional	3.6 V-tolerant (TT) I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP7 and OPAMP1_VOUT.
18	PB0	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP9, OPAMP1_VINP and COMP1_INP2.
19	PB1	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP5, OPAMP1_VINM and COMP1_INM2.
20	PB2	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also COMP1_INP3 and LSCO.
21	PB10	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option.
22	VCAP	power_in	Connection for the external capacitor stabilizing the embedded LDO; when two VCAP pins are present, each must be connected to a 2.2 µF (typical) capacitor.
23	VSS	power_in	Ground reference; all voltages are referenced to VSS.
24	VDD	power_in	Digital supply, 1.71 V to 3.6 V with HSLV=0 or 1.71 V to 2.7 V with HSLV=1.
25	PB12	bidirectional	5 V-tolerant I/O with HSLV option; also TIM1_BKIN and FDCAN1_RX alternate functions.
26	PB13	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option; also LPUART1_CTS, FDCAN1_TX and I3C2_SDA.
27	PB14	bidirectional	5 V-tolerant I/O with HSLV option; also USART1_TX and LPUART1_RTS.
28	PB15	bidirectional	5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also PVD_IN and COMP1_OUT.
29	PA8	bidirectional	5 V-tolerant I/O with HSLV option; also MCO1 and USB_SOF; supplied by VDD on this package because no VDDIO2 pin is provided.
30	PA9	bidirectional	5 V-tolerant I/O with HSLV option; also TRACED2 and USART1_TX; supplied by VDD on this package because no VDDIO2 pin is provided.
31	PA10	bidirectional	5 V-tolerant I/O with HSLV option; also USART1_RX and LPUART1_RX.
32	PA11	bidirectional	5 V-tolerant I/O with HSLV option; also USB_DM and FDCAN1_RX.
33	PA12	bidirectional	5 V-tolerant I/O with HSLV option; also USB_DP and FDCAN1_TX.
34	PA13	bidirectional	5 V-tolerant I/O with HSLV option; after reset it is JTMS/SWDIO with the internal pull-up activated.
35	VSS	power_in	Ground reference; all voltages are referenced to VSS.
36	VDD	power_in	Digital supply, 1.71 V to 3.6 V with HSLV=0 or 1.71 V to 2.7 V with HSLV=1.
37	PA14	bidirectional	5 V-tolerant I/O with HSLV option; after reset it is JTCK/SWCLK with the internal pull-down activated.
38	PA15	bidirectional	5 V-tolerant I/O with HSLV option, supplied by VDD on this package; after reset it is JTDI with the internal pull-up activated.
39	PB3	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option; after reset it is JTDO/TRACESWO, supplied by VDD on this package.
40	PB4	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option; after reset it is NJTRST with the internal pull-up activated.
41	PB5	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option; also I3C1_SDA and LPTIM1_IN1.
42	PB6	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option; also LPUART1_TX and USART1_TX.
43	PB7	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option; also WKUP5, LPUART1_RX and USART1_RX.
44	BOOT0	input	Dedicated boot pin; input voltage must not exceed min(min(VDD, VDDA, VDDIO2)+4.0 V, 6.0 V).
45	PB8	bidirectional	5 V-tolerant I/O, Fm+ capable, with HSLV option; also I3C1_SCL, I2C1_SCL and FDCAN1_RX.
46	VCAP	power_in	Connection for the external capacitor stabilizing the embedded LDO; when two VCAP pins are present, each must be connected to a 2.2 µF (typical) capacitor.
47	VSS	power_in	Ground reference; all voltages are referenced to VSS.
48	VDD	power_in	Digital supply, 1.71 V to 3.6 V with HSLV=0 or 1.71 V to 2.7 V with HSLV=1.

Key specifications

Parameter	Value
Manufacturer	STMICROELECTRONICS
Package	LQFP-48(7x7)
Category	Global Sourcing Parts
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDDx to VSS (external main supply incl. VDD, VDDA, VDDIO2, VBAT)	VDDx - VSS	-0.3		4	V	External main supply voltage (including VDD, VDDA, VDDIO2, and VBAT)	73
I/O supply voltage VDDIOx to VSS, HSLV = 0	VDDIOx - VSS	-0.3		4	V	I/O supply when HSLV = 0	73
I/O supply voltage VDDIOx to VSS, HSLV = 1	VDDIOx - VSS	-0.3		2.75	V	I/O supply when HSLV = 1	73
Input voltage on FT_xxx pins	VIN	-0.3			V	Max printed as formula min(min(VDD, VDDA, VDDIO2) + 4.0, 6.0 V); not a fixed number	74
Input voltage on FT_t in VBAT mode	VIN	-0.3			V	Max printed as formula min(min(VBAT, VDDA, VDDIO2) + 4.0, 6.0 V); not a fixed number	74
Input voltage on TT_xx pins	VIN	-0.3		4	V	TT_xx pins	74
Input voltage on BOOT0 pin	VIN	-0.3			V	Max printed as formula min(min(VDD, VDDA, VDDIO2) + 4.0, 6.0 V); not a fixed number	74
Input voltage on any other pins	VIN	-0.3		4	V	Any other pins	74
Total current into sum of all VDD power lines (source)	∑IVDD			200	mA	Source	74
Total current out of sum of all VSS ground lines (sink)	∑IVSS			200	mA	Sink	74
Output current sunk/sourced by any I/O and control pin	IIO(PIN)			20	mA	Any I/O and control pin	74
Total output current sunk by sum of all I/Os and control pins	∑IIO(PIN)			140	mA	Sunk	74
Total output current sourced by sum of all I/Os and control pins	∑IIO(PIN)			140	mA	Sourced	74
Injected current on FT_xxx, TT_xx, NRST pins	IINJ(PIN)	-5		0	mA	Injected current on FT_xxx, TT_xx, NRST pins	74
Storage temperature range	TSTG	-65		150	°C	Storage temperature range	75
Maximum junction temperature	TJ			130	°C	Limited to 105 °C in the VOS0 voltage range	75
Standard operating voltage VDD, HSLV = 0	VDD	1.71		3.6	V	HSLV = 0	75
Standard operating voltage VDD, HSLV = 1	VDD	1.71		2.7	V	HSLV = 1	75
Analog supply voltage VDDA, COMP used	VDDA	1.62		3.6	V	COMP is used	75
Analog supply voltage VDDA, DAC used	VDDA	1.8		3.6	V	DAC is used	75
Analog supply voltage VDDA, OPAMP used	VDDA	2		3.6	V	OPAMP is used	75
Analog supply voltage VDDA, ADC used	VDDA	1.62		3.6	V	ADC is used	75
Backup operating voltage	VBAT	1.2		3.6	V	Backup operating voltage	75
I/O input voltage, all I/O except TT_xx	VIN	-0.3			V	Max printed as formula min(min(VDD, VDDA, VDDIO2) + 3.6 V, 5.5 V)	76
Input voltage on FT_t in VBAT mode	VIN	-0.3			V	Max printed as formula min(min(VBAT, VDDA, VDDIO2) + 3.6 V, 5.5 V)	76
TT_xx I/O input voltage	VIN	-0.3			V	Max printed as formula VDDIOx + 0.3	76
Internal regulator ON, VOS0 core voltage	VCORE	1.3	1.35	1.4	V	Internal regulator ON, VOS0	76
Internal regulator ON, VOS1 core voltage	VCORE	1.15	1.2	1.26	V	Internal regulator ON, VOS1	76
Internal regulator ON, VOS2 core voltage	VCORE	1.05	1.1	1.15	V	Internal regulator ON, VOS2	76
Internal regulator ON, VOS3 core voltage	VCORE	0.95	1	1.05	V	Internal regulator ON, VOS3	76
AHB clock frequency fHCLK, VOS0	fHCLK			250	MHz	VOS0	76
AHB clock frequency fHCLK, VOS1	fHCLK			200	MHz	VOS1	76
AHB clock frequency fHCLK, VOS2	fHCLK			150	MHz	VOS2	76
AHB clock frequency fHCLK, VOS3	fHCLK			100	MHz	VOS3	76
Power dissipation, LQFP48, TA = 85 °C (suffix 6)	PD			831.79	mW	TA = 85 °C for suffix 6	77
Power dissipation, LQFP48, TA = 105 °C (suffix 7)	PD			462.11	mW	TA = 105 °C for suffix 7	77
Power dissipation, LQFP48, TA = 125 °C (suffix 7)	PD			92.42	mW	TA = 125 °C for suffix 7	77
Ambient temperature, suffix 6 version	TA	-40		85	°C	Maximum power dissipation	77
Ambient temperature, suffix 7 version	TA	-40		105	°C	Maximum power dissipation	77
Ambient temperature, LDO bypass or low dissipation at 125 °C	TA			125	°C	LDO bypass mode, or in low dissipation at 125 °C	77
Junction temperature range, suffix 6 and 7, VOS0	TJ	-40		105	°C	VOS0	77
Junction temperature range, suffix 6 and 7, VOS1/VOS2/VOS3	TJ	-40		130	°C	VOS1, VOS2, and VOS3	77
External capacitor CEXT for LDO enabled	CEXT		2.2		µF	Typical value, per VCAP pin when LDO enabled	78
CEXT tolerance	CEXT	-20		20	%	Variation of ±20 % tolerated	78
ESR of external VCAP capacitor	ESR			100	mΩ	ESR of external capacitor	78
Power-on/power-down reset threshold, rising edge	VPOR/PDR	1.62	1.67	1.71	V	BORH_EN = 0, rising edge	81
Power-on/power-down reset threshold, falling edge	VPOR/PDR	1.58	1.62	1.68	V	BORH_EN = 0, falling edge	81
Internal reference voltage	VREFINT	1.18	1.216	1.255	V	-40 °C < TJ < +130 °C	82
Average temperature coefficient of VREFINT	TCoeff		20	70	ppm/°C	Average temperature coefficient	82
Average voltage coefficient of VREFINT	VDDcoeff		10	1370	ppm/V	3.0 V < VDD < 3.6 V	82
HSE oscillator frequency	F	4		50	MHz	Oscillator frequency	98
HSE current consumption during startup	IDD(HSE)			10	mA	During startup	98
LSE oscillator frequency maximum (external clock)	fLSE_ext		32.768	1000	kHz	External digital/analog clock	96
HSI48 frequency	fHSI48	47.5	48	48.5	MHz	VDD=3.3 V, TJ=30 °C	101
HSI frequency	fHSI	63.7	64	64.3	MHz	VDD=3.3 V, TJ=30 °C	102
CSI frequency	fCSI	3.96	4	4.04	MHz	VDD=3.3 V, TJ=30 °C	103
LSI frequency over temperature and VDD	fLSI	29.76		33.6	kHz	TJ = -40 to 110 °C, VDD = 1.71 to 3.6 V	103
PLL input clock	fPLL_IN	2		16	MHz	Wide VCO frequency range	104
PLL VCO output frequency	fVCO_OUT	128		560	MHz	Wide VCO frequency range	104
Flash programming voltage	Vprog	1.71		3.6	V	Programming voltage	106

CAD (KiCad official)

Symbol: STM32H503CBT6
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm32h503cbt6-etched.step / stm32h503cbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32h503cbt6.step / stm32h503cbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMICROELECTRONICS datasheet (174 pp, sha256 87d98e42d910eabb, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# STM32H503CBT6

**STMICROELECTRONICS** · Global Sourcing Parts · LQFP-48(7x7)

STM32H503CBT6 from STMICROELECTRONICS, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC and backup registers, with a backup operating voltage of 1.2 V to 3.6 V. |
| 2 | PC13 | bidirectional | 5 V-tolerant (FT_t) GPIO powered through the VSW power switch and functional in VBAT mode with tamper function; output speed must not exceed 2 MHz at 30 pF and it must not be used as a current source. |
| 3 | PC14-OSC32_IN | bidirectional | 5 V-tolerant GPIO powered through the VSW power switch, limited to 2 MHz output speed at 30 pF with no current sourcing; also the LSE oscillator input OSC32_IN. |
| 4 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant GPIO powered through the VSW power switch, limited to 2 MHz output speed at 30 pF with no current sourcing; also the LSE oscillator output OSC32_OUT. |
| 5 | PH0-OSC_IN | bidirectional | 5 V-tolerant (FT) GPIO; also the HSE oscillator input OSC_IN. |
| 6 | PH1-OSC_OUT | bidirectional | 5 V-tolerant (FT) GPIO; also the HSE oscillator output OSC_OUT. |
| 7 | NRST | bidirectional | Bidirectional reset pin with an embedded weak pull-up resistor. |
| 8 | VSSA | power_in | Analog ground pin, shared with the VREF- function in the LQFP48 pinout. |
| 9 | VDDA | power_in | Analog supply, shared with the VREF+ function; minimum 1.62 V when ADC or COMP is used, 1.8 V with DAC, 2.0 V with OPAMP, up to 3.6 V. |
| 10 | PA0 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP0 analog input and WKUP1 wakeup. |
| 11 | PA1 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP1 analog input. |
| 12 | PA2 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP14 analog input and WKUP2 wakeup. |
| 13 | PA3 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP15 analog input. |
| 14 | PA4 | bidirectional | 3.6 V-tolerant (TT) I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP18 and DAC1_OUT1. |
| 15 | PA5 | bidirectional | 3.6 V-tolerant (TT) I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP19, DAC1_OUT2 and COMP1_INM3. |
| 16 | PA6 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP3 analog input. |
| 17 | PA7 | bidirectional | 3.6 V-tolerant (TT) I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP7 and OPAMP1_VOUT. |
| 18 | PB0 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP9, OPAMP1_VINP and COMP1_INP2. |
| 19 | PB1 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also ADC1_INP5, OPAMP1_VINM and COMP1_INM2. |
| 20 | PB2 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also COMP1_INP3 and LSCO. |
| 21 | PB10 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option. |
| 22 | VCAP | power_in | Connection for the external capacitor stabilizing the embedded LDO; when two VCAP pins are present, each must be connected to a 2.2 µF (typical) capacitor. |
| 23 | VSS | power_in | Ground reference; all voltages are referenced to VSS. |
| 24 | VDD | power_in | Digital supply, 1.71 V to 3.6 V with HSLV=0 or 1.71 V to 2.7 V with HSLV=1. |
| 25 | PB12 | bidirectional | 5 V-tolerant I/O with HSLV option; also TIM1_BKIN and FDCAN1_RX alternate functions. |
| 26 | PB13 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option; also LPUART1_CTS, FDCAN1_TX and I3C2_SDA. |
| 27 | PB14 | bidirectional | 5 V-tolerant I/O with HSLV option; also USART1_TX and LPUART1_RTS. |
| 28 | PB15 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA and HSLV option; also PVD_IN and COMP1_OUT. |
| 29 | PA8 | bidirectional | 5 V-tolerant I/O with HSLV option; also MCO1 and USB_SOF; supplied by VDD on this package because no VDDIO2 pin is provided. |
| 30 | PA9 | bidirectional | 5 V-tolerant I/O with HSLV option; also TRACED2 and USART1_TX; supplied by VDD on this package because no VDDIO2 pin is provided. |
| 31 | PA10 | bidirectional | 5 V-tolerant I/O with HSLV option; also USART1_RX and LPUART1_RX. |
| 32 | PA11 | bidirectional | 5 V-tolerant I/O with HSLV option; also USB_DM and FDCAN1_RX. |
| 33 | PA12 | bidirectional | 5 V-tolerant I/O with HSLV option; also USB_DP and FDCAN1_TX. |
| 34 | PA13 | bidirectional | 5 V-tolerant I/O with HSLV option; after reset it is JTMS/SWDIO with the internal pull-up activated. |
| 35 | VSS | power_in | Ground reference; all voltages are referenced to VSS. |
| 36 | VDD | power_in | Digital supply, 1.71 V to 3.6 V with HSLV=0 or 1.71 V to 2.7 V with HSLV=1. |
| 37 | PA14 | bidirectional | 5 V-tolerant I/O with HSLV option; after reset it is JTCK/SWCLK with the internal pull-down activated. |
| 38 | PA15 | bidirectional | 5 V-tolerant I/O with HSLV option, supplied by VDD on this package; after reset it is JTDI with the internal pull-up activated. |
| 39 | PB3 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option; after reset it is JTDO/TRACESWO, supplied by VDD on this package. |
| 40 | PB4 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option; after reset it is NJTRST with the internal pull-up activated. |
| 41 | PB5 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option; also I3C1_SDA and LPTIM1_IN1. |
| 42 | PB6 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option; also LPUART1_TX and USART1_TX. |
| 43 | PB7 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option; also WKUP5, LPUART1_RX and USART1_RX. |
| 44 | BOOT0 | input | Dedicated boot pin; input voltage must not exceed min(min(VDD, VDDA, VDDIO2)+4.0 V, 6.0 V). |
| 45 | PB8 | bidirectional | 5 V-tolerant I/O, Fm+ capable, with HSLV option; also I3C1_SCL, I2C1_SCL and FDCAN1_RX. |
| 46 | VCAP | power_in | Connection for the external capacitor stabilizing the embedded LDO; when two VCAP pins are present, each must be connected to a 2.2 µF (typical) capacitor. |
| 47 | VSS | power_in | Ground reference; all voltages are referenced to VSS. |
| 48 | VDD | power_in | Digital supply, 1.71 V to 3.6 V with HSLV=0 or 1.71 V to 2.7 V with HSLV=1. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMICROELECTRONICS |
| Package | LQFP-48(7x7) |
| Category | Global Sourcing Parts |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDx to VSS (external main supply incl. VDD, VDDA, VDDIO2, VBAT) | VDDx - VSS | -0.3 |  | 4 | V | External main supply voltage (including VDD, VDDA, VDDIO2, and VBAT) | 73 |
| I/O supply voltage VDDIOx to VSS, HSLV = 0 | VDDIOx - VSS | -0.3 |  | 4 | V | I/O supply when HSLV = 0 | 73 |
| I/O supply voltage VDDIOx to VSS, HSLV = 1 | VDDIOx - VSS | -0.3 |  | 2.75 | V | I/O supply when HSLV = 1 | 73 |
| Input voltage on FT_xxx pins | VIN | -0.3 |  |  | V | Max printed as formula min(min(VDD, VDDA, VDDIO2) + 4.0, 6.0 V); not a fixed number | 74 |
| Input voltage on FT_t in VBAT mode | VIN | -0.3 |  |  | V | Max printed as formula min(min(VBAT, VDDA, VDDIO2) + 4.0, 6.0 V); not a fixed number | 74 |
| Input voltage on TT_xx pins | VIN | -0.3 |  | 4 | V | TT_xx pins | 74 |
| Input voltage on BOOT0 pin | VIN | -0.3 |  |  | V | Max printed as formula min(min(VDD, VDDA, VDDIO2) + 4.0, 6.0 V); not a fixed number | 74 |
| Input voltage on any other pins | VIN | -0.3 |  | 4 | V | Any other pins | 74 |
| Total current into sum of all VDD power lines (source) | ∑IVDD |  |  | 200 | mA | Source | 74 |
| Total current out of sum of all VSS ground lines (sink) | ∑IVSS |  |  | 200 | mA | Sink | 74 |
| Output current sunk/sourced by any I/O and control pin | IIO(PIN) |  |  | 20 | mA | Any I/O and control pin | 74 |
| Total output current sunk by sum of all I/Os and control pins | ∑IIO(PIN) |  |  | 140 | mA | Sunk | 74 |
| Total output current sourced by sum of all I/Os and control pins | ∑IIO(PIN) |  |  | 140 | mA | Sourced | 74 |
| Injected current on FT_xxx, TT_xx, NRST pins | IINJ(PIN) | -5 |  | 0 | mA | Injected current on FT_xxx, TT_xx, NRST pins | 74 |
| Storage temperature range | TSTG | -65 |  | 150 | °C | Storage temperature range | 75 |
| Maximum junction temperature | TJ |  |  | 130 | °C | Limited to 105 °C in the VOS0 voltage range | 75 |
| Standard operating voltage VDD, HSLV = 0 | VDD | 1.71 |  | 3.6 | V | HSLV = 0 | 75 |
| Standard operating voltage VDD, HSLV = 1 | VDD | 1.71 |  | 2.7 | V | HSLV = 1 | 75 |
| Analog supply voltage VDDA, COMP used | VDDA | 1.62 |  | 3.6 | V | COMP is used | 75 |
| Analog supply voltage VDDA, DAC used | VDDA | 1.8 |  | 3.6 | V | DAC is used | 75 |
| Analog supply voltage VDDA, OPAMP used | VDDA | 2 |  | 3.6 | V | OPAMP is used | 75 |
| Analog supply voltage VDDA, ADC used | VDDA | 1.62 |  | 3.6 | V | ADC is used | 75 |
| Backup operating voltage | VBAT | 1.2 |  | 3.6 | V | Backup operating voltage | 75 |
| I/O input voltage, all I/O except TT_xx | VIN | -0.3 |  |  | V | Max printed as formula min(min(VDD, VDDA, VDDIO2) + 3.6 V, 5.5 V) | 76 |
| Input voltage on FT_t in VBAT mode | VIN | -0.3 |  |  | V | Max printed as formula min(min(VBAT, VDDA, VDDIO2) + 3.6 V, 5.5 V) | 76 |
| TT_xx I/O input voltage | VIN | -0.3 |  |  | V | Max printed as formula VDDIOx + 0.3 | 76 |
| Internal regulator ON, VOS0 core voltage | VCORE | 1.3 | 1.35 | 1.4 | V | Internal regulator ON, VOS0 | 76 |
| Internal regulator ON, VOS1 core voltage | VCORE | 1.15 | 1.2 | 1.26 | V | Internal regulator ON, VOS1 | 76 |
| Internal regulator ON, VOS2 core voltage | VCORE | 1.05 | 1.1 | 1.15 | V | Internal regulator ON, VOS2 | 76 |
| Internal regulator ON, VOS3 core voltage | VCORE | 0.95 | 1 | 1.05 | V | Internal regulator ON, VOS3 | 76 |
| AHB clock frequency fHCLK, VOS0 | fHCLK |  |  | 250 | MHz | VOS0 | 76 |
| AHB clock frequency fHCLK, VOS1 | fHCLK |  |  | 200 | MHz | VOS1 | 76 |
| AHB clock frequency fHCLK, VOS2 | fHCLK |  |  | 150 | MHz | VOS2 | 76 |
| AHB clock frequency fHCLK, VOS3 | fHCLK |  |  | 100 | MHz | VOS3 | 76 |
| Power dissipation, LQFP48, TA = 85 °C (suffix 6) | PD |  |  | 831.79 | mW | TA = 85 °C for suffix 6 | 77 |
| Power dissipation, LQFP48, TA = 105 °C (suffix 7) | PD |  |  | 462.11 | mW | TA = 105 °C for suffix 7 | 77 |
| Power dissipation, LQFP48, TA = 125 °C (suffix 7) | PD |  |  | 92.42 | mW | TA = 125 °C for suffix 7 | 77 |
| Ambient temperature, suffix 6 version | TA | -40 |  | 85 | °C | Maximum power dissipation | 77 |
| Ambient temperature, suffix 7 version | TA | -40 |  | 105 | °C | Maximum power dissipation | 77 |
| Ambient temperature, LDO bypass or low dissipation at 125 °C | TA |  |  | 125 | °C | LDO bypass mode, or in low dissipation at 125 °C | 77 |
| Junction temperature range, suffix 6 and 7, VOS0 | TJ | -40 |  | 105 | °C | VOS0 | 77 |
| Junction temperature range, suffix 6 and 7, VOS1/VOS2/VOS3 | TJ | -40 |  | 130 | °C | VOS1, VOS2, and VOS3 | 77 |
| External capacitor CEXT for LDO enabled | CEXT |  | 2.2 |  | µF | Typical value, per VCAP pin when LDO enabled | 78 |
| CEXT tolerance | CEXT | -20 |  | 20 | % | Variation of ±20 % tolerated | 78 |
| ESR of external VCAP capacitor | ESR |  |  | 100 | mΩ | ESR of external capacitor | 78 |
| Power-on/power-down reset threshold, rising edge | VPOR/PDR | 1.62 | 1.67 | 1.71 | V | BORH_EN = 0, rising edge | 81 |
| Power-on/power-down reset threshold, falling edge | VPOR/PDR | 1.58 | 1.62 | 1.68 | V | BORH_EN = 0, falling edge | 81 |
| Internal reference voltage | VREFINT | 1.18 | 1.216 | 1.255 | V | -40 °C < TJ < +130 °C | 82 |
| Average temperature coefficient of VREFINT | TCoeff |  | 20 | 70 | ppm/°C | Average temperature coefficient | 82 |
| Average voltage coefficient of VREFINT | VDDcoeff |  | 10 | 1370 | ppm/V | 3.0 V < VDD < 3.6 V | 82 |
| HSE oscillator frequency | F | 4 |  | 50 | MHz | Oscillator frequency | 98 |
| HSE current consumption during startup | IDD(HSE) |  |  | 10 | mA | During startup | 98 |
| LSE oscillator frequency maximum (external clock) | fLSE_ext |  | 32.768 | 1000 | kHz | External digital/analog clock | 96 |
| HSI48 frequency | fHSI48 | 47.5 | 48 | 48.5 | MHz | VDD=3.3 V, TJ=30 °C | 101 |
| HSI frequency | fHSI | 63.7 | 64 | 64.3 | MHz | VDD=3.3 V, TJ=30 °C | 102 |
| CSI frequency | fCSI | 3.96 | 4 | 4.04 | MHz | VDD=3.3 V, TJ=30 °C | 103 |
| LSI frequency over temperature and VDD | fLSI | 29.76 |  | 33.6 | kHz | TJ = -40 to 110 °C, VDD = 1.71 to 3.6 V | 103 |
| PLL input clock | fPLL_IN | 2 |  | 16 | MHz | Wide VCO frequency range | 104 |
| PLL VCO output frequency | fVCO_OUT | 128 |  | 560 | MHz | Wide VCO frequency range | 104 |
| Flash programming voltage | Vprog | 1.71 |  | 3.6 | V | Programming voltage | 106 |

## CAD (KiCad official)

- Symbol: `STM32H503CBT6`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm32h503cbt6-etched.step` / `stm32h503cbt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32h503cbt6.step` / `stm32h503cbt6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMICROELECTRONICS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904797077979136) (174 pp, sha256 `87d98e42d910eabb`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32h503cbt6-datasheet.pdf)