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Contents

README

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STM32G4A1KEU6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-32(5x5)

STM32G4A1KEU6 from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Standard operating voltage supply pin, 1.71 V to 3.6 V per the general operating conditions.
2 PF0-OSC_IN bidirectional 5 V tolerant (FT_fa) I/O that is Fm+ capable and has an analog switch supplied by VDDA; additional functions OSC_IN and ADC1_IN10, alternate functions I2C2_SDA, SPI2_NSS/I2S2_WS, TIM1_CH3N, EVENTOUT.
3 PF1-OSC_OUT bidirectional 5 V tolerant (FT_a) I/O with analog switch supplied by VDDA; additional functions OSC_OUT, ADC2_IN10 and COMP3_INM, alternate functions SPI2_SCK/I2S2_CK and EVENTOUT.
4 PG10-NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor (5 V tolerant FT I/O), alternate function MCO and EVENTOUT.
5 PA0 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM2_CH1, USART2_CTS, COMP1_OUT, TIM8_BKIN, TIM8_ETR, TIM2_ETR; additional ADC12_IN1, COMP1_INM, COMP3_INP, RTC_TAMP2, WKUP1.
6 PA1 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions RTC_REFIN, TIM2_CH2, USART2_RTS_DE, TIM15_CH1N; additional ADC12_IN2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP, OPAMP6_VINM.
7 PA2 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM2_CH3, USART2_TX, COMP2_OUT, TIM15_CH1, QUADSPI1_BK1_NCS, LPUART1_TX, UCPD1_FRSTX; additional ADC1_IN3, COMP2_INM, OPAMP1_VOUT, WKUP4/LSCO.
8 PA3 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM2_CH4, SAI1_CK1, USART2_RX, TIM15_CH2, QUADSPI1_CLK, LPUART1_RX, SAI1_MCLK_A; additional ADC1_IN4, COMP2_INP, OPAMP1_VINM/OPAMP1_VINP.
9 PA4 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM3_CH2, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, SAI1_FS_B; additional ADC2_IN17, DAC1_OUT1, COMP1_INM.
10 PA5 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM2_CH1, TIM2_ETR, SPI1_SCK, UCPD1_FRSTX; additional ADC2_IN13, DAC1_OUT2, COMP2_INM, OPAMP2_VINM.
11 PA6 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, COMP1_OUT, QUADSPI1_BK1_IO3, LPUART1_CTS; additional ADC2_IN3, OPAMP2_VOUT.
12 PA7 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM17_CH1, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, COMP2_OUT, QUADSPI1_BK1_IO2, UCPD1_FRSTX; additional ADC2_IN4, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP.
13 PB0 bidirectional 3.6 V tolerant (TT_a) I/O with analog switch supplied by VDDA; alternate functions TIM3_CH3, TIM8_CH2N, TIM1_CH2N, QUADSPI1_BK1_IO1, UCPD1_FRSTX; additional ADC1_IN15/ADC3_IN12, COMP4_INP, OPAMP2_VINP, OPAMP3_VINP.
14 VSSA power_in Analog ground pin, which must be connected to the external ground within the permitted VSS variation of 50 mV.
15 VDDA/VREF+ power_in Analog supply pin, which is internally connected to VREF+ on this package; VDDA is 1.62 V to 3.6 V when ADC or COMP is used and 2.0 V to 3.6 V when OPAMP is used.
16 VSS power_in Ground pin, which must always be connected to the external power supply ground within the permitted range.
17 VDD power_in Standard operating voltage supply pin, 1.71 V to 3.6 V per the general operating conditions.
18 PA8 bidirectional 5 V tolerant (FT_f) I/O that is Fm+ capable; alternate functions MCO, I2C3_SCL, I2C2_SDA, I2S2_MCK, TIM1_CH1, USART1_CK, TIM4_ETR, SAI1_CK2, SAI1_SCK_A, EVENTOUT.
19 PA9 bidirectional 5 V tolerant (FT_fd) Fm+ capable I/O with UCPD dead-battery function; a high level on PA9 activates the UCPD1_CC1 pull-down (5.1 kΩ) on PB6, and additional function is UCPD1_DBCC1.
20 PA10 bidirectional 5 V tolerant (FT_da) Fm+ capable I/O with UCPD dead-battery function; a high level on PA10 activates the UCPD1_CC2 pull-down (5.1 kΩ) on PB4, and additional function is UCPD1_DBCC2.
21 PA11 bidirectional 5 V tolerant (FT_u) I/O with USB function; additional function USB_DM, alternate functions include SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT, FDCAN1_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2.
22 PA12 bidirectional 5 V tolerant (FT_u) I/O with USB function; additional function USB_DP, alternate functions include TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX, TIM4_CH2, TIM1_ETR.
23 PA13 bidirectional 5 V tolerant (FT_f) Fm+ capable I/O; after reset it is the SWDIO-JTMS debug function with internal pull-up activated, alternate functions include I2C1_SCL, IR_OUT, USART3_CTS and SAI1_SD_B.
24 PA14 bidirectional 5 V tolerant (FT_f) Fm+ capable I/O; after reset it is the SWCLK-JTCK debug function with internal pull-down activated, alternate functions include LPTIM1_OUT, I2C1_SDA, TIM8_CH2, USART2_TX and SAI1_FS_B.
25 PA15 bidirectional 5 V tolerant (FT_f) Fm+ capable I/O; after reset it is the JTDI debug function with internal pull-up activated, alternate functions include TIM2_CH1, TIM8_CH1, I2C1_SCL, SPI1_NSS, USART2_RX and TIM1_BKIN.
26 PB3 bidirectional 5 V tolerant (FT) I/O; after reset it is the JTDO/TRACESWO debug function, alternate functions include TIM2_CH2, TIM4_ETR, USB_CRS_SYNC, SPI1_SCK, USART2_TX and SAI1_SCK_B.
27 PB4 bidirectional 5 V tolerant (FT_c) I/O with USB Type-C PD function; after reset it is the JTRST debug function with internal pull-up activated, and the UCPD1_CC2 pull-down (5.1 kΩ) is controlled by PA10.
28 PB5 bidirectional 5 V tolerant (FT_f) Fm+ capable I/O; alternate functions include TIM16_BKIN, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, USART2_CK, I2C3_SDA, FDCAN2_RX, TIM17_CH1, LPTIM1_IN1 and SAI1_SD_B.
29 PB6 bidirectional 5 V tolerant (FT_c) I/O with USB Type-C PD function; the UCPD1_CC1 pull-down (5.1 kΩ) is activated by a high level on PA9, alternate functions include TIM16_CH1N, TIM4_CH1, TIM8_CH1, USART1_TX, FDCAN2_TX and LPTIM1_ETR.
30 PB7 bidirectional 5 V tolerant (FT_f) Fm+ capable I/O with additional function PVD_IN; alternate functions include TIM17_CH1N, TIM4_CH2, I2C1_SDA, TIM8_BKIN, USART1_RX, COMP3_OUT and LPTIM1_IN2.
31 PB8-BOOT0 bidirectional 5 V tolerant (FT_f) Fm+ capable I/O that also serves as BOOT0 pin; it is recommended to set PB8 to a mode other than analog after startup to limit consumption if the pin is left unconnected.
32 VSS power_in Ground pin, which must always be connected to the external power supply ground within the permitted range.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: STM32G4A1KEU6
  • Footprint: Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
  • 3D model: UFQFPN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: stm32g4a1keu6-etched.step / stm32g4a1keu6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g4a1keu6.step / stm32g4a1keu6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (200 pp, sha256 cde1526cdcf6f83b, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF