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STM32G491RET6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32G491RET6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32G491RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup supply for RTC and backup registers, operating range 1.55 V to 3.6 V.
2 PC13 bidirectional FT I/O supplied through the power switch (3 mA max sink), so output speed is limited to 2 MHz with 30 pF max load; additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT1.
3 PC14-OSC32_IN bidirectional FT I/O supplied through the power switch with limited output (2 MHz, 30 pF max); additional function OSC32_IN for the 32.768 kHz LSE crystal.
4 PC15-OSC32_OUT bidirectional FT I/O supplied through the power switch with limited output (2 MHz, 30 pF max); additional function OSC32_OUT for the 32.768 kHz LSE crystal.
5 PF0-OSC_IN bidirectional FT_fa I/O with I2C2_SDA, SPI2_NSS/I2S2_WS and TIM1_CH3N alternate functions; additional functions ADC1_IN10 and OSC_IN (HSE crystal input).
6 PF1-OSC_OUT bidirectional FT_a I/O with SPI2_SCK/I2S2_CK alternate function; additional functions ADC2_IN10, COMP3_INM and OSC_OUT (HSE crystal output).
7 PG10-NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor (NRST); also usable as PG10 with MCO alternate function.
8 PC0 bidirectional FT_a I/O with LPTIM1_IN1, TIM1_CH1 and LPUART1_RX alternate functions; additional functions ADC12_IN6 and COMP3_INM.
9 PC1 bidirectional TT_a I/O with LPTIM1_OUT, TIM1_CH2, LPUART1_TX, QUADSPI1_BK2_IO0 and SAI1_SD_A alternate functions; additional functions ADC12_IN7 and COMP3_INP.
10 PC2 bidirectional FT_a I/O with LPTIM1_IN2, TIM1_CH3, COMP3_OUT, TIM20_CH2 and QUADSPI1_BK2_IO1 alternate functions; additional function ADC12_IN8.
11 PC3 bidirectional FT_a I/O with LPTIM1_ETR, TIM1_CH4, SAI1_D1, TIM1_BKIN2, QUADSPI1_BK2_IO2 and SAI1_SD_A alternate functions; additional function ADC12_IN9.
12 PA0 bidirectional TT_a I/O with TIM2_CH1, USART2_CTS, COMP1_OUT, TIM8_BKIN and TIM8_ETR alternate functions; additional functions ADC12_IN1, COMP1_INM, COMP3_INP, RTC_TAMP2 and WKUP1.
13 PA1 bidirectional TT_a I/O with RTC_REFIN, TIM2_CH2, USART2_RTS_DE and TIM15_CH1N alternate functions; additional functions ADC12_IN2, COMP1_INP and OPAMP1_VINP/OPAMP3_VINP/OPAMP6_VINM.
14 PA2 bidirectional TT_a I/O with TIM2_CH3, USART2_TX, COMP2_OUT, TIM15_CH1, QUADSPI1_BK1_NCS, LPUART1_TX and UCPD1_FRSTX alternate functions; additional functions ADC1_IN3, COMP2_INM, OPAMP1_VOUT and WKUP4/LSCO.
15 VSS power_in Digital ground supply pin; must be connected to the external ground.
16 VDD power_in Digital supply pin, 1.71 V to 3.6 V operating range, to be decoupled with ceramic capacitors.
17 PA3 bidirectional TT_a I/O with TIM2_CH4, SAI1_CK1, USART2_RX, TIM15_CH2, QUADSPI1_CLK, LPUART1_RX and SAI1_MCLK_A alternate functions; additional functions ADC1_IN4, COMP2_INP and OPAMP1_VINM/OPAMP1_VINP.
18 PA4 bidirectional TT_a I/O with TIM3_CH2, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK and SAI1_FS_B alternate functions; additional functions ADC2_IN17, DAC1_OUT1 and COMP1_INM.
19 PA5 bidirectional TT_a I/O with TIM2_CH1, TIM2_ETR, SPI1_SCK and UCPD1_FRSTX alternate functions; additional functions ADC2_IN13, DAC1_OUT2, COMP2_INM and OPAMP2_VINM.
20 PA6 bidirectional TT_a I/O with TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, COMP1_OUT, QUADSPI1_BK1_IO3 and LPUART1_CTS alternate functions; additional functions ADC2_IN3 and OPAMP2_VOUT.
21 PA7 bidirectional TT_a I/O with TIM17_CH1, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, COMP2_OUT, QUADSPI1_BK1_IO2 and UCPD1_FRSTX alternate functions; additional functions ADC2_IN4, COMP2_INP, OPAMP1_VINP and OPAMP2_VINP.
22 PC4 bidirectional FT_fa I/O with TIM1_ETR, I2C2_SCL, USART1_TX and QUADSPI1_BK2_IO3 alternate functions; additional function ADC2_IN5.
23 PC5 bidirectional TT_a I/O with TIM15_BKIN, SAI1_D3, TIM1_CH4N and USART1_RX alternate functions; additional functions ADC2_IN11, OPAMP1_VINM, OPAMP2_VINM and WKUP5.
24 PB0 bidirectional TT_a I/O with TIM3_CH3, TIM8_CH2N, TIM1_CH2N, QUADSPI1_BK1_IO1 and UCPD1_FRSTX alternate functions; additional functions ADC1_IN15/ADC3_IN12, COMP4_INP, OPAMP2_VINP and OPAMP3_VINP.
25 PB1 bidirectional TT_a I/O with TIM3_CH4, TIM8_CH3N, TIM1_CH3N, COMP4_OUT, QUADSPI1_BK1_IO0 and LPUART1_RTS_DE alternate functions; additional functions ADC1_IN12/ADC3_IN1, COMP1_INP, OPAMP3_VOUT and OPAMP6_VINM.
26 PB2 bidirectional TT_a I/O with RTC_OUT2, LPTIM1_OUT, TIM20_CH1, I2C3_SMBA and QUADSPI1_BK2_IO1 alternate functions; additional functions ADC2_IN12, COMP4_INM and OPAMP3_VINM.
27 VSSA power_in Analog ground supply pin for the analog domain (ADC, DAC, OPAMP, COMP, VREFBUF).
28 VREF+ power_in Voltage reference pin; additional function VREFBUF_OUT (internal reference buffer output); VREF+ must not exceed VDDA by more than 0.4 V.
29 VDDA power_in Analog supply pin, 1.62 V to 3.6 V when ADC or COMP is used (2.0 V min with OPAMP, 2.4 V min with VREFBUF).
30 PB10 bidirectional TT_a I/O with TIM2_CH3, USART3_TX, LPUART1_RX, QUADSPI1_CLK, TIM1_BKIN and SAI1_SCK_A alternate functions; additional function OPAMP3_VINM.
31 VSS power_in Digital ground supply pin; must be connected to the external ground.
32 VDD power_in Digital supply pin, 1.71 V to 3.6 V operating range, to be decoupled with ceramic capacitors.
33 PB11 bidirectional TT_a I/O with TIM2_CH4, USART3_RX, LPUART1_TX and QUADSPI1_BK1_NCS alternate functions; additional functions ADC12_IN14 and OPAMP6_VOUT.
34 PB12 bidirectional TT_a I/O with I2C2_SMBA, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK, LPUART1_RTS_DE and FDCAN2_RX alternate functions; additional functions ADC1_IN11 and OPAMP6_VINP.
35 PB13 bidirectional TT_a I/O with SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS, LPUART1_CTS and FDCAN2_TX alternate functions; additional functions ADC3_IN5, OPAMP3_VINP and OPAMP6_VINP.
36 PB14 bidirectional TT_a I/O with TIM15_CH1, SPI2_MISO, TIM1_CH2N, USART3_RTS_DE and COMP4_OUT alternate functions; additional functions ADC1_IN5 and OPAMP2_VINP.
37 PB15 bidirectional FT_a I/O with RTC_REFIN, TIM15_CH2, TIM15_CH1N, COMP3_OUT, TIM1_CH3N and SPI2_MOSI/I2S2_SD alternate functions; additional function ADC2_IN15.
38 PC6 bidirectional FT I/O with TIM3_CH1, TIM8_CH1 and I2S2_MCK alternate functions.
39 PC7 bidirectional FT I/O with TIM3_CH2, TIM8_CH2 and I2S3_MCK alternate functions.
40 PC8 bidirectional FT_f I/O (Fm+ capable) with TIM3_CH3, TIM8_CH3, TIM20_CH3 and I2C3_SCL alternate functions.
41 PC9 bidirectional FT_f I/O (Fm+ capable) with TIM3_CH4, TIM8_CH4, I2SCKIN, TIM8_BKIN2 and I2C3_SDA alternate functions.
42 PA8 bidirectional FT_f I/O with MCO, I2C3_SCL, I2C2_SDA, I2S2_MCK, TIM1_CH1, USART1_CK, TIM4_ETR, SAI1_CK2 and SAI1_SCK_A alternate functions.
43 PA9 bidirectional FT_fd I/O with I2C3_SMBA, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3 and SAI1_FS_A alternate functions; additional function UCPD1_DBCC1 (dead battery control).
44 PA10 bidirectional FT_da I/O with TIM17_BKIN, USB_CRS_SYNC, I2C2_SMBA, SPI2_MISO, TIM1_CH3, USART1_RX, TIM2_CH4, TIM8_BKIN, SAI1_D1 and SAI1_SD_A alternate functions; additional function UCPD1_DBCC2 (dead battery control).
45 PA11 bidirectional FT_u I/O with SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT, FDCAN1_RX, TIM4_CH1, TIM1_CH4 and TIM1_BKIN2 alternate functions; additional function USB_DM.
46 PA12 bidirectional FT_u I/O with TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX, TIM4_CH2 and TIM1_ETR alternate functions; additional function USB_DP.
47 VSS power_in Digital ground supply pin; must be connected to the external ground.
48 VDD power_in Digital supply pin, 1.71 V to 3.6 V operating range, to be decoupled with ceramic capacitors.
49 PA13 bidirectional FT_f I/O that is SWDIO-JTMS after reset (internal pull-up active), with TIM16_CH1N, I2C1_SCL, IR_OUT, USART3_CTS, TIM4_CH3 and SAI1_SD_B alternate functions.
50 PA14 bidirectional FT_f I/O that is SWCLK-JTCK after reset (internal pull-down active), with LPTIM1_OUT, I2C1_SDA, TIM8_CH2, TIM1_BKIN, USART2_TX and SAI1_FS_B alternate functions.
51 PA15 bidirectional FT_f I/O that is JTDI after reset (internal pull-up active), with TIM2_CH1, TIM8_CH1, TIM20_ETR, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, UART4_RTS_DE and TIM1_BKIN alternate functions.
52 PC10 bidirectional FT I/O with TIM8_CH1N, UART4_TX, SPI3_SCK/I2S3_CK and USART3_TX alternate functions.
53 PC11 bidirectional FT_f I/O with TIM8_CH2N, UART4_RX, SPI3_MISO, USART3_RX and I2C3_SDA alternate functions.
54 PC12 bidirectional FT I/O with TIM8_CH3N, UART5_TX, SPI3_MOSI/I2S3_SD, USART3_CK and UCPD1_FRSTX alternate functions.
55 PD2 bidirectional FT I/O with TIM3_ETR, TIM8_BKIN and UART5_RX alternate functions.
56 PB3 bidirectional FT I/O that is JTDO/TRACESWO after reset, with TIM2_CH2, TIM4_ETR, USB_CRS_SYNC, TIM8_CH1N, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR and SAI1_SCK_B alternate functions.
57 PB4 bidirectional FT_c I/O that is JTRST after reset (internal pull-up active), with TIM16_CH1, TIM3_CH1, SPI1_MISO, SPI3_MISO, USART2_RX, UART5_RTS_DE and SAI1_MCLK_B alternate functions; additional function UCPD1_CC2 with 5.1 kΩ dead-battery pull-down.
58 PB5 bidirectional FT_f I/O with TIM16_BKIN, TIM3_CH2, TIM8_CH3N, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, FDCAN2_RX, TIM17_CH1, LPTIM1_IN1, SAI1_SD_B and UART5_CTS alternate functions.
59 PB6 bidirectional FT_c I/O with TIM16_CH1N, TIM4_CH1, TIM8_CH1, TIM8_ETR, USART1_TX, COMP4_OUT, FDCAN2_TX, TIM8_BKIN2, LPTIM1_ETR and SAI1_FS_B alternate functions; additional function UCPD1_CC1 with 5.1 kΩ dead-battery pull-down.
60 PB7 bidirectional FT_f I/O with TIM17_CH1N, TIM4_CH2, I2C1_SDA, TIM8_BKIN, USART1_RX, COMP3_OUT, TIM3_CH4, LPTIM1_IN2 and UART4_CTS alternate functions; additional function PVD_IN.
61 PB8-BOOT0 bidirectional FT_f I/O that doubles as the BOOT0 pin, with TIM16_CH1, TIM4_CH3, SAI1_CK1, I2C1_SCL, USART3_RX, COMP1_OUT, FDCAN1_RX, TIM8_CH2, TIM1_BKIN and SAI1_MCLK_A alternate functions; set to a mode other than analog after startup to limit consumption if left unconnected.
62 PB9 bidirectional FT_f I/O with TIM17_CH1, TIM4_CH4, SAI1_D2, I2C1_SDA, IR_OUT, USART3_TX, COMP2_OUT, FDCAN1_TX, TIM8_CH3, TIM1_CH3N and SAI1_FS_A alternate functions.
63 VSS power_in Digital ground supply pin; must be connected to the external ground.
64 VDD power_in Digital supply pin, 1.71 V to 3.6 V operating range, to be decoupled with ceramic capacitors.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32G491RET6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32g491ret6-etched.step / stm32g491ret6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g491ret6.step / stm32g491ret6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (199 pp, sha256 ba71e197157250a1, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF