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STM32G491CET6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32G491CET6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
STM32G491CET6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC, backup registers and the power switch feeding PC13 to PC15; operating range is 1.55 V to 3.6 V. |
| 2 | PC13 | bidirectional | 5 V tolerant GPIO on the power-switch domain, which sinks only 3 mA, so output use is limited to 2 MHz at 30 pF maximum and it must not source current to loads such as LEDs; also WKUP2, RTC_TAMP1, RTC_TS and RTC_OUT1. |
| 3 | PC14-OSC32_IN | bidirectional | 5 V tolerant GPIO on the power-switch domain with the same 3 mA and 2 MHz / 30 pF output limits as PC13, also serving as the 32 kHz oscillator input OSC32_IN. |
| 4 | PC15-OSC32_OUT | bidirectional | 5 V tolerant GPIO on the power-switch domain with the same 3 mA and 2 MHz / 30 pF output limits as PC13, also serving as the 32 kHz oscillator output OSC32_OUT. |
| 5 | PF0-OSC_IN | bidirectional | 5 V tolerant, Fm+ capable I/O with analog switch supplied by VDDA, also serving as the HSE oscillator input OSC_IN and ADC1_IN10, with I2C2_SDA and SPI2_NSS/I2S2_WS alternate functions. |
| 6 | PF1-OSC_OUT | bidirectional | 5 V tolerant I/O with analog switch supplied by VDDA, also serving as the HSE oscillator output OSC_OUT, with ADC2_IN10 and COMP3_INM additional functions. |
| 7 | PG10-NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor (NRST), also providing the MCO alternate function. |
| 8 | PA0 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC12_IN1, WKUP1, RTC_TAMP2 and TIM2_CH1 / USART2_CTS. |
| 9 | PA1 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC12_IN2, RTC_REFIN, OPAMP1_VINP and TIM2_CH2 / USART2_RTS_DE. |
| 10 | PA2 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC1_IN3, COMP2_OUT, WKUP4/LSCO, TIM2_CH3 and USART2_TX. |
| 11 | PA3 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC1_IN4, OPAMP1_VINM/OPAMP1_VINP, TIM2_CH4 and USART2_RX. |
| 12 | PA4 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC2_IN17, DAC1_OUT1, COMP1_INM, SPI1_NSS and TIM3_CH2. |
| 13 | PA5 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC2_IN13, DAC1_OUT2, COMP2_INM, OPAMP2_VINM, SPI1_SCK and TIM2_CH1. |
| 14 | PA6 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC2_IN3, OPAMP2_VOUT, COMP1_OUT, SPI1_MISO and TIM16_CH1. |
| 15 | PA7 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC2_IN4, COMP2_INP, OPAMP1_VINP/OPAMP2_VINP, SPI1_MOSI and TIM17_CH1. |
| 16 | PB0 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC1_IN15/ADC3_IN12, COMP4_INP, OPAMP2_VINP, OPAMP3_VINP and TIM3_CH3. |
| 17 | PB1 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC1_IN12/ADC3_IN1, COMP1_INP, OPAMP3_VOUT, OPAMP6_VINM and TIM3_CH4. |
| 18 | PB2 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC2_IN12, COMP4_INM, OPAMP3_VINM, RTC_OUT2 and LPTIM1_OUT. |
| 19 | VSSA | power_in | Analog ground for the ADC, DAC, OPAMP, COMP and VREFBUF; ground-pin variations must stay within 50 mV of VSS. |
| 20 | VREF+ | power_in | Positive reference voltage input for the ADC and DAC (also VREFBUF_OUT); VREF+ may exceed VDDA by no more than 0.4 V and can be internally connected to VDDA depending on package. |
| 21 | VDDA | power_in | Analog supply for the ADC, DAC, OPAMP, COMP and VREFBUF; minimum 1.62 V for ADC or COMP, 1.71 V for DAC, 2.0 V for OPAMP and 2.4 V for VREFBUF, maximum 3.6 V. |
| 22 | PB10 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also OPAMP3_VINM, TIM2_CH3, USART3_TX, LPUART1_RX and QUADSPI1_CLK. |
| 23 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground. |
| 24 | VDD | power_in | Main digital supply pin; operating voltage range is 1.71 V to 3.6 V. |
| 25 | PB11 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC12_IN14, OPAMP6_VOUT, TIM2_CH4, USART3_RX and LPUART1_TX. |
| 26 | PB12 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC1_IN11, OPAMP6_VINP, SPI2_NSS/I2S2_WS, USART3_CK and FDCAN2_RX. |
| 27 | PB13 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC3_IN5, OPAMP3_VINP, OPAMP6_VINP, SPI2_SCK/I2S2_CK, USART3_CTS and FDCAN2_TX. |
| 28 | PB14 | bidirectional | 3.6 V tolerant I/O with analog switch supplied by VDDA; also ADC1_IN5, OPAMP2_VINP, TIM15_CH1, SPI2_MISO and COMP4_OUT. |
| 29 | PB15 | bidirectional | 5 V tolerant I/O with analog switch supplied by VDDA; also ADC2_IN15, RTC_REFIN, TIM15_CH2, COMP3_OUT and SPI2_MOSI/I2S2_SD. |
| 30 | PA8 | bidirectional | 5 V tolerant, Fm+ capable I/O; also MCO, I2C3_SCL, I2C2_SDA, TIM1_CH1, USART1_CK and SAI1_CK2. |
| 31 | PA9 | bidirectional | 5 V tolerant, Fm+ capable I/O with USB Type-C dead-battery function; a high level on this pin activates the internal 5.1 kΩ pull-down on PB6 (UCPD1_CC1) after reset, also USART1_TX, I2C2_SCL and TIM1_CH2. |
| 32 | PA10 | bidirectional | 5 V tolerant, Fm+ capable I/O with USB Type-C dead-battery function; a high level on this pin activates the internal 5.1 kΩ pull-down on PB4 (UCPD1_CC2) after reset, also USART1_RX, SPI2_MISO and USB_CRS_SYNC. |
| 33 | PA11 | bidirectional | 5 V tolerant I/O with USB function; also USB_DM, USART1_CTS, SPI2_MOSI/I2S2_SD, TIM1_CH1N, COMP1_OUT and FDCAN1_RX. |
| 34 | PA12 | bidirectional | 5 V tolerant I/O with USB function; also USB_DP, USART1_RTS_DE, TIM16_CH1, COMP2_OUT and FDCAN1_TX. |
| 35 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground. |
| 36 | VDD | power_in | Main digital supply pin; operating voltage range is 1.71 V to 3.6 V. |
| 37 | PA13 | bidirectional | 5 V tolerant, Fm+ capable I/O; after reset it is configured as SWDIO-JTMS with an internal pull-up enabled, also IR_OUT, I2C1_SCL and USART3_CTS. |
| 38 | PA14 | bidirectional | 5 V tolerant, Fm+ capable I/O; after reset it is configured as SWCLK-JTCK with an internal pull-down enabled, also I2C1_SDA, LPTIM1_OUT and USART2_TX. |
| 39 | PA15 | bidirectional | 5 V tolerant, Fm+ capable I/O; after reset it is configured as JTDI with an internal pull-up enabled, also TIM2_CH1, SPI1_NSS, SPI3_NSS/I2S3_WS and USART2_RX. |
| 40 | PB3 | bidirectional | 5 V tolerant I/O; after reset it is configured as JTDO/TRACESWO debug alternate function, also SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX and TIM2_CH2. |
| 41 | PB4 | bidirectional | 5 V tolerant, USB Type-C CC capable I/O; after reset it is configured as JTRST with an internal pull-up enabled and its UCPD1_CC2 pull-down is enabled unless disabled, also SPI1_MISO, USART2_RX and TIM16_CH1. |
| 42 | PB5 | bidirectional | 5 V tolerant, Fm+ capable I/O; also TIM16_BKIN, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, FDCAN2_RX and LPTIM1_IN1. |
| 43 | PB6 | bidirectional | 5 V tolerant, USB Type-C CC capable I/O; its UCPD1_CC1 pull-down is controlled by the level on PA9 after reset, also TIM16_CH1N, TIM4_CH1, USART1_TX, COMP4_OUT and FDCAN2_TX. |
| 44 | PB7 | bidirectional | 5 V tolerant, Fm+ capable I/O; also PVD_IN, TIM17_CH1N, TIM4_CH2, I2C1_SDA, USART1_RX and COMP3_OUT. |
| 45 | PB8-BOOT0 | bidirectional | 5 V tolerant, Fm+ capable I/O that also carries the BOOT0 function; the datasheet recommends setting it to a mode other than analog after startup to limit consumption if left unconnected, also TIM16_CH1, I2C1_SCL and USART3_RX. |
| 46 | PB9 | bidirectional | 5 V tolerant, Fm+ capable I/O; also TIM17_CH1, TIM4_CH4, I2C1_SDA, IR_OUT, USART3_TX, COMP2_OUT and FDCAN1_TX. |
| 47 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground. |
| 48 | VDD | power_in | Main digital supply pin; operating voltage range is 1.71 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
STM32G491CET6 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32g491cet6-etched.step/stm32g491cet6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32g491cet6.step/stm32g491cet6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (199 pp, sha256
ba71e197157250a1, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).