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STM32G474QET3
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-128(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32G474QET3
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-128(14x14)
STM32G474QET3 from STMicroelectronics, in a LQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant I/O (FT); alternate functions TRACECK, TIM3_CH1, SAI1_CK1, SPI4_SCK, TIM20_CH1, FMC_A23, SAI1_MCLK_A, EVENTOUT; no additional function. |
| 2 | PE3 | bidirectional | 5 V tolerant I/O (FT); alternate functions TRACED0, TIM3_CH2, SPI4_NSS, TIM20_CH2, FMC_A19, SAI1_SD_B, EVENTOUT; no additional function. |
| 3 | PE4 | bidirectional | 5 V tolerant I/O (FT); alternate functions TRACED1, TIM3_CH3, SAI1_D2, SPI4_NSS, TIM20_CH1N, FMC_A20, SAI1_FS_A, EVENTOUT; no additional function. |
| 4 | PE5 | bidirectional | 5 V tolerant I/O (FT); alternate functions TRACED2, TIM3_CH4, SAI1_CK2, SPI4_MISO, TIM20_CH2N, FMC_A21, SAI1_SCK_A, EVENTOUT; no additional function. |
| 5 | PE6 | bidirectional | 5 V tolerant I/O (FT); alternate functions TRACED3, SAI1_D1, SPI4_MOSI, TIM20_CH3N, FMC_A22, SAI1_SD_A, EVENTOUT; additional functions WKUP3, RTC_TAMP3. |
| 6 | VBAT | power_in | Backup domain supply for RTC and backup registers; VBAT operating range is 1.55 V to 3.6 V. |
| 7 | PC13 | bidirectional | 5 V tolerant I/O (FT) supplied through the power switch, limited to 3 mA sink, so output use is limited to 2 MHz at 30 pF max and it must not drive current sources such as LEDs; alternate functions TIM1_BKIN, TIM1_CH1N, TIM8_CH4N, EVENTOUT; additional functions WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT1. |
| 8 | PC14-OSC32_IN | bidirectional | 5 V tolerant I/O (FT) on the backup power switch with the same 3 mA and output-speed limits as PC13; additional function OSC32_IN (32 kHz oscillator input), alternate function EVENTOUT. |
| 9 | PC15-OSC32_OUT | bidirectional | 5 V tolerant I/O (FT) on the backup power switch with the same 3 mA and output-speed limits as PC13; additional function OSC32_OUT (32 kHz oscillator output), alternate function EVENTOUT. |
| 10 | PF3 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM20_CH4, I2C3_SCL, FMC_A3, EVENTOUT. |
| 11 | PF4 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions COMP1_OUT, TIM20_CH1N, I2C3_SDA, FMC_A4, EVENTOUT. |
| 12 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 13 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
| 14 | PF5 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_CH2N, FMC_A5, EVENTOUT. |
| 15 | PF7 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_BKIN, TIM5_CH2, QUADSPI1_BK1_IO2, FMC_A1, SAI1_MCLK_B, EVENTOUT. |
| 16 | PF8 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_BKIN2, TIM5_CH3, QUADSPI1_BK1_IO0, FMC_A24, SAI1_SCK_B, EVENTOUT. |
| 17 | PF9 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_BKIN, TIM15_CH1, SPI2_SCK, TIM5_CH4, QUADSPI1_BK1_IO1, FMC_A25, SAI1_FS_B, EVENTOUT. |
| 18 | PF10 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_BKIN2, TIM15_CH2, SPI2_SCK, QUADSPI1_CLK, FMC_A0, SAI1_D3, EVENTOUT. |
| 19 | PF0-OSC_IN | bidirectional | 5 V tolerant I/O with analog switch and Fm+ capability (FT_fa); alternate functions I2C2_SDA, SPI2_NSS/I2S2_WS, TIM1_CH3N, EVENTOUT; additional functions ADC1_IN10, OSC_IN. |
| 20 | PF1-OSC_OUT | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions SPI2_SCK/I2S2_CK, EVENTOUT; additional functions ADC2_IN10, COMP3_INM, OSC_OUT. |
| 21 | PG10-NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor (FT I/O); alternate function MCO, EVENTOUT; additional function NRST. |
| 22 | PC0 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions LPTIM1_IN1, TIM1_CH1, LPUART1_RX, EVENTOUT; additional functions ADC12_IN6, COMP3_INM. |
| 23 | PC1 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions LPTIM1_OUT, TIM1_CH2, LPUART1_TX, QUADSPI1_BK2_IO0, SAI1_SD_A, EVENTOUT; additional functions ADC12_IN7, COMP3_INP. |
| 24 | PC2 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions LPTIM1_IN2, TIM1_CH3, COMP3_OUT, TIM20_CH2, QUADSPI1_BK2_IO1, EVENTOUT; additional function ADC12_IN8. |
| 25 | PC3 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions LPTIM1_ETR, TIM1_CH4, SAI1_D1, TIM1_BKIN2, QUADSPI1_BK2_IO2, SAI1_SD_A, EVENTOUT; additional functions ADC12_IN9, OPAMP5_VINP. |
| 26 | PF2 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_CH3, I2C2_SMBA, FMC_A2, EVENTOUT. |
| 27 | PA0 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM2_CH1, TIM5_CH1, USART2_CTS, COMP1_OUT, TIM8_BKIN, TIM8_ETR, TIM2_ETR, EVENTOUT; additional functions ADC12_IN1, COMP1_INM, COMP3_INP, RTC_TAMP2, WKUP1. |
| 28 | PA1 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions RTC_REFIN, TIM2_CH2, TIM5_CH2, USART2_RTS_DE, TIM15_CH1N, EVENTOUT; additional functions ADC12_IN2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP, OPAMP6_VINM. |
| 29 | PA2 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM2_CH3, TIM5_CH3, USART2_TX, COMP2_OUT, TIM15_CH1, QUADSPI1_BK1_NCS, LPUART1_TX, UCPD1_FRSTX, EVENTOUT; additional functions ADC1_IN3, COMP2_INM, OPAMP1_VOUT, WKUP4/LSCO. |
| 30 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 31 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
| 32 | PA3 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM2_CH4, TIM5_CH4, SAI1_CK1, USART2_RX, TIM15_CH2, QUADSPI1_CLK, LPUART1_RX, SAI1_MCLK_A, EVENTOUT; additional functions ADC1_IN4, COMP2_INP, OPAMP1_VINM/OPAMP1_VINP, OPAMP5_VINM. |
| 33 | PA4 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM3_CH2, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, SAI1_FS_B, EVENTOUT; additional functions ADC2_IN17, DAC1_OUT1, COMP1_INM. |
| 34 | PA5 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM2_CH1, TIM2_ETR, SPI1_SCK, UCPD1_FRSTX, EVENTOUT; additional functions ADC2_IN13, DAC1_OUT2, COMP2_INM, OPAMP2_VINM. |
| 35 | PA6 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, COMP1_OUT, QUADSPI1_BK1_IO3, LPUART1_CTS, EVENTOUT; additional functions ADC2_IN3, DAC2_OUT1, OPAMP2_VOUT. |
| 36 | PA7 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM17_CH1, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, COMP2_OUT, QUADSPI1_BK1_IO2, UCPD1_FRSTX, EVENTOUT; additional functions ADC2_IN4, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP. |
| 37 | PC4 | bidirectional | 5 V tolerant Fm+ capable I/O with analog switch (FT_fa); alternate functions TIM1_ETR, I2C2_SCL, USART1_TX, QUADSPI1_BK2_IO3, EVENTOUT; additional function ADC2_IN5. |
| 38 | PC5 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM15_BKIN, SAI1_D3, TIM1_CH4N, USART1_RX, HRTIM1_EEV10, EVENTOUT; additional functions ADC2_IN11, OPAMP1_VINM, OPAMP2_VINM, WKUP5. |
| 39 | PB0 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM3_CH3, TIM8_CH2N, TIM1_CH2N, QUADSPI1_BK1_IO1, HRTIM1_FLT5, UCPD1_FRSTX, EVENTOUT; additional functions ADC3_IN12/ADC1_IN15, COMP4_INP, OPAMP2_VINP, OPAMP3_VINP. |
| 40 | PB1 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM3_CH4, TIM8_CH3N, TIM1_CH3N, COMP4_OUT, QUADSPI1_BK1_IO0, LPUART1_RTS_DE, HRTIM1_SCOUT, EVENTOUT; additional functions ADC3_IN1/ADC1_IN12, COMP1_INP, OPAMP3_VOUT, OPAMP6_VINM. |
| 41 | PB2 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions RTC_OUT2, LPTIM1_OUT, TIM5_CH1, TIM20_CH1, I2C3_SMBA, QUADSPI1_BK2_IO1, HRTIM1_SCIN, EVENTOUT; additional functions ADC2_IN12, COMP4_INM, OPAMP3_VINM. |
| 42 | VSSA | power_in | Analog ground pin; all ground pins (VSS, VSSA) must be connected and variation between ground pins is limited to 50 mV. |
| 43 | VREF+ | power_in | Positive reference voltage pin for ADC/DAC; VREF+ may exceed VDDA by no more than 0.4 V; additional function VREFBUF_OUT. |
| 44 | VREF+ | power_in | Second positive reference voltage pin for ADC/DAC (paired with pin 43); VREF+ may exceed VDDA by no more than 0.4 V; additional function VREFBUF_OUT. |
| 45 | VDDA | power_in | Analog supply: 1.62 V minimum for ADC, 1.8 V minimum for DAC, OPAMP and COMP, 2.4 V minimum when VREFBUF is used, 3.6 V maximum. |
| 46 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 47 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
| 48 | PF11 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_ETR, FMC_NE4, EVENTOUT. |
| 49 | PF12 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_CH1, FMC_A6, EVENTOUT. |
| 50 | PF13 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_CH2, I2C4_SMBA, FMC_A7, EVENTOUT. |
| 51 | PF14 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM20_CH3, I2C4_SCL, FMC_A8, EVENTOUT. |
| 52 | PF15 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM20_CH4, I2C4_SDA, FMC_A9, EVENTOUT. |
| 53 | PE7 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM1_ETR, FMC_D4, SAI1_SD_B, EVENTOUT; additional functions ADC3_IN4, COMP4_INP. |
| 54 | PE8 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM5_CH3, TIM1_CH1N, FMC_D5, SAI1_SCK_B, EVENTOUT; additional functions ADC345_IN6, COMP4_INM. |
| 55 | PE9 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM5_CH4, TIM1_CH1, FMC_D6, SAI1_FS_B, EVENTOUT; additional function ADC3_IN2. |
| 56 | PE10 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM1_CH2N, QUADSPI1_CLK, FMC_D7, SAI1_MCLK_B, EVENTOUT; additional function ADC345_IN14. |
| 57 | PE11 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM1_CH2, SPI4_NSS, QUADSPI1_BK1_NCS, FMC_D8, EVENTOUT; additional function ADC345_IN15. |
| 58 | PE12 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM1_CH3N, SPI4_SCK, QUADSPI1_BK1_IO0, FMC_D9, EVENTOUT; additional function ADC345_IN16. |
| 59 | PE13 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM1_CH3, SPI4_MISO, QUADSPI1_BK1_IO1, FMC_D10, EVENTOUT; additional function ADC3_IN3. |
| 60 | PE14 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM1_CH4, SPI4_MOSI, TIM1_BKIN2, QUADSPI1_BK1_IO2, FMC_D11, EVENTOUT; additional function ADC4_IN1. |
| 61 | PE15 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM1_BKIN, TIM1_CH4N, USART3_RX, QUADSPI1_BK1_IO3, FMC_D12, EVENTOUT; additional function ADC4_IN2. |
| 62 | PB10 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM2_CH3, USART3_TX, LPUART1_RX, QUADSPI1_CLK, TIM1_BKIN, HRTIM1_FLT3, SAI1_SCK_A, EVENTOUT; additional functions COMP5_INM, OPAMP3_VINM, OPAMP4_VINM. |
| 63 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 64 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
| 65 | PB11 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM2_CH4, USART3_RX, LPUART1_TX, QUADSPI1_BK1_NCS, HRTIM1_FLT4, EVENTOUT; additional functions ADC12_IN14, COMP6_INP, OPAMP4_VINP, OPAMP6_VOUT. |
| 66 | PB12 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM5_ETR, I2C2_SMBA, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK, LPUART1_RTS_DE, FDCAN2_RX, HRTIM1_CHC1, EVENTOUT; additional functions ADC4_IN3/ADC1_IN11, COMP7_INM, OPAMP4_VOUT, OPAMP6_VINP. |
| 67 | PB13 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS, LPUART1_CTS, FDCAN2_TX, HRTIM1_CHC2, EVENTOUT; additional functions ADC3_IN5, COMP5_INP, OPAMP3_VINP, OPAMP4_VINP, OPAMP6_VINP. |
| 68 | PB14 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM15_CH1, SPI2_MISO, TIM1_CH2N, USART3_RTS_DE, COMP4_OUT, HRTIM1_CHD1, EVENTOUT; additional functions ADC4_IN4/ADC1_IN5, COMP7_INP, OPAMP2_VINP, OPAMP5_VINP. |
| 69 | PB15 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions RTC_REFIN, TIM15_CH2, TIM15_CH1N, COMP3_OUT, TIM1_CH3N, SPI2_MOSI/I2S2_SD, HRTIM1_CHD2, EVENTOUT; additional functions ADC4_IN5/ADC2_IN15, COMP6_INM, OPAMP5_VINM. |
| 70 | PD8 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions USART3_TX, FMC_D13, EVENTOUT; additional functions ADC4_IN12/ADC5_IN12, OPAMP4_VINM. |
| 71 | PD9 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions USART3_RX, FMC_D14, EVENTOUT; additional functions ADC4_IN13/ADC5_IN13, OPAMP6_VINP. |
| 72 | PD10 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions USART3_CK, FMC_D15, EVENTOUT; additional functions ADC345_IN7, COMP6_INM. |
| 73 | PD11 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM5_ETR, I2C4_SMBA, USART3_CTS, FMC_A16, EVENTOUT; additional functions ADC345_IN8, COMP6_INP, OPAMP4_VINP. |
| 74 | PD12 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM4_CH1, USART3_RTS_DE, FMC_A17, EVENTOUT; additional functions ADC345_IN9, COMP5_INP, OPAMP5_VINP. |
| 75 | PD13 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM4_CH2, FMC_A18, EVENTOUT; additional functions ADC345_IN10, COMP5_INM. |
| 76 | PD14 | bidirectional | 3.6 V tolerant I/O with analog switch (TT_a); alternate functions TIM4_CH3, FMC_D0, EVENTOUT; additional functions ADC345_IN11, COMP7_INP, OPAMP2_VINP. |
| 77 | PD15 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions TIM4_CH4, SPI2_NSS, FMC_D1, EVENTOUT; additional function COMP7_INM. |
| 78 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 79 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
| 80 | PC6 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM3_CH1, HRTIM1_EEV10, TIM8_CH1, I2S2_MCK, COMP6_OUT, I2C4_SCL, HRTIM1_CHF1, EVENTOUT. |
| 81 | PC7 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM3_CH2, HRTIM1_FLT5, TIM8_CH2, I2S3_MCK, COMP5_OUT, I2C4_SDA, HRTIM1_CHF2, EVENTOUT. |
| 82 | PG0 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_CH1N, FMC_A10, EVENTOUT. |
| 83 | PG1 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_CH2N, FMC_A11, EVENTOUT. |
| 84 | PG2 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_CH3N, SPI1_SCK, FMC_A12, EVENTOUT. |
| 85 | PG3 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM20_BKIN, I2C4_SCL, SPI1_MISO, TIM20_CH4N, FMC_A13, EVENTOUT. |
| 86 | PG4 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM20_BKIN2, I2C4_SDA, SPI1_MOSI, FMC_A14, EVENTOUT. |
| 87 | PC8 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM3_CH3, HRTIM1_CHE1, TIM8_CH3, TIM20_CH3, COMP7_OUT, I2C3_SCL, EVENTOUT. |
| 88 | PC9 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM3_CH4, HRTIM1_CHE2, TIM8_CH4, I2SCKIN, TIM8_BKIN2, I2C3_SDA, EVENTOUT. |
| 89 | PA8 | bidirectional | 5 V tolerant I/O with analog switch (FT_a); alternate functions MCO, I2C3_SCL, I2C2_SDA, I2S2_MCK, TIM1_CH1, USART1_CK, COMP7_OUT, TIM4_ETR, FDCAN3_RX, SAI1_CK2, HRTIM1_CHA1, SAI1_SCK_A, EVENTOUT; additional functions ADC5_IN1, OPAMP5_VOUT. |
| 90 | PA9 | bidirectional | 5 V tolerant Fm+ capable I/O with analog switch and USB Type-C dead-battery function (FT_fda); alternate functions I2C3_SMBA, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, COMP5_OUT, TIM15_BKIN, TIM2_CH3, HRTIM1_CHA2, SAI1_FS_A, EVENTOUT; additional functions ADC5_IN2, UCPD1_DBCC1. |
| 91 | PA10 | bidirectional | 5 V tolerant Fm+ capable I/O with analog switch and USB Type-C dead-battery function (FT_fda); alternate functions TIM17_BKIN, USB_CRS_SYNC, I2C2_SMBA, SPI2_MISO, TIM1_CH3, USART1_RX, COMP6_OUT, TIM2_CH4, TIM8_BKIN, SAI1_D1, HRTIM1_CHB1, SAI1_SD_A, EVENTOUT; additional function UCPD1_DBCC2. |
| 92 | PA11 | bidirectional | 5 V tolerant I/O with USB function (FT_u); alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT, FDCAN1_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2, HRTIM1_CHB2, EVENTOUT; additional function USB_DM. |
| 93 | PA12 | bidirectional | 5 V tolerant I/O with USB function (FT_u); alternate functions TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX, TIM4_CH2, TIM1_ETR, HRTIM1_FLT1, EVENTOUT; additional function USB_DP. |
| 94 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 95 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
| 96 | PA13 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); after reset it is configured as the SWDIO/JTMS debug function with internal pull-up enabled; alternate functions SWDIO-JTMS, TIM16_CH1N, I2C4_SCL, I2C1_SCL, IR_OUT, USART3_CTS, TIM4_CH3, SAI1_SD_B, EVENTOUT. |
| 97 | PF6 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM5_ETR, TIM4_CH4, SAI1_SD_B, I2C2_SCL, TIM5_CH1, USART3_RTS, QUADSPI1_BK1_IO3, EVENTOUT. |
| 98 | PA14 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); after reset it is configured as the SWCLK/JTCK debug function with internal pull-down enabled; alternate functions SWCLK-JTCK, LPTIM1_OUT, I2C4_SMBA, I2C1_SDA, TIM8_CH2, TIM1_BKIN, USART2_TX, SAI1_FS_B, EVENTOUT. |
| 99 | PA15 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); after reset it is configured as the JTDI debug function with internal pull-up enabled; alternate functions JTDI, TIM2_CH1, TIM8_CH1, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, UART4_RTS_DE, TIM1_BKIN, FDCAN3_TX, HRTIM1_FLT2, TIM2_ETR, EVENTOUT. |
| 100 | PC10 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM8_CH1N, UART4_TX, SPI3_SCK/I2S3_CK, USART3_TX, HRTIM1_FLT6, EVENTOUT. |
| 101 | PC11 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions HRTIM1_EEV2, TIM8_CH2N, UART4_RX, SPI3_MISO, USART3_RX, I2C3_SDA, EVENTOUT. |
| 102 | PC12 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM5_CH2, HRTIM1_EEV1, TIM8_CH3N, UART5_TX, SPI3_MOSI/I2S3_SD, USART3_CK, UCPD1_FRSTX, EVENTOUT. |
| 103 | PG5 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_ETR, SPI1_NSS, LPUART1_CTS, FMC_A15, EVENTOUT. |
| 104 | PG6 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM20_BKIN, I2C3_SMBA, LPUART1_RTS_DE, FMC_INT, EVENTOUT. |
| 105 | PG7 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions SAI1_CK1, I2C3_SCL, LPUART1_TX, FMC_INT, SAI1_MCLK_A, EVENTOUT. |
| 106 | PG8 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions I2C3_SDA, LPUART1_RX, FMC_NE3, EVENTOUT. |
| 107 | PG9 | bidirectional | 5 V tolerant I/O (FT); alternate functions SPI3_SCK, USART1_TX, FMC_NCE/FMC_NE2, TIM15_CH1N, EVENTOUT. |
| 108 | PD0 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM8_CH4N, FDCAN1_RX, FMC_D2, EVENTOUT. |
| 109 | PD1 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM8_CH4, TIM8_BKIN2, FDCAN1_TX, FMC_D3, EVENTOUT. |
| 110 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 111 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
| 112 | PD2 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM3_ETR, TIM8_BKIN, UART5_RX, EVENTOUT. |
| 113 | PD3 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM2_CH1/TIM2_ETR, USART2_CTS, QUADSPI1_BK2_NCS, FMC_CLK, EVENTOUT. |
| 114 | PD4 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM2_CH2, USART2_RTS_DE, QUADSPI1_BK2_IO0, FMC_NOE, EVENTOUT. |
| 115 | PD5 | bidirectional | 5 V tolerant I/O (FT); alternate functions USART2_TX, QUADSPI1_BK2_IO1, FMC_NWE, EVENTOUT. |
| 116 | PD6 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM2_CH4, SAI1_D1, USART2_RX, QUADSPI1_BK2_IO2, FMC_NWAIT, SAI1_SD_A, EVENTOUT. |
| 117 | PD7 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM2_CH3, USART2_CK, QUADSPI1_BK2_IO3, FMC_NCE/FMC_NE1, EVENTOUT. |
| 118 | PB3 | bidirectional | 5 V tolerant I/O (FT); after reset it is configured as the JTDO/TRACESWO debug function with internal pull-up/pull-down per note 4; alternate functions JTDO-TRACESWO, TIM2_CH2, TIM4_ETR, UCPD1_CRS_SYNC, TIM8_CH1N, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR, FDCAN3_RX, HRTIM1_SCOUT, HRTIM1_EEV9, SAI1_SCK_B, EVENTOUT. |
| 119 | PB4 | bidirectional | 5 V tolerant Fm+/USB Type-C capable I/O (FT_c); after reset it is configured as the JTRST debug function with internal pull-up enabled and a UCPD CC pull-down (5.1 kΩ) that can be disabled via UCPD1_DBDIS; alternate functions JTRST, TIM16_CH1, TIM3_CH1, TIM8_CH2N, SPI1_MISO, SPI3_MISO, USART2_RX, UART5_RTS_DE, TIM17_BKIN, FDCAN3_TX, HRTIM1_EEV7, SAI1_MCLK_B, EVENTOUT; UCPD1_CC2. |
| 120 | PB5 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM16_BKIN, TIM3_CH2, TIM8_CH3N, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, FDCAN2_RX, TIM17_CH1, LPTIM1_IN1, SAI1_SD_B, HRTIM1_EEV6, UART5_CTS, EVENTOUT. |
| 121 | PB6 | bidirectional | 5 V tolerant USB Type-C capable I/O (FT_c); after reset a 5.1 kΩ UCPD pull-down can be activated, enabled by high level on PA9; alternate functions TIM16_CH1N, TIM4_CH1, TIM8_CH1, TIM8_ETR, USART1_TX, COMP4_OUT, FDCAN2_TX, TIM8_BKIN2, LPTIM1_ETR, HRTIM1_SCIN, HRTIM1_EEV4, SAI1_FS_B, EVENTOUT; UCPD1_CC1. |
| 122 | PB7 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM17_CH1N, TIM4_CH2, I2C4_SDA, I2C1_SDA, TIM8_BKIN, USART1_RX, COMP3_OUT, TIM3_CH4, LPTIM1_IN2, FMC_NL, HRTIM1_EEV3, UART4_CTS, EVENTOUT; additional function PVD_IN. |
| 123 | PB8-BOOT0 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f) that also serves as the BOOT0 pin; alternate functions TIM16_CH1, TIM4_CH3, SAI1_CK1, I2C1_SCL, USART3_RX, COMP1_OUT, FDCAN1_RX, TIM8_CH2, TIM1_BKIN, HRTIM1_EEV8, SAI1_MCLK_A, EVENTOUT; set to a mode other than analog after startup to limit consumption if left unconnected. |
| 124 | PB9 | bidirectional | 5 V tolerant Fm+ capable I/O (FT_f); alternate functions TIM17_CH1, TIM4_CH4, SAI1_D2, I2C1_SDA, IR_OUT, USART3_TX, COMP2_OUT, FDCAN1_TX, TIM8_CH3, TIM1_CH3N, HRTIM1_EEV5, SAI1_FS_A, EVENTOUT. |
| 125 | PE0 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM4_ETR, TIM20_CH4N, TIM16_CH1, TIM20_ETR, USART1_TX, FMC_NBL0, EVENTOUT. |
| 126 | PE1 | bidirectional | 5 V tolerant I/O (FT); alternate functions TIM17_CH1, TIM20_CH4, USART1_RX, FMC_NBL1, EVENTOUT. |
| 127 | VSS | power_in | Ground pin; all VSS pins must be connected to the external ground and variation between ground pins is limited to 50 mV. |
| 128 | VDD | power_in | Digital supply pin; standard operating voltage is 1.71 V to 3.6 V and variation between VDD pins is limited to 50 mV. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-128(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 128 |
CAD (KiCad official)
- Symbol:
STM32G474QET3 - Footprint:
Package_QFP:LQFP-128_14x14mm_P0.4mm - 3D model: LQFP-128(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32g474qet3-etched.step/stm32g474qet3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32g474qet3.step/stm32g474qet3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (236 pp, sha256
e2e6db47d49faed3, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).