# STM32G474CCU6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32G474CCU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply for the RTC and backup registers, specified from 1.55 V to 3.6 V. |
| 2 | PC13 | bidirectional | FT GPIO on the backup domain, but its power switch sinks only 3 mA, so output use is limited to 2 MHz at 30 pF and it must not source LEDs; also TIM1_BKIN, RTC_TAMP1, RTC_TS and RTC_OUT1. |
| 3 | PC14-OSC32_IN | bidirectional | FT GPIO on the backup domain with the same 3 mA power-switch limit, also serving as the LSE oscillator input OSC32_IN. |
| 4 | PC15-OSC32_OUT | bidirectional | FT GPIO on the backup domain with the same 3 mA power-switch limit, also serving as the LSE oscillator output OSC32_OUT. |
| 5 | PF0-OSC_IN | bidirectional | 5 V tolerant FT_fa I/O that also serves as HSE oscillator input OSC_IN, with ADC1_IN10, I2C2_SDA and SPI2_NSS/I2S2_WS. |
| 6 | PF1-OSC_OUT | bidirectional | 3.6 V tolerant FT_a I/O that also serves as HSE oscillator output OSC_OUT, with ADC2_IN10, COMP3_INM and SPI2_SCK/I2S2_CK. |
| 7 | PG10-NRST | bidirectional | Bidirectional reset pin with an embedded weak pull-up resistor, also usable as an FT I/O with MCO output. |
| 8 | PA0 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC12_IN1, COMP1_INM, TIM2_CH1, USART2_CTS and WKUP1. |
| 9 | PA1 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC12_IN2, COMP1_INP, OPAMP1_VINP, TIM2_CH2 and RTC_REFIN. |
| 10 | PA2 | bidirectional | 5 V tolerant FT_a I/O with analog switch supplied by VDDA, also ADC1_IN3, COMP2_INM, OPAMP1_VOUT, USART2_TX and WKUP4/LSCO. |
| 11 | PA3 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC1_IN4, COMP2_INP, OPAMP1_VINM/OPAMP1_VINP, USART2_RX and LPUART1_RX. |
| 12 | PA4 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC2_IN17, DAC1_OUT1, COMP1_INM, SPI1_NSS and USART2_CK. |
| 13 | PA5 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC2_IN13, DAC1_OUT2, COMP2_INM, OPAMP2_VINM and SPI1_SCK. |
| 14 | PA6 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC2_IN3, DAC2_OUT1, OPAMP2_VOUT, SPI1_MISO and COMP1_OUT. |
| 15 | PA7 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC2_IN4, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP and SPI1_MOSI. |
| 16 | PC4 | bidirectional | 5 V tolerant FT_fa I/O with Fm+ capability and analog switch supplied by VDDA, also ADC2_IN5, I2C2_SCL, USART1_TX and TIM1_ETR. |
| 17 | PB0 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC3_IN12/ADC1_IN15, COMP4_INP, OPAMP2_VINP, OPAMP3_VINP and TIM3_CH3. |
| 18 | PB1 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC3_IN1/ADC1_IN12, COMP1_INP, OPAMP3_VOUT, OPAMP6_VINM and TIM3_CH4. |
| 19 | PB2 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC2_IN12, COMP4_INM, OPAMP3_VINM, RTC_OUT2 and LPTIM1_OUT. |
| 20 | VREF+ | power_in | Positive reference voltage for the ADCs and DACs, which can be connected internally to VDDA depending on the package, and which also provides the VREFBUF_OUT function. |
| 21 | VDDA | power_in | Analog supply: 1.62 V minimum for the ADC, 1.8 V minimum for DAC (1 MSPS or 15 MSPS), OPAMP and COMP, 2.4 V minimum when VREFBUF is used, up to 3.6 V. |
| 22 | PB10 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also TIM2_CH3, USART3_TX, LPUART1_RX, QUADSPI1_CLK, COMP5_INM and OPAMP3_VINM. |
| 23 | VDD | power_in | Standard operating supply voltage, 1.71 V to 3.6 V. |
| 24 | PB11 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC12_IN14, COMP6_INP, OPAMP4_VINP, USART3_RX and LPUART1_TX. |
| 25 | PB12 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC4_IN3/ADC1_IN11, COMP7_INM, OPAMP4_VOUT, SPI2_NSS/I2S2_WS, TIM1_BKIN and USART3_CK. |
| 26 | PB13 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC3_IN5, COMP5_INP, OPAMP3_VINP, SPI2_SCK/I2S2_CK, TIM1_CH1N and USART3_CTS. |
| 27 | PB14 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC4_IN4/ADC1_IN5, COMP7_INP, OPAMP2_VINP, TIM15_CH1, SPI2_MISO and COMP4_OUT. |
| 28 | PB15 | bidirectional | 3.6 V tolerant TT_a I/O with analog switch supplied by VDDA, also ADC4_IN5/ADC2_IN15, COMP6_INM, OPAMP5_VINM, RTC_REFIN and SPI2_MOSI/I2S2_SD. |
| 29 | PC6 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability, also TIM3_CH1, TIM8_CH1, I2S2_MCK, COMP6_OUT and I2C4_SCL. |
| 30 | PA8 | bidirectional | 5 V tolerant FT_a I/O, also MCO output, TIM1_CH1, USART1_CK, I2C3_SCL, I2C2_SDA, ADC5_IN1 and OPAMP5_VOUT. |
| 31 | PA9 | bidirectional | 5 V tolerant FT_fda I/O with Fm+ capability and dead-battery function, also TIM1_CH2, USART1_TX, I2C2_SCL, ADC5_IN2 and UCPD1_DBCC1. |
| 32 | PA10 | bidirectional | 5 V tolerant FT_fda I/O with Fm+ capability and dead-battery function, also TIM1_CH3, USART1_RX, SPI2_MISO, USB_CRS_SYNC and UCPD1_DBCC2. |
| 33 | PA11 | bidirectional | 5 V tolerant FT_u I/O with USB function, also USB_DM, TIM1_CH1N, USART1_CTS, FDCAN1_RX and COMP1_OUT. |
| 34 | PA12 | bidirectional | 5 V tolerant FT_u I/O with USB function, also USB_DP, TIM16_CH1, USART1_RTS_DE, FDCAN1_TX and TIM1_ETR. |
| 35 | VDD | power_in | Standard operating supply voltage, 1.71 V to 3.6 V. |
| 36 | PA13 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability; after reset it is the SWDIO-JTMS debug function with an internal pull-up active, also IR_OUT, I2C1_SCL and USART3_CTS. |
| 37 | PA14 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability; after reset it is the SWCLK-JTCK debug function with an internal pull-down active, also LPTIM1_OUT, I2C1_SDA and USART2_TX. |
| 38 | PA15 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability; after reset it is the JTDI debug function with an internal pull-up active, also TIM2_CH1, SPI1_NSS, USART2_RX and FDCAN3_TX. |
| 39 | PC10 | bidirectional | 5 V tolerant FT I/O, also UART4_TX, SPI3_SCK/I2S3_CK, USART3_TX, TIM8_CH1N and HRTIM1_FLT6. |
| 40 | PC11 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability, also UART4_RX, SPI3_MISO, USART3_RX, I2C3_SDA and HRTIM1_EEV2. |
| 41 | PB3 | bidirectional | 5 V tolerant FT I/O; after reset it is the JTDO-TRACESWO debug function, also TIM2_CH2, SPI1_SCK, SPI3_SCK/I2S3_CK and USART2_TX. |
| 42 | PB4 | bidirectional | 5 V tolerant FT_c I/O, USB Type-C PD capable; after reset it is the JTRST debug function with an internal pull-up active, and its UCPD1_CC2 pull-down (5.1 kOhm) can be enabled, also TIM16_CH1, SPI1_MISO and USART2_RX. |
| 43 | PB5 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability, also TIM16_BKIN, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK and FDCAN2_RX. |
| 44 | PB6 | bidirectional | 5 V tolerant FT_c I/O, USB Type-C PD capable; after reset its UCPD1_CC1 pull-down (5.1 kOhm) can be activated by a high level on PA9, also TIM16_CH1N, TIM4_CH1, USART1_TX and FDCAN2_TX. |
| 45 | PB7 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability, also TIM17_CH1N, TIM4_CH2, I2C4_SDA, I2C1_SDA, USART1_RX, COMP3_OUT and PVD_IN. |
| 46 | PB8-BOOT0 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability that is also the dedicated BOOT0 pin; it is recommended to set it out of analog mode after startup to limit consumption if left unconnected, also TIM16_CH1, I2C1_SCL and USART3_RX. |
| 47 | PB9 | bidirectional | 5 V tolerant FT_f I/O with Fm+ capability, also TIM17_CH1, TIM4_CH4, SAI1_D2, I2C1_SDA, IR_OUT, USART3_TX and FDCAN1_TX. |
| 48 | VDD | power_in | Standard operating supply voltage, 1.71 V to 3.6 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage (VDD, VDDA, VBAT, VREF+) | VDD - VSS | -0.3 |  | 4 | V | Including VDD, VDDA, VBAT and VREF+ | 82 |
| Allowed voltage difference for VREF+ > VDDA | VREF+-VDDA |  |  | 0.4 | V | Allowed voltage difference for VREF+ > VDDA | 82 |
| Variations between VDDx power pins of the same domain | /∆VDDx/ |  |  | 50 | mV | Variations between different VDDX power pins of the same domain | 82 |
| Variations between all ground pins | /VSSx-VSS/ |  |  | 50 | mV | Variations between all the different ground pins, include VREF- pin | 82 |
| Total current into sum of all VDD power lines (source) | ∑IVDD |  |  | 150 | mA | Total current into sum of all VDD power lines (source) | 83 |
| Total current out of sum of all VSS ground lines (sink) | ∑IVSS |  |  | 150 | mA | Total current out of sum of all VSS ground lines (sink) | 83 |
| Maximum current into each VDD power pin (source) | IVDD(PIN) |  |  | 100 | mA | Maximum current into each VDD power pin (source) | 83 |
| Maximum current out of each VSS ground pin (sink) | IVSS(PIN) |  |  | 100 | mA | Maximum current out of each VSS ground pin (sink) | 83 |
| Output current sunk by any I/O and control pin except FT_f | IIO(PIN) |  |  | 20 | mA | Output current sunk by any I/O and control pin except FT_f | 83 |
| Output current sunk by any FT_f pin | IIO(PIN) |  |  | 20 | mA | Output current sunk by any FT_f pin | 83 |
| Output current sourced by any I/O and control pin | IIO(PIN) |  |  | 20 | mA | Output current sourced by any I/O and control pin | 83 |
| Total output current sunk by sum of all I/Os and control pins | ∑IIO(PIN) |  |  | 100 | mA | Total output current sunk by sum of all I/Os and control pins | 83 |
| Total output current sourced by sum of all I/Os and control pins | ∑IIO(PIN) |  |  | 100 | mA | Total output current sourced by sum of all I/Os and control pins | 83 |
| Injected current on FT_xxx, TT_xx, NRST pins | IINJ(PIN) | -5 |  | 0 | mA | Injected current on FT_xxx, TT_xx, NRST pins | 83 |
| Total injected current (sum of all I/Os and control pins) | ∑/IINJ(PIN)/ |  |  | 25 | mA | Sum of all I/Os and control pins | 83 |
| Storage temperature range | TSTG | -65 |  | 150 | °C | Storage temperature range | 83 |
| Maximum junction temperature | TJ |  |  | 150 | °C | Maximum junction temperature | 83 |
| Internal AHB clock frequency | fHCLK | 0 |  | 170 | MHz |  | 84 |
| Internal APB1 clock frequency | fPCLK1 | 0 |  | 170 | MHz |  | 84 |
| Internal APB2 clock frequency | fPCLK2 | 0 |  | 170 | MHz |  | 84 |
| Standard operating voltage | VDD | 1.71 |  | 3.6 | V |  | 84 |
| Analog supply voltage for ADC | VDDA | 1.62 |  | 3.6 | V | ADC | 84 |
| Analog supply voltage for DAC and OPAMP | VDDA | 1.8 |  | 3.6 | V | DAC 1 MSPS or DAC 15 MSPS or OPAMP | 84 |
| Analog supply voltage when COMP used | VDDA | 1.8 |  | 3.6 | V | COMP used | 84 |
| Analog supply voltage when VREFBUF used | VDDA | 2.4 |  | 3.6 | V | VREFBUF used | 84 |
| Analog supply voltage when ADC, DAC, OPAMP, COMP, VREFBUF not used | VDDA | 0 |  | 3.6 | V | ADC, DAC, OPAMP, COMP, VREFBUF not used | 84 |
| Backup operating voltage | VBAT | 1.55 |  | 3.6 | V |  | 84 |
| Ambient temperature suffix 6 version, maximum power dissipation | TA | -40 |  | 85 | °C | Ambient temperature for the suffix 6 version, maximum power dissipation | 84 |
| Ambient temperature suffix 6 version, low-power dissipation | TA | -40 |  | 105 | °C | Ambient temperature for the suffix 6 version, low-power dissipation | 84 |
| Junction temperature range suffix 6 version | TJ | -40 |  | 105 | °C | Suffix 6 version | 84 |
| Internal reference voltage | VREFINT | 1.182 | 1.212 | 1.232 | V | -40 °C < TA < +130 °C | 88 |
| Average temperature coefficient | TCoeff |  | 30 | 50 | ppm/°C | -40°C < TA < +130°C | 88 |
| Average voltage coefficient | VDDCoeff |  | 250 | 1200 | ppm/V | 3.0 V < VDD < 3.6 V | 88 |
| Brown-out reset threshold 0 rising edge | VBOR0 | 1.62 | 1.66 | 1.7 | V | Rising edge | 86 |
| Brown-out reset threshold 0 falling edge | VBOR0 | 1.6 | 1.64 | 1.69 | V | Falling edge | 86 |
| Reset temporization after BOR0 is detected | tRSTTEMPO |  | 250 | 400 | μs | VDD rising | 86 |

## CAD (KiCad official)

- Symbol: `STM32G474CCU6`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm32g474ccu6-etched.step` / `stm32g474ccu6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32g474ccu6.step` / `stm32g474ccu6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm32g474ccu6.pdf) (236 pp, sha256 `e2e6db47d49faed3`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32g474ccu6-datasheet.pdf)