STM32G441VBT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	5 V tolerant (FT) I/O; alternate functions include TRACECK, TIM3_CH1, SAI1_CK1 and SAI1_MCLK_A.
2	PE3	bidirectional	5 V tolerant (FT) I/O; alternate functions include TRACED0, TIM3_CH2 and SAI1_SD_B.
3	PE4	bidirectional	5 V tolerant (FT) I/O; alternate functions include TRACED1, TIM3_CH3, SAI1_D2 and SAI1_FS_A.
4	PE5	bidirectional	5 V tolerant (FT) I/O; alternate functions include TRACED2, TIM3_CH4, SAI1_CK2 and SAI1_SCK_A.
5	PE6	bidirectional	5 V tolerant (FT) I/O; alternate functions include TRACED3, SAI1_D1 and SAI1_SD_A; additional functions WKUP3 and RTC_TAMP3.
6	VBAT	power_in	Backup domain supply, 1.55 V to 3.6 V.
7	PC13	bidirectional	5 V tolerant I/O supplied through the power switch, which sinks at most 3 mA; output speed is limited to 2 MHz at 30 pF and it must not drive LEDs as a current source.
8	PC14-OSC32_IN	bidirectional	I/O supplied through the power switch (3 mA limit, output limited to 2 MHz at 30 pF); also the LSE oscillator input OSC32_IN.
9	PC15-OSC32_OUT	bidirectional	I/O supplied through the power switch (3 mA limit, output limited to 2 MHz at 30 pF); also the LSE oscillator output OSC32_OUT.
10	PF9	bidirectional	5 V tolerant I/O; alternate functions TIM15_CH1, SPI2_SCK and SAI1_FS_B.
11	PF10	bidirectional	5 V tolerant I/O; alternate functions TIM15_CH2, SPI2_SCK and SAI1_D3.
12	PF0-OSC_IN	input	FT_f input; OSC_IN high-speed oscillator input; alternate functions I2C2_SDA, SPI2_NSS/I2S2_WS and TIM1_CH3N; ADC1_IN10.
13	PF1-OSC_OUT	output	FT output; OSC_OUT high-speed oscillator output; alternate function SPI2_SCK/I2S2_CK; ADC2_IN10 and COMP3_INM.
14	PG10-NRST	bidirectional	Bidirectional reset pin with embedded weak pull-up resistor; alternate function MCO.
15	PC0	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate functions LPTIM1_IN1, TIM1_CH1 and LPUART1_RX; ADC12_IN6 and COMP3_INM.
16	PC1	bidirectional	TT I/O (3.6 V tolerant); alternate functions LPTIM1_OUT, TIM1_CH2, LPUART1_TX and SAI1_SD_A; ADC12_IN7 and COMP3_INP.
17	PC2	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate functions LPTIM1_IN2, TIM1_CH3 and COMP3_OUT; ADC12_IN8.
18	PC3	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate functions LPTIM1_ETR, TIM1_CH4, SAI1_D1 and TIM1_BKIN2; ADC12_IN9.
19	PF2	bidirectional	5 V tolerant I/O; alternate function I2C2_SMBA.
20	PA0	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM2_CH1, USART2_CTS, COMP1_OUT and TIM8_BKIN; ADC12_IN1, COMP1_INM, COMP3_INP, RTC_TAMP2 and WKUP1.
21	PA1	bidirectional	TT I/O (3.6 V tolerant); alternate functions RTC_REFIN, TIM2_CH2, USART2_RTS_DE and TIM15_CH1N; ADC12_IN2, COMP1_INP, OPAMP1_VINP and OPAMP3_VINP.
22	PA2	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM2_CH3, USART2_TX, COMP2_OUT, TIM15_CH1, LPUART1_TX and UCPD1_FRSTX; ADC1_IN3, COMP2_INM, OPAMP1_VOUT and WKUP4/LSCO.
23	VSS_2	power_in	Ground pin for the second VSS domain.
24	VDD_2	power_in	Supply pin; VDD standard operating range 1.71 V to 3.6 V.
25	PA3	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM2_CH4, SAI1_CK1, USART2_RX, TIM15_CH2, LPUART1_RX and SAI1_MCLK_A; ADC1_IN4 and COMP2_INP.
26	PA4	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM3_CH2, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK and SAI1_FS_B; ADC2_IN17, DAC1_OUT1 and COMP1_INM.
27	PA5	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM2_CH1, TIM2_ETR, SPI1_SCK and UCPD1_FRSTX; ADC2_IN13, DAC1_OUT2 and COMP2_INM.
28	PA6	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, COMP1_OUT and LPUART1_CTS; ADC2_IN3 and OPAMP2_VOUT.
29	PA7	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM17_CH1, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, COMP2_OUT and UCPD1_FRSTX; ADC2_IN4, COMP2_INP, OPAMP1_VINP and OPAMP2_VINP.
30	PC4	bidirectional	FT_fa I/O; alternate functions TIM1_ETR, I2C2_SCL and USART1_TX; ADC2_IN5.
31	PC5	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM15_BKIN, SAI1_D3, TIM1_CH4N and USART1_RX; ADC2_IN11, OPAMP1_VINM, OPAMP2_VINM and WKUP5.
32	PB0	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM3_CH3, TIM8_CH2N, TIM1_CH2N and UCPD1_FRSTX; ADC1_IN15, COMP4_INP, OPAMP2_VINP and OPAMP3_VINP.
33	PB1	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM3_CH4, TIM8_CH3N, TIM1_CH3N, COMP4_OUT and LPUART1_RTS_DE; ADC1_IN12, COMP1_INP and OPAMP3_VOUT.
34	PB2	bidirectional	TT I/O (3.6 V tolerant); alternate functions RTC_OUT2, LPTIM1_OUT and I2C3_SMBA; ADC2_IN12, COMP4_INM and OPAMP3_VINM.
35	VSSA	power_in	Analog ground reference.
36	VREF+	power_in	Positive reference voltage for the ADC and DAC; can be internally connected to the VREFBUF_OUT output.
37	VDDA	power_in	Analog supply; minimum 1.62 V when ADC or COMP is used, 1.71 V for DAC, 2.0 V for OPAMP and 2.4 V when VREFBUF is used, maximum 3.6 V.
38	PE7	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM1_ETR and SAI1_SD_B; COMP4_INP.
39	PE8	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate functions TIM1_CH1N and SAI1_SCK_B; COMP4_INM.
40	PE9	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM1_CH1 and SAI1_FS_B.
41	PE10	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM1_CH2N and SAI1_MCLK_B.
42	PE11	bidirectional	5 V tolerant (FT) I/O; alternate function TIM1_CH2.
43	PE12	bidirectional	5 V tolerant (FT) I/O; alternate function TIM1_CH3N.
44	PE13	bidirectional	5 V tolerant (FT) I/O; alternate function TIM1_CH3.
45	PE14	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM1_CH4 and TIM1_BKIN2.
46	PE15	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM1_BKIN, TIM1_CH4N and USART3_RX.
47	PB10	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM2_CH3, USART3_TX, LPUART1_RX, TIM1_BKIN and SAI1_SCK_A; OPAMP3_VINM.
48	VSS	power_in	Ground pin.
49	VDD	power_in	Supply pin; VDD standard operating range 1.71 V to 3.6 V.
50	PB11	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate functions TIM2_CH4, USART3_RX, LPUART1_TX; ADC12_IN14.
51	PB12	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate functions I2C2_SMBA, SPI2_NSS/I2S2_WS, TIM1_BKIN, USART3_CK and LPUART1_RTS_DE; ADC1_IN11.
52	PB13	bidirectional	TT I/O (3.6 V tolerant); alternate functions SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS and LPUART1_CTS; OPAMP3_VINP.
53	PB14	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM15_CH1, SPI2_MISO, TIM1_CH2N, USART3_RTS_DE and COMP4_OUT; ADC1_IN5 and OPAMP2_VINP.
54	PB15	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate functions RTC_REFIN, TIM15_CH2, TIM15_CH1N, COMP3_OUT, TIM1_CH3N and SPI2_MOSI/I2S2_SD; ADC2_IN15.
55	PD8	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate function USART3_TX.
56	PD9	bidirectional	5 V tolerant (FT) I/O; alternate function USART3_RX.
57	PD10	bidirectional	5 V tolerant (FT) I/O; alternate function USART3_CK.
58	PD11	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate function USART3_CTS.
59	PD12	bidirectional	TT I/O (3.6 V tolerant); alternate functions TIM4_CH1 and USART3_RTS_DE.
60	PD13	bidirectional	5 V tolerant (FT) I/O; alternate function TIM4_CH2.
61	PD14	bidirectional	FT_a I/O with analog switch supplied by VDDA; alternate function TIM4_CH3; OPAMP2_VINP.
62	PD15	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM4_CH4 and SPI2_NSS.
63	VSS	power_in	Ground pin.
64	VDD	power_in	Supply pin; VDD standard operating range 1.71 V to 3.6 V.
65	PC6	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM3_CH1, TIM8_CH1 and I2S2_MCK.
66	PC7	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM3_CH2, TIM8_CH2 and I2S3_MCK.
67	PC8	bidirectional	FT_f I/O (Fm+ capable); alternate functions TIM3_CH3, TIM8_CH3 and I2C3_SCL.
68	PC9	bidirectional	FT_f I/O (Fm+ capable); alternate functions TIM3_CH4, TIM8_CH4, I2SCKIN, TIM8_BKIN2 and I2C3_SDA.
69	PA8	bidirectional	5 V tolerant (FT) I/O; alternate functions MCO, I2C3_SCL, I2C2_SDA, I2S2_MCK, TIM1_CH1, USART1_CK and SAI1_SCK_A.
70	PA9	bidirectional	FT_f I/O (Fm+ capable); alternate functions I2C3_SMBA, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX and SAI1_FS_A; UCPD1_DBCC1.
71	PA10	bidirectional	FT_da I/O with USB Type-C dead battery function; alternate functions TIM17_BKIN, USB_CRS_SYNC, TIM1_CH3, USART1_RX and SAI1_SD_A; UCPD1_DBCC2.
72	PA11	bidirectional	5 V tolerant (FT) I/O; alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, COMP1_OUT and FDCAN1_RX; USB_DM.
73	PA12	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM16_CH1, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX and TIM4_CH2; USB_DP.
74	VSS	power_in	Ground pin.
75	VDD	power_in	Supply pin; VDD standard operating range 1.71 V to 3.6 V.
76	PA13	bidirectional	FT_f I/O (Fm+ capable); SWDIO-JTMS debug function after reset with internal pull-up enabled; alternate functions TIM16_CH1N, I2C1_SCL, IR_OUT and USART3_CTS.
77	PA14	bidirectional	FT_f I/O (Fm+ capable); SWCLK-JTCK debug function after reset with internal pull-down enabled; alternate functions LPTIM1_OUT, I2C1_SDA, TIM8_CH2, TIM1_BKIN and USART2_TX.
78	PA15	bidirectional	FT_f I/O (Fm+ capable); JTDI debug function after reset with internal pull-up enabled; alternate functions TIM2_CH1, TIM8_CH1, I2C1_SCL, SPI1_NSS and USART2_RX.
79	PC10	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM8_CH1N, UART4_TX, SPI3_SCK/I2S3_CK and USART3_TX.
80	PC11	bidirectional	FT_f I/O (Fm+ capable); alternate functions TIM8_CH2N, UART4_RX, SPI3_MISO, USART3_RX and I2C3_SDA.
81	PC12	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM8_CH3N, SPI3_MOSI/I2S3_SD, USART3_CK and UCPD1_FRSTX.
82	PD0	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM8_CH4N and FDCAN1_RX.
83	PD1	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM8_CH4, TIM8_BKIN2 and FDCAN1_TX.
84	PD2	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM3_ETR and TIM8_BKIN.
85	PD3	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM2_CH1/TIM2_ETR and USART2_CTS.
86	PD4	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM2_CH2 and USART2_RTS_DE.
87	PD5	bidirectional	5 V tolerant (FT) I/O; alternate function USART2_TX.
88	PD6	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM2_CH4, SAI1_D1, USART2_RX and SAI1_SD_A.
89	PD7	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM2_CH3 and USART2_CK.
90	PB3	bidirectional	5 V tolerant (FT) I/O; JTDO-TRACESWO debug function after reset; alternate functions TIM2_CH2, TIM4_ETR, USB_CRS_SYNC, SPI1_SCK, SPI3_SCK/I2S3_CK and USART2_TX.
91	PB4	bidirectional	5 V tolerant (FT) I/O; JTRST debug function after reset with internal pull-up enabled; alternate functions TIM16_CH1, TIM3_CH1, SPI1_MISO and USART2_RX; UCPD1_CC2.
92	PB5	bidirectional	FT_f I/O (Fm+ capable); alternate functions TIM16_BKIN, TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA and LPTIM1_IN1.
93	PB6	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM16_CH1N, TIM4_CH1, TIM8_CH1, TIM8_ETR, USART1_TX and COMP4_OUT; UCPD1_CC1.
94	PB7	bidirectional	FT_f I/O (Fm+ capable); alternate functions TIM17_CH1N, TIM4_CH2, I2C1_SDA, TIM8_BKIN, USART1_RX and COMP3_OUT; PVD_IN.
95	PB8-BOOT0	bidirectional	FT_f I/O (Fm+ capable) and dedicated BOOT0 pin; alternate functions TIM16_CH1, TIM4_CH3, I2C1_SCL, USART3_RX and FDCAN1_RX; set to a non-analog mode after startup if left unconnected.
96	PB9	bidirectional	FT_f I/O (Fm+ capable); alternate functions TIM17_CH1, TIM4_CH4, I2C1_SDA, IR_OUT, USART3_TX and FDCAN1_TX.
97	PE0	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM4_ETR, TIM16_CH1 and USART1_TX.
98	PE1	bidirectional	5 V tolerant (FT) I/O; alternate functions TIM17_CH1 and USART1_RX.
99	VSS	power_in	Ground pin.
100	VDD	power_in	Supply pin; VDD standard operating range 1.71 V to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
External main supply voltage (including VDD, VDDA and VBAT)	VDD - VSS	-0.3		4	V		68
Total current into sum of all VDD power lines (source)	∑IVDD			150	mA		69
Total current out of sum of all VSS ground lines (sink)	∑IVSS			150	mA		69
Maximum current into each VDD power pin (source)	IVDD(PIN)			100	mA		69
Maximum current out of each VSS ground pin (sink)	IVSS(PIN)			100	mA		69
Output current sunk by any I/O and control pin except FT_f	IIO(PIN)			20	mA		69
Output current sunk by any FT_f pin	IIO(PIN)			20	mA	FT_f pin	69
Output current sourced by any I/O and control pin	IIO(PIN)			20	mA	Sourced	69
Total output current sunk by sum of all I/Os and control pins	∑IIO(PIN)			100	mA		69
Total output current sourced by sum of all I/Os and control pins	∑IIO(PIN)			100	mA	Sourced	69
Injected current on FT_xxx, TT_xx, NRST pins	IINJ(PIN)	-5		0	mA		69
Total injected current (sum of all I/Os and control pins)	∑/IINJ(PIN)/			25	mA		69
Variations between different VDDX power pins of the same domain	/ΔVDDx/			50	mV		68
Variations between all the different ground pins	/VSSx-VSS/			50	mV	Include VREF- pin	68
Storage temperature range	TSTG	-65		150	°C		69
Maximum junction temperature	TJ			150	°C		69
Internal AHB clock frequency	fHCLK	0		170	MHz		70
Standard operating voltage	VDD	1.71		3.6	V		70
Analog supply voltage, ADC or COMP used	VDDA	1.62		3.6	V	ADC or COMP used	70
Analog supply voltage, DAC 1 MSPS or DAC 15 MSPS	VDDA	1.71		3.6	V	DAC 1 MSPS or DAC 15 MSPS	70
Analog supply voltage, OPAMP used	VDDA	2		3.6	V	OPAMP used	70
Analog supply voltage, VREFBUF used	VDDA	2.4		3.6	V	VREFBUF used	70
Backup operating voltage	VBAT	1.55		3.6	V		70
Ambient temperature, suffix 6, maximum power dissipation	TA	-40		85	°C	Suffix 6 version, maximum power dissipation	70
Ambient temperature, suffix 6, low-power dissipation	TA	-40		105	°C	Suffix 6 version, low-power dissipation	70
Junction temperature range, suffix 6 version	TJ	-40		105	°C	Suffix 6 version	70
Brown-out reset threshold 0, rising edge	VBOR0	1.62	1.66	1.7	V	Rising edge	71
Brown-out reset threshold 0, falling edge	VBOR0	1.6	1.64	1.69	V	Falling edge	71
Programmable voltage detector threshold 0, rising edge	VPVD0	2.1	2.15	2.19	V	Rising edge	71
Programmable voltage detector threshold 0, falling edge	VPVD0	2	2.05	2.1	V	Falling edge	71
VDDA peripheral voltage monitoring (COMP/ADC), rising edge	VPVM1	1.61	1.65	1.69	V	Rising edge	71
Internal reference voltage	VREFINT	1.182	1.212	1.232	V	-40 °C < TA < +130 °C	73
Average temperature coefficient	TCoeff		30	50	ppm/°C	-40°C < TA < +130°C	73
Average voltage coefficient	VDDCoeff		250	1200	ppm/V	3.0 V < VDD < 3.6 V	73
1/4 reference voltage	VREFINT_DIV1	24	25	26	%	Percentage of VREFINT	73
Supply current in Run mode, Range 1 Boost mode	IDD (Run)		25.5	27	mA	fHCLK = 170 MHz, ART enable, all peripherals disabled, 25°C	75
Supply current in Stop 0 mode, RTC disabled	IDD(Stop 0)		155	270	µA	VDD = 3 V, 25°C	89
Supply current in Stop 1 mode, RTC disabled	IDD (Stop 1)		59	160	µA	VDD = 3.0 V, 25°C	88
Supply current in Standby mode, RTC disabled, no independent watchdog	IDD (Standby)		120	280	nA	VDD = 3 V, 25°C	89
Supply current in Shutdown mode, RTC disabled	IDD (Shutdown)		35	330	nA	VDD = 3 V, 25°C	92
Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2	tVOST		20	40	µs	Wakeup clock HSI16 = 16 MHz, HPRE = 8	101
Wakeup time needed to calculate the maximum USART/LPUART baudrate, Stop 0 mode	tWUUSART / tWULPUART			1.7	µs	Stop 0 mode, USART/LPUART clock source HSI16	101
Wakeup time needed to calculate the maximum USART/LPUART baudrate, Stop 1 mode	tWUUSART / tWULPUART			8.5	µs	Stop 1 mode, USART/LPUART clock source HSI16	101
User external clock source frequency, voltage scaling Range 1	fHSE_ext	8		48	MHz	Voltage scaling Range 1	101
User external clock source frequency, voltage scaling Range 2	fHSE_ext	8		26	MHz	Voltage scaling Range 2	101

CAD (KiCad official)

Symbol: STM32G441VBT6
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: stm32g441vbt6-etched.step / stm32g441vbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g441vbt6.step / stm32g441vbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (197 pp, sha256 c557688669ff903c, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STM32G441VBT6

Verified STM32G441VBT6

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README