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Contents

README

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STM32G431K6U6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-32(5x5)

STM32G431K6U6 from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply pin, main VDD for core and I/O logic, 1.71-3.6 V.
2 PF0-OSC_IN bidirectional GPIO port F pin 0 serving as external oscillator crystal input; 5 V tolerant with analog switch function supplied by VDDA; supports I2C2_SDA, SPI2_NSS, TIM1_CH3N alternate functions and ADC1_IN10 analog input.
3 PF1-OSC_OUT bidirectional GPIO port F pin 1 serving as external oscillator crystal output; 3.6 V tolerant with analog switch function; supports SPI2_SCK alternate function, ADC2_IN10 analog input, and COMP3_INM comparator input.
4 PG10-NRST bidirectional System reset pin and GPIO port G pin 10 with embedded weak pull-up; 5 V tolerant; can serve as MCO output or general I/O, provides NRST reset function.
5 PA0 bidirectional GPIO port A pin 0 with analog functionality; 3.6 V tolerant with analog switch; supports TIM2_CH1, USART2_CTS, COMP1_OUT, TIM8 functions and ADC12_IN1 input; wakeup pin WKUP1.
6 PA1 bidirectional GPIO port A pin 1 with analog functionality; 3.6 V tolerant with analog switch; supports TIM2_CH2, USART2_RTS_DE, TIM15_CH1N, RTC_REFIN, and op-amp/comparator functions; ADC12_IN2 input.
7 PA2 bidirectional GPIO port A pin 2 with analog functionality; 3.6 V tolerant; supports TIM2_CH3, USART2_TX, COMP2_OUT, TIM15_CH1, LPUART1_TX, UCPD1_FRSTX; ADC1_IN3 input and op-amp output function.
8 PA3 bidirectional GPIO port A pin 3 with analog functionality; 3.6 V tolerant with analog switch; supports TIM2_CH4, SAI1_CK1, USART2_RX, TIM15_CH2, LPUART1_RX; ADC1_IN4 input and op-amp functions.
9 PA4 bidirectional GPIO port A pin 4 with analog output functionality (DAC1_OUT1); 3.6 V tolerant with analog switch; supports TIM3_CH2, SPI1_NSS, SPI3_NSS, USART2_CK, SAI1_FS_B and ADC2_IN17 analog input.
10 PA5 bidirectional GPIO port A pin 5 with analog functionality; 3.6 V tolerant with analog switch; supports TIM2_CH1, TIM2_ETR, SPI1_SCK, UCPD1_FRSTX; ADC2_IN13 input and DAC1_OUT2, op-amp functions.
11 PA6 bidirectional GPIO port A pin 6 with analog functionality; 3.6 V tolerant; supports TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, COMP1_OUT, LPUART1_CTS; ADC2_IN3 input and op-amp output.
12 PA7 bidirectional GPIO port A pin 7 with analog functionality; 3.6 V tolerant; supports TIM17_CH1, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, COMP2_OUT, UCPD1_FRSTX; ADC2_IN4 input and op-amp functions.
13 PB0 bidirectional GPIO port B pin 0 with analog functionality (ADC1_IN15); 3.6 V tolerant with analog switch; supports TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UCPD1_FRSTX and comparator/op-amp functions.
14 VSSA power_in Analog ground supply pin for ADC and analog peripherals.
15 VDDA/VREF+ power_in Analog supply pin (1.62-3.6 V for ADC/COMP/DAC, 2.0-3.6 V for op-amp, 2.4-3.6 V with VREFBUF); serves as VREFBUF_OUT for internal voltage reference buffer (2.048/2.5/2.9 V outputs).
16 VSS power_in Ground supply pin, second VSS connection for I/O and digital circuits.
17 VDD power_in Power supply pin, second VDD for core and I/O logic, 1.71-3.6 V.
18 PA8 bidirectional GPIO port A pin 8; 5 V tolerant with Fm+ capability; supports MCO, I2C3_SCL, I2C2_SDA, I2S2_MCK, TIM1_CH1, USART1_CK, TIM4_ETR, SAI1 alternate functions.
19 PA9 bidirectional GPIO port A pin 9; 5 V tolerant with USB dead battery and UCPD dead battery (UCPD1_DBCC1) functions; supports I2C3, I2C2, I2S3, TIM1_CH2, USART1_TX, TIM15_BKIN, TIM2_CH3, SAI1_FS_A alternate functions.
20 PA10 bidirectional GPIO port A pin 10; 5 V tolerant with USB dead battery (UCPD1_DBCC2) and analog switch functions; supports TIM17_BKIN, USB_CRS_SYNC, I2C2, SPI2, TIM1_CH3, USART1_RX, TIM2_CH4, TIM8_BKIN, SAI1 alternate functions.
21 PA11 bidirectional GPIO port A pin 11 with USB functionality (USB_DM); 5 V tolerant; supports SPI2_MOSI, TIM1_CH1N, USART1_CTS, COMP1_OUT, FDCAN1_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2 alternate functions.
22 PA12 bidirectional GPIO port A pin 12 with USB functionality (USB_DP); 5 V tolerant; supports TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS_DE, COMP2_OUT, FDCAN1_TX, TIM4_CH2, TIM1_ETR alternate functions.
23 PA13 bidirectional GPIO port A pin 13 / SWDIO-JTMS debug pin; 5 V tolerant with Fm+ capability; internal pull-up activated after reset; supports TIM16_CH1N, I2C1_SCL, IR_OUT, USART3_CTS, TIM4_CH3, SAI1_SD_B alternate functions.
24 PA14 bidirectional GPIO port A pin 14 / SWCLK-JTCK debug pin; 5 V tolerant with Fm+ capability; internal pull-down activated after reset; supports LPTIM1_OUT, I2C1_SDA, TIM8_CH2, TIM1_BKIN, USART2_TX, SAI1_FS_B alternate functions.
25 PA15 bidirectional GPIO port A pin 15 / JTDI debug pin; 5 V tolerant with Fm+ capability; internal pull-up activated after reset; supports TIM2_CH1, TIM8_CH1, I2C1_SCL, SPI1_NSS, SPI3_NSS, USART2_RX, UART4_RTS_DE, TIM1 alternate functions.
26 PB3 bidirectional GPIO port B pin 3 / JTDO-TRACESWO debug pin; 5 V tolerant; internal pull-up after reset; supports TIM2_CH2, TIM4_ETR, USB_CRS_SYNC, TIM8_CH1N, SPI1_SCK, SPI3_SCK, USART2_TX, TIM3_ETR, SAI1_SCK_B alternate functions.
27 PB4 bidirectional GPIO port B pin 4 / JTRST debug pin; 5 V tolerant USB Type-C capable with UCPD1_CC2 function; internal pull-down (5.1 kΩ) controlled by UCPD dead battery detection; supports TIM16_CH1, TIM3_CH1, TIM8_CH2N, SPI1_MISO, SPI3_MISO, USART2_RX, TIM17_BKIN, SAI1_MCLK_B alternate functions.
28 PB5 bidirectional GPIO port B pin 5; 5 V tolerant with Fm+ capability; supports TIM16_BKIN, TIM3_CH2, TIM8_CH3N, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART2_CK, I2C3_SDA, TIM17_CH1, LPTIM1_IN1, SAI1_SD_B alternate functions.
29 PB6 bidirectional GPIO port B pin 6; 5 V tolerant USB Type-C capable with UCPD1_CC1 function; internal pull-down (5.1 kΩ) controlled by UCPD dead battery detection; supports TIM16_CH1N, TIM4_CH1, TIM8_CH1, TIM8_ETR, USART1_TX, COMP4_OUT, TIM8_BKIN2, LPTIM1_ETR, SAI1_FS_B alternate functions.
30 PB7 bidirectional GPIO port B pin 7; 5 V tolerant with Fm+ capability; supports TIM17_CH1N, TIM4_CH2, I2C1_SDA, TIM8_BKIN, USART1_RX, COMP3_OUT, TIM3_CH4, LPTIM1_IN2, UART4_CTS alternate functions; PVD_IN power supervision input.
31 PB8-BOOT0 bidirectional GPIO port B pin 8 and BOOT0 boot mode select pin; 5 V tolerant with Fm+ capability; recommended to set to non-analog mode after startup if left unconnected; supports TIM16_CH1, TIM4_CH3, SAI1_CK1, I2C1_SCL, USART3_RX, COMP1_OUT, FDCAN1_RX, TIM8_CH2, TIM1_BKIN, SAI1_MCLK_A alternate functions.
32 VSS power_in Ground supply pin, second VSS connection for digital circuits.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: STM32G431K6U6
  • Footprint: Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
  • 3D model: UFQFPN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: stm32g431k6u6-etched.step / stm32g431k6u6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g431k6u6.step / stm32g431k6u6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (197 pp, sha256 caaa126a00ab9e06, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF