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STM32G0B1RBT6

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STMicroelectronics Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32G0B1RBT6

STMicroelectronics · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

STM32G0B1RBT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC11 bidirectional 5 V-tolerant (FT) I/O with alternate functions USART3_RX, USART4_RX, TIM1_CH4, SPI3_MISO.
2 PC12 bidirectional 5 V-tolerant (FT) I/O with alternate functions LPTIM1_IN1, UCPD1_FRSTX, TIM14_CH1, USART5_TX, SPI3_MOSI.
3 PC13 bidirectional FT I/O supplied through the power switch (sinks only 3 mA, output limited to 2 MHz with 30 pF max, not a current source); AF TIM1_BKIN; additional TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2.
4 PC14-OSC32_IN bidirectional FT I/O supplied through the power switch (3 mA limit); AF TIM1_BKIN2; additional function OSC32_IN (32 kHz crystal input).
5 PC15-OSC32_OUT bidirectional FT I/O supplied through the power switch (3 mA limit); AF OSC32_EN, OSC_EN, TIM15_BKIN; additional function OSC32_OUT (32 kHz crystal output).
6 VBAT power_in Backup supply of 1.55 V to 3.6 V for RTC, TAMP, LSE oscillator and backup registers when VDD is not present.
7 VREF+ power_in Analog reference voltage input, or output of the internal voltage reference buffer (VREFBUF_OUT) when enabled; 2 V to VDDA when VDDA is 2 V or above.
8 VDD/VDDA power_in Main digital and analog supply, 1.7 V to 3.6 V (VDDA 1.62 V for ADC/COMP, 1.8 V for DAC, 2.4 V for VREFBUF); also supplies VDDIO1.
9 VSS/VSSA power_in Ground for digital and analog supplies.
10 PF0-OSC_IN bidirectional FT I/O with AF CRS1_SYNC, EVENTOUT, TIM14_CH1; additional function OSC_IN (4-48 MHz crystal oscillator input).
11 PF1-OSC_OUT bidirectional FT I/O with AF OSC_EN, EVENTOUT, TIM15_CH1N; additional function OSC_OUT (crystal oscillator output).
12 PF2-NRST bidirectional Bidirectional reset pin with embedded weak pull-up; also AF MCO, LPUART2_TX, LPUART2_RTS_DE.
13 PC0 bidirectional FT_a I/O with AF LPTIM1_IN1, LPUART1_RX, LPTIM2_IN1, LPUART2_TX, USART6_TX, I2C3_SCL, COMP3_OUT; additional COMP3_INM7.
14 PC1 bidirectional FT_a I/O with AF LPTIM1_OUT, LPUART1_TX, TIM15_CH1, LPUART2_RX, USART6_RX, I2C3_SDA; additional COMP3_INP1.
15 PC2 bidirectional FT I/O with AF LPTIM1_IN2, SPI2_MISO/I2S2_MCK, TIM15_CH2, FDCAN2_RX, COMP3_OUT.
16 PC3 bidirectional FT I/O with AF LPTIM1_ETR, SPI2_MOSI/I2S2_SD, LPTIM2_ETR, FDCAN2_TX.
17 PA0 bidirectional FT_a I/O with AF SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT; additional COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1.
18 PA1 bidirectional FT_ea I/O with AF SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT; additional COMP1_INP2, ADC_IN1.
19 PA2 bidirectional FT_a I/O with AF SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT; additional COMP2_INM8, ADC_IN2, WKUP4, LSCO.
20 PA3 bidirectional FT_ea I/O with AF SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT; additional COMP2_INP2, ADC_IN3.
21 PA4 bidirectional 3.6 V-tolerant TT_a I/O with AF SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS; additional ADC_IN4, DAC1_OUT1, RTC_OUT2.
22 PA5 bidirectional TT_ea I/O with AF SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT; additional ADC_IN5, DAC1_OUT2.
23 PA6 bidirectional FT_ea I/O with AF SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA; additional ADC_IN6.
24 PA7 bidirectional FT_a I/O with AF SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL; additional ADC_IN7.
25 PC4 bidirectional FT_a I/O with AF USART3_TX, USART1_TX, TIM2_CH1_ETR, FDCAN1_RX; additional COMP1_INM7, ADC_IN17.
26 PC5 bidirectional FT_a I/O with AF USART3_RX, USART1_RX, TIM2_CH2, FDCAN1_TX; additional COMP1_INP0, ADC_IN18, WKUP5.
27 PB0 bidirectional FT_ea I/O with AF SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS; additional COMP3_INP0, ADC_IN8.
28 PB1 bidirectional FT_ea I/O with AF TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE; additional COMP1_INM6, ADC_IN9.
29 PB2 bidirectional FT_ea I/O with AF SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT; additional COMP1_INP1, COMP3_INM6, ADC_IN10.
30 PB10 bidirectional FT_fa (Fm+ capable) I/O with AF CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK/I2S2_CK, I2C2_SCL, COMP1_OUT; additional ADC_IN11.
31 PB11 bidirectional FT_fa (Fm+ capable) I/O with AF SPI2_MOSI/I2S2_SD, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT; additional ADC_IN15.
32 PB12 bidirectional FT_fa (Fm+ capable) I/O with AF SPI2_NSS/I2S2_WS, LPUART1_RTS_DE, TIM1_BKIN, FDCAN2_RX, TIM15_BKIN, UCPD2_FRSTX, EVENTOUT, I2C2_SMBA; additional ADC_IN16.
33 PB13 bidirectional FT_fs (Fm+ capable) I/O with AF SPI2_SCK/I2S2_CK, LPUART1_CTS, TIM1_CH1N, FDCAN2_TX, USART3_CTS, TIM15_CH1N, I2C2_SCL, EVENTOUT.
34 PB14 bidirectional FT_fs (Fm+ capable) I/O with AF SPI2_MISO/I2S2_MCK, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, EVENTOUT, USART6_RTS_DE_CK.
35 PB15 bidirectional FT_fcs I/O with AF SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, EVENTOUT, USART6_CTS; additional UCPD1_CC2, RTC_REFIN; a pull-down may be present upon reset.
36 PA8 bidirectional FT_fcs I/O with AF MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA; additional UCPD1_CC1; a pull-down may be present upon reset.
37 PA9 bidirectional FT_fds I/O with AF MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL; additional UCPD1_DBCC1.
38 PC6 bidirectional FT_s I/O supplied from VDDIO2 only, with AF UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX.
39 PC7 bidirectional FT_s I/O supplied from VDDIO2 only, with AF UCPD2_FRSTX, TIM3_CH2, TIM2_CH4, LPUART2_RX.
40 PD8 bidirectional FT_s I/O supplied from VDDIO2 only, with AF USART3_TX, SPI1_SCK/I2S1_CK, LPTIM1_OUT.
41 PD9 bidirectional FT_s I/O supplied from VDDIO2 only, with AF USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2.
42 PA10 bidirectional FT_fds I/O with AF SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA; additional UCPD1_DBCC2.
43 PA11 [PA9] bidirectional FT_fs I/O with AF SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT; additional USB_DM; can be remapped to PA9.
44 PA12 [PA10] bidirectional FT_fs I/O with AF SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT; additional USB_DP; can be remapped to PA10.
45 PA13 bidirectional FT_es I/O, SWDIO at reset with internal pull-up active; AF IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX.
46 PA14-BOOT0 bidirectional FT_s I/O, SWCLK at reset with internal pull-down active; AF USART2_TX, EVENTOUT, LPUART2_TX; additional BOOT0.
47 PA15 bidirectional FT_s I/O with AF SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS.
48 PC8 bidirectional FT_s I/O with AF UCPD2_FRSTX, TIM3_CH3, TIM1_CH1, LPUART2_CTS.
49 PC9 bidirectional FT_s I/O with AF I2S_CKIN, TIM3_CH4, TIM1_CH2, LPUART2_RTS_DE, USB_NOE.
50 PD0 bidirectional FT_cs I/O with AF EVENTOUT, SPI2_NSS/I2S2_WS, TIM16_CH1, FDCAN1_RX; additional UCPD2_CC1; a pull-down may be present upon reset.
51 PD1 bidirectional FT_ds I/O with AF EVENTOUT, SPI2_SCK/I2S2_CK, TIM17_CH1, FDCAN1_TX; additional UCPD2_DBCC1.
52 PD2 bidirectional FT_cs I/O with AF USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, USART5_RX; additional UCPD2_CC2; a pull-down may be present upon reset.
53 PD3 bidirectional FT_ds I/O with AF USART2_CTS, SPI2_MISO/I2S2_MCK, TIM1_CH2N, USART5_TX; additional UCPD2_DBCC2.
54 PD4 bidirectional FT_s I/O with AF USART2_RTS_DE_CK, SPI2_MOSI/I2S2_SD, TIM1_CH3N, USART5_RTS_DE_CK.
55 PD5 bidirectional FT I/O with AF USART2_TX, SPI1_MISO/I2S1_MCK, TIM1_BKIN, USART5_CTS.
56 PD6 bidirectional FT I/O with AF USART2_RX, SPI1_MOSI/I2S1_SD, LPTIM2_OUT.
57 PB3 bidirectional FT_a I/O with AF SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK; additional COMP2_INM6.
58 PB4 bidirectional FT_a I/O with AF SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO; additional COMP2_INP0.
59 PB5 bidirectional FT I/O with AF SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI; additional WKUP6.
60 PB6 bidirectional FT_fa (Fm+ capable) I/O with AF USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX; additional COMP2_INP1.
61 PB7 bidirectional FT_fa (Fm+ capable) I/O with AF USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX; additional COMP2_INM7, PVD_IN.
62 PB8 bidirectional FT_f (Fm+ capable) I/O with AF CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3.
63 PB9 bidirectional FT_f (Fm+ capable) I/O with AF IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4.
64 PC10 bidirectional FT I/O with AF USART3_TX, USART4_TX, TIM1_CH3, SPI3_SCK.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External supply voltage VDD -0.3 4 V 66
External supply voltage for selected I/Os VDDIO2 -0.3 4 V 66
External supply voltage on VBAT pin VBAT -0.3 4 V 66
Input voltage on FT_xx pins except FT_c VIN -0.3 V max VDD + 4.0 (to sustain voltage higher than 4 V pull-up/pull-down must be disabled) 66
Input voltage on FT_c pins VIN -0.3 5.5 V 66
Input voltage on any other pin VIN -0.3 4 V 66
Current into VDD/VDDA/VDDIO2 power pin (source) IVDD/VDDA/VDDIO2 100 mA 67
Current out of VSS/VSSA ground pin (sink) IVSS/VSSA 100 mA 67
Output current sunk by any I/O and control pin except FT_f IIO(PIN) 15 mA 67
Output current sourced by any I/O and control pin IIO(PIN) 15 mA 67
Total output current sunk by sum of all I/Os and control pins ΣIIO(PIN) 80 mA 67
Storage temperature range TSTG -65 150 °C 67
Maximum junction temperature TJ 150 °C 67
Internal AHB clock frequency fHCLK 0 64 MHz 67
Internal APB clock frequency fPCLK 0 64 MHz 67
Standard operating voltage VDD 1.7 3.6 V When RESET is released functionality is guaranteed down to VPDR min 67
External supply voltage for selected I/Os VDDIO2 1.7 3.6 V 67
Analog supply voltage VDDA 1.62 3.6 V For ADC and COMP operation 68
Analog supply voltage VDDA 1.8 3.6 V For DAC operation 68
Analog supply voltage VDDA 2.4 3.6 V For VREFBUF operation 68
Backup operating voltage VBAT 1.55 3.6 V 68
Ambient temperature TA -40 85 °C Suffix 6 68
Junction temperature TJ -40 105 °C Suffix 6 68
Power-on reset threshold VPOR 1.62 1.66 1.7 V 68
Power-down reset threshold VPDR 1.6 1.64 1.69 V 69
POR temporization when VDD crosses VPOR tRSTTEMPO 250 400 μs VDD rising 68
BOR and PVD consumption IDD(BOR_PVD) 1.1 1.6 µA 69
Internal reference voltage VREFINT 1.182 1.212 1.232 V -40°C < TJ < 130°C 70
Temperature coefficient of VREFINT TCoeff_vrefint 30 50 ppm/°C 70
Supply current in Run mode IDD(Run) 8.6 9 mA Range 1; fHCLK = 64 MHz; Flash memory; 25 °C; VDD = 3.0 V typ / 3.6 V max 72
Supply current in Stop 0 mode IDD(Stop 0) 295 375 µA HSI kernel enabled; VDD 3 V; 25°C 74
Supply current in Standby mode IDD(Standby) 0.2 1.4 µA RTC disabled; VDD 3.0 V; 25°C 75
HSI16 Frequency fHSI16 15.88 16.08 MHz VDD=3.0 V, TA=30 °C 86
LSI frequency fLSI 31.04 32.96 kHz VDD = 3.0 V, TA = 30 °C 88
Page (2 Kbyte) erase time tERASE 22 40 ms 89
Endurance NEND 10 kcycles TA = -40 to +105 °C 90

CAD (KiCad official)

  • Symbol: STM32G0B1RBT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32g0b1rbt6-etched.step / stm32g0b1rbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g0b1rbt6.step / stm32g0b1rbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (159 pp, sha256 add53ab68c4d519b, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF