STM32G0B1CCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32G0B1CCT6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PC13	bidirectional	5 V-tolerant (FT) I/O supplied through the power switch, limited to 3 mA so output speed is at most 2 MHz with 30 pF load and it can act only as a current sink; alternate TIM1_BKIN, additional TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2.
2	PC14-OSC32_IN	bidirectional	FT I/O on the power-switch domain with the same 3 mA / 2 MHz / 30 pF output limits; used as OSC32_IN for the 32.768 kHz LSE crystal (alternate TIM1_BKIN2).
3	PC15-OSC32_OUT	bidirectional	FT I/O on the power-switch domain with the same 3 mA / 2 MHz / 30 pF output limits; used as OSC32_OUT for the LSE crystal (alternates OSC32_EN, OSC_EN, TIM15_BKIN).
4	VBAT	power_in	Backup supply for RTC, TAMP, LSE and backup registers, specified from 1.55 V to 3.6 V when VDD is not present.
5	VREF+	power_in	Analog reference input (or VREFBUF_OUT); must equal VDDA when VDDA < 2 V and be between 2 V and VDDA when VDDA ≥ 2 V, and can be grounded when unused.
6	VDD/VDDA	power_in	Main supply for the internal regulator, I/Os and analog blocks, operating from 1.7 V to 3.6 V (VDDA minimum 1.62 V for ADC and COMP).
7	VSS/VSSA	power_in	Ground reference for digital and analog circuitry; all voltages are referenced to VSS.
8	PF0-OSC_IN	bidirectional	FT I/O that serves as OSC_IN, the HSE 4 to 48 MHz crystal oscillator input (alternates CRS1_SYNC, EVENTOUT, TIM14_CH1).
9	PF1-OSC_OUT	bidirectional	FT I/O that serves as OSC_OUT, the HSE crystal oscillator output (alternates OSC_EN, EVENTOUT, TIM15_CH1N).
10	PF2-NRST	bidirectional	Reset pin with embedded weak pull-up, RST structure when configured as reset and FT when configured as GPIO (alternates MCO, LPUART2_TX, LPUART2_RTS_DE).
11	PA0	bidirectional	FT_a 5 V-tolerant I/O with analog switch function; alternates include SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, LPTIM1_OUT, COMP1_OUT, additional ADC_IN0, TAMP_IN2, WKUP1.
12	PA1	bidirectional	FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_SCK, USART2_RTS_DE_CK, TIM2_CH2, TIM15_CH1N, I2C1_SMBA, additional ADC_IN1 and COMP1_INP2.
13	PA2	bidirectional	FT_a I/O with analog switch; alternates include SPI1_MOSI, USART2_TX, TIM2_CH3, UCPD1_FRSTX, LPUART1_TX, COMP2_OUT, additional ADC_IN2, WKUP4, LSCO.
14	PA3	bidirectional	FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI2_MISO, USART2_RX, TIM2_CH4, TIM15_CH2, LPUART1_RX, additional ADC_IN3 and COMP2_INP2.
15	PA4	bidirectional	TT_a 3.6 V-tolerant I/O with analog switch; alternates include SPI1_NSS, SPI2_MOSI, USART6_TX, TIM14_CH1, LPTIM2_OUT, SPI3_NSS, additional ADC_IN4, DAC1_OUT1, RTC_OUT2.
16	PA5	bidirectional	TT_ea 3.6 V-tolerant I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_SCK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, additional ADC_IN5 and DAC1_OUT2.
17	PA6	bidirectional	FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_MISO, TIM3_CH1, TIM1_BKIN, USART6_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, additional ADC_IN6.
18	PA7	bidirectional	FT_a I/O with analog switch; alternates include SPI1_MOSI, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM17_CH1, COMP2_OUT, I2C2_SCL, I2C3_SCL, additional ADC_IN7.
19	PB0	bidirectional	FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_NSS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, COMP1_OUT, additional COMP3_INP0 and ADC_IN8.
20	PB1	bidirectional	FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, COMP3_OUT, additional COMP1_INM6 and ADC_IN9.
21	PB2	bidirectional	FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI2_MISO, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT, additional COMP1_INP1, COMP3_INM6 and ADC_IN10.
22	PB10	bidirectional	FT_fa I/O with analog switch and Fm+ capability; alternates include CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK, I2C2_SCL, COMP1_OUT, additional ADC_IN11.
23	PB11	bidirectional	FT_fa I/O with analog switch and Fm+ capability; alternates include SPI2_MOSI, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT, additional ADC_IN15.
24	PB12	bidirectional	FT_fa I/O with analog switch and Fm+ capability; alternates include SPI2_NSS, LPUART1_RTS_DE, TIM1_BKIN, FDCAN2_RX, TIM15_BKIN, UCPD2_FRSTX, I2C2_SMBA, additional ADC_IN16.
25	PB13	bidirectional	FT_fs I/O supplied from VDDIO2 only; alternates include SPI2_SCK, LPUART1_CTS, TIM1_CH1N, FDCAN2_TX, USART3_CTS, TIM15_CH1N, I2C2_SCL.
26	PB14	bidirectional	FT_fs I/O supplied from VDDIO2 only; alternates include SPI2_MISO, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, USART6_RTS_DE_CK.
27	PB15	bidirectional	FT_fcs I/O supplied from VDDIO2 only, with possible pull-down on reset depending on PA9-related voltage; alternates include SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, USART6_CTS, additional UCPD1_CC2 and RTC_REFIN.
28	PA8	bidirectional	FT_fcs I/O supplied from VDDIO2 only, with possible pull-down on reset depending on PA9 voltage; alternates include MCO, SPI2_NSS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, I2C2_SMBA, additional UCPD1_CC1.
29	PA9	bidirectional	FT_fds I/O supplied from VDDIO2 only, with possible pull-down on reset depending on voltage level; alternates include MCO, USART1_TX, TIM1_CH2, SPI2_MISO, TIM15_BKIN, I2C1_SCL, I2C2_SCL, additional UCPD1_DBCC1.
30	PC6	bidirectional	FT_s I/O supplied from VDDIO2 only; alternates include UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX.
31	PC7	bidirectional	FT_s I/O supplied from VDDIO2 only; alternates include UCPD2_FRSTX, TIM3_CH2, TIM2_CH4, LPUART2_RX.
32	PA10	bidirectional	FT_fds I/O supplied from VDDIO2 only, with possible pull-down on reset depending on PD1 voltage; alternates include SPI2_MOSI, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, I2C2_SDA, additional UCPD1_DBCC2.
33	PA11 [PA9]	bidirectional	FT_fus I/O supplied from VDDIO2 only with USB function; alternates include SPI1_MISO, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT, additional USB_DM; can be remapped with PA9 via SYSCFG_CFGR1.
34	PA12 [PA10]	bidirectional	FT_fus I/O supplied from VDDIO2 only with USB function; alternates include SPI1_MOSI, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT, additional USB_DP; can be remapped with PA10 via SYSCFG_CFGR1.
35	PA13	bidirectional	FT_es I/O with switchable diode to VDDIOx; upon reset it is configured as SWDIO with internal pull-up active; alternates include IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX.
36	PA14-BOOT0	bidirectional	FT_s I/O supplied from VDDIO2 only; upon reset it is configured as SWCLK with internal pull-down active, and it serves as the BOOT0 pin (alternates USART2_TX, EVENTOUT, LPUART2_TX).
37	PA15	bidirectional	FT_s I/O supplied from VDDIO2 only; alternates include SPI1_NSS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS.
38	PD0	bidirectional	FT_cs I/O with USB Type-C CC function and possible pull-down on reset depending on PD1 voltage; alternates include EVENTOUT, SPI2_NSS, TIM16_CH1, FDCAN1_RX, additional UCPD2_CC1.
39	PD1	bidirectional	FT_ds I/O with USB Type-C dead battery function and possible pull-down on reset depending on voltage level; alternates include EVENTOUT, SPI2_SCK, TIM17_CH1, FDCAN1_TX, additional UCPD2_DBCC1.
40	PD2	bidirectional	FT_cs I/O with USB Type-C CC function and possible pull-down on reset depending on PD3 voltage; alternates include USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, USART5_RX, additional UCPD2_CC2.
41	PD3	bidirectional	FT_ds I/O with USB Type-C dead battery function and possible pull-down on reset depending on voltage level; alternates include USART2_CTS, SPI2_MISO, TIM1_CH2N, USART5_TX, additional UCPD2_DBCC2.
42	PB3	bidirectional	FT_a I/O with analog switch; alternates include SPI1_SCK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK, additional COMP2_INM6.
43	PB4	bidirectional	FT_a I/O with analog switch; alternates include SPI1_MISO, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO, additional COMP2_INP0.
44	PB5	bidirectional	FT I/O; alternates include SPI1_MOSI, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI, additional WKUP6.
45	PB6	bidirectional	FT_fa I/O with analog switch and Fm+ capability; alternates include USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, USART5_CTS, TIM4_CH1, LPUART2_TX, additional COMP2_INP1.
46	PB7	bidirectional	FT_fa I/O with analog switch and Fm+ capability; alternates include USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, TIM4_CH2, LPUART2_RX, additional COMP2_INM7 and PVD_IN.
47	PB8	bidirectional	FT_f I/O with Fm+ capability; alternates include CEC, SPI2_SCK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, USART6_TX, TIM4_CH3.
48	PB9	bidirectional	FT_f I/O with Fm+ capability; alternates include IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS, I2C1_SDA, USART6_RX, TIM4_CH4.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD (external)	VDD	-0.3		4	V		66
External supply voltage for selected I/Os	VDDIO2	-0.3		4	V		66
External supply voltage on VBAT pin	VBAT	-0.3		4	V		66
External voltage on VREF+ pin	VREF+	-0.3			V	Printed max is Min(VDD + 0.4, 4.0)	66
Input voltage on FT_xx pins except FT_c	VIN	-0.3			V	Printed max is VDD + 4.0; internal pull-up/pull-down must be disabled above 4 V	66
Input voltage on FT_c pins	VIN	-0.3		5.5	V		66
Input voltage on any other pin	VIN	-0.3		4	V		66
Current into VDD/VDDA and VDDIO2 power pins (source)	IVDD/VDDA/VDDIO2			100	mA		66
Current out of VSS/VSSA and VSS ground pins (sink)	IVSS/VSSA			100	mA		66
Output current sunk by any I/O and control pin except FT_f	IIO(PIN)			15	mA		67
Output current sunk by any FT_f pin	IIO(PIN)			20	mA		67
Output current sourced by any I/O and control pin	IIO(PIN)			15	mA		67
Total output current sunk by sum of all I/Os and control pins	∑IIO(PIN)			80	mA		67
Total output current sourced by sum of all I/Os and control pins	∑IIO(PIN)			80	mA		67
Injected current on a FT_xx pin	IINJ(PIN)	-5			mA	Printed as -5 / NA; positive injection not possible on FT_xx	67
Injected current on a TT_a pin	IINJ(PIN)	-5		0	mA	Printed as -5 / 0; any injection disturbs analog performance	67
Total injected current (sum of all I/Os and control pins)	∑/IINJ(PIN)/			25	mA		67
Storage temperature range	TSTG	-65		150	°C		67
Maximum junction temperature	TJ			150	°C		67
Internal AHB clock frequency	fHCLK	0		64	MHz		67
Internal APB clock frequency	fPCLK	0		64	MHz		67
Standard operating voltage	VDD	1.7		3.6	V		67
External supply voltage for selected I/Os	VDDIO2	1.65		3.6	V		67
Analog supply voltage for ADC and COMP operation	VDDA	1.62		3.6	V	For ADC and COMP operation	67
Analog supply voltage for DAC operation	VDDA	1.8		3.6	V	For DAC operation	67
Analog supply voltage for VREFBUF operation	VDDA	2.4		3.6	V	For VREFBUF operation	67
Backup operating voltage	VBAT	1.55		3.6	V		67
I/O input voltage (all except RST, TT_xx and FT_c)	VIN	-0.3			V	Printed max is Min(VDD + 3.6, 5.5)	68
I/O input voltage RST pin	VIN	-0.3			V	Printed max is VDD + 0.3	68
I/O input voltage TT_xx pins	VIN	-0.3			V	Printed max is VDDA + 0.3	68
I/O input voltage FT_c pins	VIN	-0.3		5	V		68
Ambient temperature, suffix 6	TA	-40		85	°C	Temperature range digit 6 in order code	68
Junction temperature, suffix 6	TJ	-40		105	°C	Temperature range digit 6 in order code	68
Power-on reset threshold	VPOR	1.62	1.66	1.7	V		68
Power-down reset threshold	VPDR	1.6	1.64	1.69	V		68
Brownout reset threshold 1 (rising)	VBOR1	2.05	2.1	2.18	V	VDD rising	68
Brownout reset threshold 1 (falling)	VBOR1	1.95	2	2.08	V	VDD falling	68
Brownout reset threshold 2 (rising)	VBOR2	2.2	2.31	2.38	V	VDD rising	69
Brownout reset threshold 2 (falling)	VBOR2	2.1	2.21	2.28	V	VDD falling	69
Brownout reset threshold 3 (rising)	VBOR3	2.5	2.62	2.68	V	VDD rising	69
Brownout reset threshold 3 (falling)	VBOR3	2.4	2.52	2.58	V	VDD falling	69
Brownout reset threshold 4 (rising)	VBOR4	2.8	2.91	3	V	VDD rising	69
Brownout reset threshold 4 (falling)	VBOR4	2.7	2.81	2.9	V	VDD falling	69
Internal reference voltage	VREFINT	1.182	1.212	1.232	V	-40°C < TJ < 130°C	70
Internal reference voltage temperature coefficient	TCoeff_vrefint		30	50	ppm/°C		70
Internal reference voltage voltage coefficient	VDDCoeff		250	1200	ppm/V	3.0 V < VDD < 3.6 V	70
Supply current in Standby mode, 25 °C	IDD(Standby)		0.3	1.8	µA	RTC disabled; VDD = 3.6 V; 25 °C	75
Supply current in Standby mode, 85 °C	IDD(Standby)		3.5	21	µA	RTC disabled; VDD = 3.6 V; 85 °C	75
Supply current in Run mode (from flash memory), 64 MHz, 25 °C	IDD(Run)		8.6	9	mA	Range 1; PLL enabled; fHCLK = 64 MHz; flash memory; 25 °C	72
User external clock source frequency, Range 1	fHSE_ext	8		48	MHz	Voltage scaling Range 1	81
User external clock source frequency, Range 2	fHSE_ext	8		26	MHz	Voltage scaling Range 2	81
HSE oscillator frequency	fOSC_IN	4	8	48	MHz		83
HSI16 frequency	fHSI16	15.88		16.08	MHz	VDD = 3.0 V, TA = 30 °C	86
HSI16 oscillator frequency drift over temperature	∆Temp(HSI16)	-1		1	%	TA = 0 to 85 °C	86
Accuracy of the HSI48 oscillator over temperature (factory calibrated)	ACCHSI48_REL	-3		3	%	VDD = 3.0 V to 3.6 V, TA = -15 to 85 °C	87
LSI frequency	fLSI	29.5		34	kHz	VDD = 1.62 V to 3.6 V, TA = -40 to 125 °C	88
Wakeup time from Standby mode	tWUSTBY		14.5	30	µs	Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1	80
Wakeup time from Shutdown mode	tWUSHDN		258	340	µs	Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1	81
PLL input clock frequency	fPLL_IN	2.66		16	MHz		88

CAD (KiCad official)

Symbol: STM32G0B1CCT6
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm32g0b1cct6-etched.step / stm32g0b1cct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g0b1cct6.step / stm32g0b1cct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (160 pp, sha256 c0903d327169522e, retrieved 2026-10-20, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# STM32G0B1CCT6

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32G0B1CCT6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC13 | bidirectional | 5 V-tolerant (FT) I/O supplied through the power switch, limited to 3 mA so output speed is at most 2 MHz with 30 pF load and it can act only as a current sink; alternate TIM1_BKIN, additional TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. |
| 2 | PC14-OSC32_IN | bidirectional | FT I/O on the power-switch domain with the same 3 mA / 2 MHz / 30 pF output limits; used as OSC32_IN for the 32.768 kHz LSE crystal (alternate TIM1_BKIN2). |
| 3 | PC15-OSC32_OUT | bidirectional | FT I/O on the power-switch domain with the same 3 mA / 2 MHz / 30 pF output limits; used as OSC32_OUT for the LSE crystal (alternates OSC32_EN, OSC_EN, TIM15_BKIN). |
| 4 | VBAT | power_in | Backup supply for RTC, TAMP, LSE and backup registers, specified from 1.55 V to 3.6 V when VDD is not present. |
| 5 | VREF+ | power_in | Analog reference input (or VREFBUF_OUT); must equal VDDA when VDDA < 2 V and be between 2 V and VDDA when VDDA ≥ 2 V, and can be grounded when unused. |
| 6 | VDD/VDDA | power_in | Main supply for the internal regulator, I/Os and analog blocks, operating from 1.7 V to 3.6 V (VDDA minimum 1.62 V for ADC and COMP). |
| 7 | VSS/VSSA | power_in | Ground reference for digital and analog circuitry; all voltages are referenced to VSS. |
| 8 | PF0-OSC_IN | bidirectional | FT I/O that serves as OSC_IN, the HSE 4 to 48 MHz crystal oscillator input (alternates CRS1_SYNC, EVENTOUT, TIM14_CH1). |
| 9 | PF1-OSC_OUT | bidirectional | FT I/O that serves as OSC_OUT, the HSE crystal oscillator output (alternates OSC_EN, EVENTOUT, TIM15_CH1N). |
| 10 | PF2-NRST | bidirectional | Reset pin with embedded weak pull-up, RST structure when configured as reset and FT when configured as GPIO (alternates MCO, LPUART2_TX, LPUART2_RTS_DE). |
| 11 | PA0 | bidirectional | FT_a 5 V-tolerant I/O with analog switch function; alternates include SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, LPTIM1_OUT, COMP1_OUT, additional ADC_IN0, TAMP_IN2, WKUP1. |
| 12 | PA1 | bidirectional | FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_SCK, USART2_RTS_DE_CK, TIM2_CH2, TIM15_CH1N, I2C1_SMBA, additional ADC_IN1 and COMP1_INP2. |
| 13 | PA2 | bidirectional | FT_a I/O with analog switch; alternates include SPI1_MOSI, USART2_TX, TIM2_CH3, UCPD1_FRSTX, LPUART1_TX, COMP2_OUT, additional ADC_IN2, WKUP4, LSCO. |
| 14 | PA3 | bidirectional | FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI2_MISO, USART2_RX, TIM2_CH4, TIM15_CH2, LPUART1_RX, additional ADC_IN3 and COMP2_INP2. |
| 15 | PA4 | bidirectional | TT_a 3.6 V-tolerant I/O with analog switch; alternates include SPI1_NSS, SPI2_MOSI, USART6_TX, TIM14_CH1, LPTIM2_OUT, SPI3_NSS, additional ADC_IN4, DAC1_OUT1, RTC_OUT2. |
| 16 | PA5 | bidirectional | TT_ea 3.6 V-tolerant I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_SCK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, additional ADC_IN5 and DAC1_OUT2. |
| 17 | PA6 | bidirectional | FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_MISO, TIM3_CH1, TIM1_BKIN, USART6_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, additional ADC_IN6. |
| 18 | PA7 | bidirectional | FT_a I/O with analog switch; alternates include SPI1_MOSI, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM17_CH1, COMP2_OUT, I2C2_SCL, I2C3_SCL, additional ADC_IN7. |
| 19 | PB0 | bidirectional | FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI1_NSS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, COMP1_OUT, additional COMP3_INP0 and ADC_IN8. |
| 20 | PB1 | bidirectional | FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, COMP3_OUT, additional COMP1_INM6 and ADC_IN9. |
| 21 | PB2 | bidirectional | FT_ea I/O with analog switch and switchable diode to VDDIOx; alternates include SPI2_MISO, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT, additional COMP1_INP1, COMP3_INM6 and ADC_IN10. |
| 22 | PB10 | bidirectional | FT_fa I/O with analog switch and Fm+ capability; alternates include CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK, I2C2_SCL, COMP1_OUT, additional ADC_IN11. |
| 23 | PB11 | bidirectional | FT_fa I/O with analog switch and Fm+ capability; alternates include SPI2_MOSI, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT, additional ADC_IN15. |
| 24 | PB12 | bidirectional | FT_fa I/O with analog switch and Fm+ capability; alternates include SPI2_NSS, LPUART1_RTS_DE, TIM1_BKIN, FDCAN2_RX, TIM15_BKIN, UCPD2_FRSTX, I2C2_SMBA, additional ADC_IN16. |
| 25 | PB13 | bidirectional | FT_fs I/O supplied from VDDIO2 only; alternates include SPI2_SCK, LPUART1_CTS, TIM1_CH1N, FDCAN2_TX, USART3_CTS, TIM15_CH1N, I2C2_SCL. |
| 26 | PB14 | bidirectional | FT_fs I/O supplied from VDDIO2 only; alternates include SPI2_MISO, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, USART6_RTS_DE_CK. |
| 27 | PB15 | bidirectional | FT_fcs I/O supplied from VDDIO2 only, with possible pull-down on reset depending on PA9-related voltage; alternates include SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, USART6_CTS, additional UCPD1_CC2 and RTC_REFIN. |
| 28 | PA8 | bidirectional | FT_fcs I/O supplied from VDDIO2 only, with possible pull-down on reset depending on PA9 voltage; alternates include MCO, SPI2_NSS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, I2C2_SMBA, additional UCPD1_CC1. |
| 29 | PA9 | bidirectional | FT_fds I/O supplied from VDDIO2 only, with possible pull-down on reset depending on voltage level; alternates include MCO, USART1_TX, TIM1_CH2, SPI2_MISO, TIM15_BKIN, I2C1_SCL, I2C2_SCL, additional UCPD1_DBCC1. |
| 30 | PC6 | bidirectional | FT_s I/O supplied from VDDIO2 only; alternates include UCPD1_FRSTX, TIM3_CH1, TIM2_CH3, LPUART2_TX. |
| 31 | PC7 | bidirectional | FT_s I/O supplied from VDDIO2 only; alternates include UCPD2_FRSTX, TIM3_CH2, TIM2_CH4, LPUART2_RX. |
| 32 | PA10 | bidirectional | FT_fds I/O supplied from VDDIO2 only, with possible pull-down on reset depending on PD1 voltage; alternates include SPI2_MOSI, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, I2C2_SDA, additional UCPD1_DBCC2. |
| 33 | PA11 [PA9] | bidirectional | FT_fus I/O supplied from VDDIO2 only with USB function; alternates include SPI1_MISO, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT, additional USB_DM; can be remapped with PA9 via SYSCFG_CFGR1. |
| 34 | PA12 [PA10] | bidirectional | FT_fus I/O supplied from VDDIO2 only with USB function; alternates include SPI1_MOSI, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT, additional USB_DP; can be remapped with PA10 via SYSCFG_CFGR1. |
| 35 | PA13 | bidirectional | FT_es I/O with switchable diode to VDDIOx; upon reset it is configured as SWDIO with internal pull-up active; alternates include IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. |
| 36 | PA14-BOOT0 | bidirectional | FT_s I/O supplied from VDDIO2 only; upon reset it is configured as SWCLK with internal pull-down active, and it serves as the BOOT0 pin (alternates USART2_TX, EVENTOUT, LPUART2_TX). |
| 37 | PA15 | bidirectional | FT_s I/O supplied from VDDIO2 only; alternates include SPI1_NSS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. |
| 38 | PD0 | bidirectional | FT_cs I/O with USB Type-C CC function and possible pull-down on reset depending on PD1 voltage; alternates include EVENTOUT, SPI2_NSS, TIM16_CH1, FDCAN1_RX, additional UCPD2_CC1. |
| 39 | PD1 | bidirectional | FT_ds I/O with USB Type-C dead battery function and possible pull-down on reset depending on voltage level; alternates include EVENTOUT, SPI2_SCK, TIM17_CH1, FDCAN1_TX, additional UCPD2_DBCC1. |
| 40 | PD2 | bidirectional | FT_cs I/O with USB Type-C CC function and possible pull-down on reset depending on PD3 voltage; alternates include USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, USART5_RX, additional UCPD2_CC2. |
| 41 | PD3 | bidirectional | FT_ds I/O with USB Type-C dead battery function and possible pull-down on reset depending on voltage level; alternates include USART2_CTS, SPI2_MISO, TIM1_CH2N, USART5_TX, additional UCPD2_DBCC2. |
| 42 | PB3 | bidirectional | FT_a I/O with analog switch; alternates include SPI1_SCK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK, additional COMP2_INM6. |
| 43 | PB4 | bidirectional | FT_a I/O with analog switch; alternates include SPI1_MISO, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO, additional COMP2_INP0. |
| 44 | PB5 | bidirectional | FT I/O; alternates include SPI1_MOSI, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI, additional WKUP6. |
| 45 | PB6 | bidirectional | FT_fa I/O with analog switch and Fm+ capability; alternates include USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, USART5_CTS, TIM4_CH1, LPUART2_TX, additional COMP2_INP1. |
| 46 | PB7 | bidirectional | FT_fa I/O with analog switch and Fm+ capability; alternates include USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, TIM4_CH2, LPUART2_RX, additional COMP2_INM7 and PVD_IN. |
| 47 | PB8 | bidirectional | FT_f I/O with Fm+ capability; alternates include CEC, SPI2_SCK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, USART6_TX, TIM4_CH3. |
| 48 | PB9 | bidirectional | FT_f I/O with Fm+ capability; alternates include IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS, I2C1_SDA, USART6_RX, TIM4_CH4. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD (external) | VDD | -0.3 |  | 4 | V |  | 66 |
| External supply voltage for selected I/Os | VDDIO2 | -0.3 |  | 4 | V |  | 66 |
| External supply voltage on VBAT pin | VBAT | -0.3 |  | 4 | V |  | 66 |
| External voltage on VREF+ pin | VREF+ | -0.3 |  |  | V | Printed max is Min(VDD + 0.4, 4.0) | 66 |
| Input voltage on FT_xx pins except FT_c | VIN | -0.3 |  |  | V | Printed max is VDD + 4.0; internal pull-up/pull-down must be disabled above 4 V | 66 |
| Input voltage on FT_c pins | VIN | -0.3 |  | 5.5 | V |  | 66 |
| Input voltage on any other pin | VIN | -0.3 |  | 4 | V |  | 66 |
| Current into VDD/VDDA and VDDIO2 power pins (source) | IVDD/VDDA/VDDIO2 |  |  | 100 | mA |  | 66 |
| Current out of VSS/VSSA and VSS ground pins (sink) | IVSS/VSSA |  |  | 100 | mA |  | 66 |
| Output current sunk by any I/O and control pin except FT_f | IIO(PIN) |  |  | 15 | mA |  | 67 |
| Output current sunk by any FT_f pin | IIO(PIN) |  |  | 20 | mA |  | 67 |
| Output current sourced by any I/O and control pin | IIO(PIN) |  |  | 15 | mA |  | 67 |
| Total output current sunk by sum of all I/Os and control pins | ∑IIO(PIN) |  |  | 80 | mA |  | 67 |
| Total output current sourced by sum of all I/Os and control pins | ∑IIO(PIN) |  |  | 80 | mA |  | 67 |
| Injected current on a FT_xx pin | IINJ(PIN) | -5 |  |  | mA | Printed as -5 / NA; positive injection not possible on FT_xx | 67 |
| Injected current on a TT_a pin | IINJ(PIN) | -5 |  | 0 | mA | Printed as -5 / 0; any injection disturbs analog performance | 67 |
| Total injected current (sum of all I/Os and control pins) | ∑/IINJ(PIN)/ |  |  | 25 | mA |  | 67 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 67 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 67 |
| Internal AHB clock frequency | fHCLK | 0 |  | 64 | MHz |  | 67 |
| Internal APB clock frequency | fPCLK | 0 |  | 64 | MHz |  | 67 |
| Standard operating voltage | VDD | 1.7 |  | 3.6 | V |  | 67 |
| External supply voltage for selected I/Os | VDDIO2 | 1.65 |  | 3.6 | V |  | 67 |
| Analog supply voltage for ADC and COMP operation | VDDA | 1.62 |  | 3.6 | V | For ADC and COMP operation | 67 |
| Analog supply voltage for DAC operation | VDDA | 1.8 |  | 3.6 | V | For DAC operation | 67 |
| Analog supply voltage for VREFBUF operation | VDDA | 2.4 |  | 3.6 | V | For VREFBUF operation | 67 |
| Backup operating voltage | VBAT | 1.55 |  | 3.6 | V |  | 67 |
| I/O input voltage (all except RST, TT_xx and FT_c) | VIN | -0.3 |  |  | V | Printed max is Min(VDD + 3.6, 5.5) | 68 |
| I/O input voltage RST pin | VIN | -0.3 |  |  | V | Printed max is VDD + 0.3 | 68 |
| I/O input voltage TT_xx pins | VIN | -0.3 |  |  | V | Printed max is VDDA + 0.3 | 68 |
| I/O input voltage FT_c pins | VIN | -0.3 |  | 5 | V |  | 68 |
| Ambient temperature, suffix 6 | TA | -40 |  | 85 | °C | Temperature range digit 6 in order code | 68 |
| Junction temperature, suffix 6 | TJ | -40 |  | 105 | °C | Temperature range digit 6 in order code | 68 |
| Power-on reset threshold | VPOR | 1.62 | 1.66 | 1.7 | V |  | 68 |
| Power-down reset threshold | VPDR | 1.6 | 1.64 | 1.69 | V |  | 68 |
| Brownout reset threshold 1 (rising) | VBOR1 | 2.05 | 2.1 | 2.18 | V | VDD rising | 68 |
| Brownout reset threshold 1 (falling) | VBOR1 | 1.95 | 2 | 2.08 | V | VDD falling | 68 |
| Brownout reset threshold 2 (rising) | VBOR2 | 2.2 | 2.31 | 2.38 | V | VDD rising | 69 |
| Brownout reset threshold 2 (falling) | VBOR2 | 2.1 | 2.21 | 2.28 | V | VDD falling | 69 |
| Brownout reset threshold 3 (rising) | VBOR3 | 2.5 | 2.62 | 2.68 | V | VDD rising | 69 |
| Brownout reset threshold 3 (falling) | VBOR3 | 2.4 | 2.52 | 2.58 | V | VDD falling | 69 |
| Brownout reset threshold 4 (rising) | VBOR4 | 2.8 | 2.91 | 3 | V | VDD rising | 69 |
| Brownout reset threshold 4 (falling) | VBOR4 | 2.7 | 2.81 | 2.9 | V | VDD falling | 69 |
| Internal reference voltage | VREFINT | 1.182 | 1.212 | 1.232 | V | -40°C < TJ < 130°C | 70 |
| Internal reference voltage temperature coefficient | TCoeff_vrefint |  | 30 | 50 | ppm/°C |  | 70 |
| Internal reference voltage voltage coefficient | VDDCoeff |  | 250 | 1200 | ppm/V | 3.0 V < VDD < 3.6 V | 70 |
| Supply current in Standby mode, 25 °C | IDD(Standby) |  | 0.3 | 1.8 | µA | RTC disabled; VDD = 3.6 V; 25 °C | 75 |
| Supply current in Standby mode, 85 °C | IDD(Standby) |  | 3.5 | 21 | µA | RTC disabled; VDD = 3.6 V; 85 °C | 75 |
| Supply current in Run mode (from flash memory), 64 MHz, 25 °C | IDD(Run) |  | 8.6 | 9 | mA | Range 1; PLL enabled; fHCLK = 64 MHz; flash memory; 25 °C | 72 |
| User external clock source frequency, Range 1 | fHSE_ext | 8 |  | 48 | MHz | Voltage scaling Range 1 | 81 |
| User external clock source frequency, Range 2 | fHSE_ext | 8 |  | 26 | MHz | Voltage scaling Range 2 | 81 |
| HSE oscillator frequency | fOSC_IN | 4 | 8 | 48 | MHz |  | 83 |
| HSI16 frequency | fHSI16 | 15.88 |  | 16.08 | MHz | VDD = 3.0 V, TA = 30 °C | 86 |
| HSI16 oscillator frequency drift over temperature | ∆Temp(HSI16) | -1 |  | 1 | % | TA = 0 to 85 °C | 86 |
| Accuracy of the HSI48 oscillator over temperature (factory calibrated) | ACCHSI48_REL | -3 |  | 3 | % | VDD = 3.0 V to 3.6 V, TA = -15 to 85 °C | 87 |
| LSI frequency | fLSI | 29.5 |  | 34 | kHz | VDD = 1.62 V to 3.6 V, TA = -40 to 125 °C | 88 |
| Wakeup time from Standby mode | tWUSTBY |  | 14.5 | 30 | µs | Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 | 80 |
| Wakeup time from Shutdown mode | tWUSHDN |  | 258 | 340 | µs | Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 | 81 |
| PLL input clock frequency | fPLL_IN | 2.66 |  | 16 | MHz |  | 88 |

## CAD (KiCad official)

- Symbol: `STM32G0B1CCT6`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm32g0b1cct6-etched.step` / `stm32g0b1cct6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32g0b1cct6.step` / `stm32g0b1cct6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603032934681501696) (160 pp, sha256 `c0903d327169522e`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32g0b1cct6-datasheet.pdf)