component
STM32G0B1CBT6N
Public Made by Adomby adom
STMicroelectronics Integrated Circuits (ICs), 48-LQFP. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
Generated by adom_assets · KiCad file format 20240108
STM32G0B1CBT6N
STMicroelectronics · Integrated Circuits (ICs) · 48-LQFP
STM32G0B1CBT6N from STMicroelectronics, in a 48-LQFP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data). The symbol is generated from that pin table, the footprint is an Adom_Gen land derived from the manufacturer drawing, and the 3D model is generated to fit it.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC13 | bidirectional | PC13 is a 5 V tolerant GPIO supplied through the power switch with a 3 mA limit, so it must not exceed 2 MHz at 30 pF in output mode and can only sink current; it also provides TIM1_BKIN, RTC_TS, RTC_OUT1 and WKUP2. |
| 2 | PC14-OSC32_IN | bidirectional | PC14 is a 5 V tolerant GPIO supplied through the power switch with a 3 mA limit that can only sink current in output mode, and it doubles as the 32.768 kHz oscillator input OSC32_IN. |
| 3 | PC15-OSC32_OUT | bidirectional | PC15 is a 5 V tolerant GPIO supplied through the power switch with a 3 mA limit that can only sink current in output mode, and it doubles as the 32.768 kHz oscillator output OSC32_OUT. |
| 4 | VBAT | power_in | VBAT supplies the RTC, TAMP, the low-speed 32.768 kHz oscillator and backup registers from 1.55 V to 3.6 V when VDD is not present. |
| 5 | VREF+ | power_in | VREF+ is the analog reference input or internal buffer output and must equal VDDA when VDDA is below 2 V, or lie between 2 V and VDDA when VDDA is 2 V or above. |
| 6 | VDD/VDDA | power_in | VDD/VDDA is the main 1.7 V to 3.6 V supply for the internal regulator, the I/O ring and the analog blocks. |
| 7 | VSS/VSSA | power_in | VSS/VSSA is the ground reference for the digital and analog supplies. |
| 8 | PF0-OSC_IN | bidirectional | PF0 is a 5 V tolerant FT I/O that doubles as the high-speed crystal oscillator input OSC_IN. |
| 9 | PF1-OSC_OUT | bidirectional | PF1 is a 5 V tolerant FT I/O that doubles as the high-speed crystal oscillator output OSC_OUT. |
| 10 | PF2-NRST | bidirectional | PF2 is an RST-type I/O with embedded weak pull-up that acts as the NRST reset input when configured as reset, and as a 5 V tolerant FT GPIO otherwise. |
| 11 | PA0 | bidirectional | PA0 is a 5 V tolerant FT_a I/O with an analog switch function that also serves as ADC input ADC_IN0, TAMP_IN2 and WKUP1. |
| 12 | PA1 | bidirectional | PA1 is a 5 V tolerant FT_ea I/O with a switchable diode to VDDIOx and an analog switch function that also serves as ADC input ADC_IN1. |
| 13 | PA2 | bidirectional | PA2 is a 5 V tolerant FT_a I/O with an analog switch function that also serves as ADC_IN2 and WKUP4. |
| 14 | PA3 | bidirectional | PA3 is a 5 V tolerant FT_ea I/O with a switchable diode to VDDIOx and an analog switch function that also serves as ADC_IN3. |
| 15 | PA4 | bidirectional | PA4 is a 3.6 V tolerant TT_a I/O with an analog switch function that also serves as ADC_IN4 and DAC1_OUT1. |
| 16 | PA5 | bidirectional | PA5 is a 3.6 V tolerant TT_ea I/O with a switchable diode to VDDIOx and an analog switch function that also serves as ADC_IN5 and DAC1_OUT2. |
| 17 | PA6 | bidirectional | PA6 is a 5 V tolerant FT_ea I/O with a switchable diode to VDDIOx and an analog switch function that also serves as ADC_IN6. |
| 18 | PA7 | bidirectional | PA7 is a 5 V tolerant FT_a I/O with an analog switch function that also serves as ADC_IN7. |
| 19 | PB0 | bidirectional | PB0 is a 5 V tolerant FT_ea I/O with a switchable diode to VDDIOx and an analog switch function that also serves as ADC_IN8 and COMP3_INP0. |
| 20 | PB1 | bidirectional | PB1 is a 5 V tolerant FT_ea I/O with a switchable diode to VDDIOx and an analog switch function that also serves as ADC_IN9 and COMP1_INM6. |
| 21 | PB2 | bidirectional | PB2 is a 5 V tolerant FT_ea I/O with a switchable diode to VDDIOx and an analog switch function that also serves as ADC_IN10. |
| 22 | PB10 | bidirectional | PB10 is a 5 V tolerant FT_fa I/O with Fm+ capability and an analog switch function that also serves as ADC_IN11. |
| 23 | PB11 | bidirectional | PB11 is a 5 V tolerant FT_fa I/O with Fm+ capability and an analog switch function that also serves as ADC_IN15. |
| 24 | PB12 | bidirectional | PB12 is a 5 V tolerant FT_fa I/O with Fm+ capability and an analog switch function that also serves as ADC_IN16. |
| 25 | PB13 | bidirectional | PB13 is a 5 V tolerant FT_fs I/O with Fm+ capability that is supplied from VDDIO2 only. |
| 26 | PB14 | bidirectional | PB14 is a 5 V tolerant FT_fs I/O with Fm+ capability that is supplied from VDDIO2 only. |
| 27 | PB15 | bidirectional | PB15 is a 5 V tolerant FT_fcs I/O with Fm+ and USB Type-C PD capability that is supplied from VDDIO2 only, and may have a pull-down present at reset depending on PD1. |
| 28 | PA8 | bidirectional | PA8 is a 5 V tolerant FT_fcs I/O with Fm+ and USB Type-C PD capability that is supplied from VDDIO2 only, and may have a pull-down present at reset depending on PA9. |
| 29 | PA9 | bidirectional | PA9 is a 5 V tolerant FT_fds I/O with Fm+ and USB Type-C dead-battery capability that is supplied from VDDIO2 only and can be remapped in place of PA11. |
| 30 | VSS | power_in | VSS is a ground pin of the device. |
| 31 | VDDIO2 | power_in | VDDIO2 is the separate I/O supply from 1.65 V to 3.6 V for selected I/Os and VDDUSB and must not be applied without valid VDD. |
| 32 | PA10 | bidirectional | PA10 is a 5 V tolerant FT_fds I/O with Fm+ and USB Type-C dead-battery capability that is supplied from VDDIO2 only and can be remapped in place of PA12. |
| 33 | PA11 [PA9] | bidirectional | PA11 is a 5 V tolerant FT_fus I/O with Fm+ and USB function that is supplied from VDDIO2 and carries the USB_DM signal. |
| 34 | PA12 [PA10] | bidirectional | PA12 is a 5 V tolerant FT_fus I/O with Fm+ and USB function that is supplied from VDDIO2 and carries the USB_DP signal. |
| 35 | PA13 | bidirectional | PA13 is a 5 V tolerant FT_es I/O with a switchable diode to VDDIOx that is configured as SWDIO with an internal pull-up after reset. |
| 36 | PA14-BOOT0 | bidirectional | PA14 is a 5 V tolerant FT_s I/O supplied from VDDIO2 only that is configured as SWCLK with an internal pull-down after reset and is shared with the BOOT0 pin. |
| 37 | PA15 | bidirectional | PA15 is a 5 V tolerant FT_s I/O supplied from VDDIO2 only with alternate functions including SPI1_NSS, USART2_RX and USB_NOE. |
| 38 | PD0 | bidirectional | PD0 is a 5 V tolerant FT_cs I/O with USB Type-C PD capability that is supplied from VDDIO2 only and may have a pull-down present at reset. |
| 39 | PD1 | bidirectional | PD1 is a 5 V tolerant FT_ds I/O with USB Type-C dead-battery capability that is supplied from VDDIO2 only and may have a pull-down present at reset. |
| 40 | PD2 | bidirectional | PD2 is a 5 V tolerant FT_cs I/O with USB Type-C PD capability that is supplied from VDDIO2 only and may have a pull-down present at reset. |
| 41 | PD3 | bidirectional | PD3 is a 5 V tolerant FT_ds I/O with USB Type-C dead-battery capability that is supplied from VDDIO2 only and may have a pull-down present at reset. |
| 42 | PB3 | bidirectional | PB3 is a 5 V tolerant FT_a I/O with an analog switch function that also serves as COMP2_INM6. |
| 43 | PB4 | bidirectional | PB4 is a 5 V tolerant FT_a I/O with an analog switch function that also serves as COMP2_INP0. |
| 44 | PB5 | bidirectional | PB5 is a 5 V tolerant FT I/O that also serves as WKUP6. |
| 45 | PB6 | bidirectional | PB6 is a 5 V tolerant FT_fa I/O with Fm+ capability and an analog switch function that also serves as COMP2_INP1. |
| 46 | PB7 | bidirectional | PB7 is a 5 V tolerant FT_fa I/O with Fm+ capability and an analog switch function that also serves as COMP2_INM7 and PVD_IN. |
| 47 | PB8 | bidirectional | PB8 is a 5 V tolerant FT_f I/O with Fm+ capability. |
| 48 | PB9 | bidirectional | PB9 is a 5 V tolerant FT_f I/O with Fm+ capability that also serves as IR_OUT and TIM17_CH1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | 48-LQFP |
| Category | Integrated Circuits (ICs) |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External supply voltage | VDD | -0.3 | 4 | V | 66 | ||
| External supply voltage for selected I/Os | VDDIO2 | -0.3 | 4 | V | 66 | ||
| External supply voltage on VBAT pin | VBAT | -0.3 | 4 | V | 66 | ||
| Input voltage on any other pin | VIN | -0.3 | 4 | V | Input voltage on any other pin | 66 | |
| Current into VDD/VDDA and VDDIO2 power pins (source) | IVDD/VDDA,VDDIO2 | 100 | mA | 66 | |||
| Current out of VSS/VSSA and VSS ground pins (sink) | IVSS/VSSA,VSS | 100 | mA | 66 | |||
| Output current sunk by any I/O and control pin except FT_f | IIO(PIN) | 15 | mA | 67 | |||
| Output current sunk by any FT_f pin | IIO(PIN) | 20 | mA | 67 | |||
| Total output current sunk by sum of all I/Os and control pins | ∑IIO(PIN) | 80 | mA | 67 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 67 | ||
| Maximum junction temperature | TJ | 150 | °C | 67 | |||
| Internal AHB clock frequency | fHCLK | 0 | 64 | MHz | 67 | ||
| Internal APB clock frequency | fPCLK | 0 | 64 | MHz | 67 | ||
| Standard operating voltage | VDD | 1.7 | 3.6 | V | 67 | ||
| External supply voltage for selected I/Os | VDDIO2 | 1.65 | 3.6 | V | 67 | ||
| Analog supply voltage | VDDA | 1.62 | 3.6 | V | For ADC and COMP operation | 67 | |
| Analog supply voltage | VDDA | 1.8 | 3.6 | V | For DAC operation | 67 | |
| Analog supply voltage | VDDA | 2.4 | 3.6 | V | For VREFBUF operation | 67 | |
| Backup operating voltage | VBAT | 1.55 | 3.6 | V | 67 | ||
| Ambient temperature | TA | -40 | 85 | °C | Suffix 6 | 68 | |
| Junction temperature | TJ | -40 | 105 | °C | Suffix 6 | 68 | |
| POR temporization when VDD crosses VPOR | tRSTTEMPO | 250 | 400 | µs | VDD rising | 68 | |
| Power-on reset threshold | VPOR | 1.62 | 1.66 | 1.7 | V | 68 | |
| Power-down reset threshold | VPDR | 1.6 | 1.64 | 1.69 | V | 68 | |
| Brownout reset threshold 1 | VBOR1 | 2.05 | 2.1 | 2.18 | V | VDD rising | 68 |
| Brownout reset threshold 1 | VBOR1 | 1.95 | 2 | 2.08 | V | VDD falling | 68 |
| Brownout reset threshold 2 | VBOR2 | 2.2 | 2.31 | 2.38 | V | VDD rising | 69 |
| Brownout reset threshold 2 | VBOR2 | 2.1 | 2.21 | 2.28 | V | VDD falling | 69 |
| Brownout reset threshold 3 | VBOR3 | 2.5 | 2.62 | 2.68 | V | VDD rising | 69 |
| Brownout reset threshold 3 | VBOR3 | 2.4 | 2.52 | 2.58 | V | VDD falling | 69 |
| Brownout reset threshold 4 | VBOR4 | 2.8 | 2.91 | 3 | V | VDD rising | 69 |
| Brownout reset threshold 4 | VBOR4 | 2.7 | 2.81 | 2.9 | V | VDD falling | 69 |
| Internal reference voltage | VREFINT | 1.182 | 1.212 | 1.232 | V | -40°C < TJ < 130°C | 70 |
| 1/4 reference voltage | VREFINT_DIV1 | 24 | 25 | 26 | % | % VREFINT | 70 |
| 1/2 reference voltage | VREFINT_DIV2 | 49 | 50 | 51 | % | % VREFINT | 70 |
| 3/4 reference voltage | VREFINT_DIV3 | 74 | 75 | 76 | % | % VREFINT | 70 |
| Supply current in Run mode (from flash memory) | IDD(Run) | 8.6 | 9 | mA | Range 1; PLL enabled; fHCLK 64 MHz; flash memory; typ 25 °C, max 25 °C | 72 | |
| Supply current in Low-power run mode (from flash memory) | IDD(LPRun) | 280 | 415 | µA | PLL disabled; fHCLK 2 MHz; flash memory; typ 25 °C, max 25 °C | 72 | |
| Supply current in Sleep mode | IDD(Sleep) | 1.9 | 2.5 | mA | Range 1; fHCLK 64 MHz; all peripherals disabled; typ 25 °C, max 25 °C | 74 | |
| Supply current in Low-power sleep mode | IDD(LPSleep) | 70 | 175 | µA | Flash memory disabled; PLL disabled; fHCLK 2 MHz; typ 25 °C, max 25 °C | 74 | |
| Supply current in Stop 0 mode | IDD(Stop 0) | 295 | 375 | µA | HSI kernel enabled; VDD 3 V; typ 25 °C, max 25 °C | 74 | |
| Supply current in Standby mode | IDD(Standby) | 0.2 | 1.4 | µA | RTC disabled; VDD 3.0 V; typ 25 °C, max 25 °C | 75 | |
| Supply current in Shutdown mode | IDD(Shutdown) | 38 | 370 | nA | RTC disabled; VDD 3.0 V; typ 25 °C, max 25 °C | 76 | |
| Wakeup time from Sleep to Run mode | tWUSLEEP | 11 | 11 | CPU cycles | 80 | ||
| Wakeup time from Stop 0 (flash not powered) | tWUSTOP0 | 5.6 | 6 | µs | Transiting to Run-mode execution in flash memory not powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2 | 80 | |
| Wakeup time from Standby mode | tWUSTBY | 14.5 | 30 | µs | Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 | 80 | |
| Wakeup time from Shutdown mode | tWUSHDN | 258 | 340 | µs | Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 | 81 | |
| User external clock source frequency (HSE) | fHSE_ext | 8 | 48 | MHz | Voltage scaling Range 1 | 81 | |
| User external clock source frequency (HSE) | fHSE_ext | 8 | 26 | MHz | Voltage scaling Range 2 | 81 | |
| HSE oscillator frequency | fOSC_IN | 4 | 8 | 48 | MHz | 83 | |
| HSI16 frequency | fHSI16 | 15.88 | 16.08 | MHz | VDD=3.0 V, TA=30 °C | 86 | |
| LSI frequency | fLSI | 31.04 | 32.96 | kHz | VDD = 3.0 V, TA = 30 °C | 88 | |
| LSI frequency | fLSI | 29.5 | 34 | kHz | VDD = 1.62 V to 3.6 V, TA = -40 to 125 °C | 88 | |
| PLL input clock frequency | fPLL_IN | 2.66 | 16 | MHz | 88 | ||
| PLL input clock duty cycle | DPLL_IN | 45 | 55 | % | 88 | ||
| PLL VCO output | fVCO_OUT | 96 | 344 | MHz | Voltage scaling Range 1 | 88 | |
| PLL VCO output | fVCO_OUT | 96 | 128 | MHz | Voltage scaling Range 2 | 88 | |
| Endurance | NEND | 10 | kcycles | TA = -40 to +105 °C | 89 |
CAD (Adom-generated)
- Symbol:
STM32G0B1CBT6N - Footprint:
Adom_Gen:STMicroelectronics_STM32_ccff95 - 3D model: generated to fit the land (STEP)
- 3D model files:
stm32g0b1cbt6n-etched.step/stm32g0b1cbt6n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32g0b1cbt6n.step/stm32g0b1cbt6n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (165 pp, sha256
8433e47bc5da5cac, retrieved 2026-11-13, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: symbol generated from the datasheet pin table; footprint an Adom_Gen land derived from the manufacturer drawing; 3D model generated to fit that land.