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STM32G071KBU3

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32G071KBU3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-32(5x5)

STM32G071KBU3 from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB9 bidirectional Fm+-capable 5 V tolerant (FT_f) I/O with alternate functions IR_OUT, UCPD2_FRSTX, TIM17_CH1, USART3_RX, SPI2_NSS, I2C1_SDA and EVENTOUT.
2 PC14-OSC32_IN bidirectional 5 V tolerant (FT) I/O on the power-switch supply, limited to a 3 mA sink, no more than 2 MHz at 30 pF in output mode and not to be used as a current source; it is also the OSC32_IN LSE oscillator input.
3 PC15-OSC32_OUT bidirectional 5 V tolerant (FT) I/O on the power-switch supply, limited to a 3 mA sink, no more than 2 MHz at 30 pF in output mode and not to be used as a current source; it is also the OSC32_OUT LSE oscillator output.
4 VDD/VDDA power_in Standard operating supply 1.7 V to 3.6 V, also the analog supply VDDA (1.62 V minimum for ADC and COMP, 1.8 V for DAC, 2.4 V for VREFBUF) on the same pin.
5 VSS/VSSA power_in Ground reference pin for digital and analog circuits; all voltages are referenced to VSS.
6 PF2-NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor, also usable as PF2 I/O (FT) with MCO alternate function.
7 PA0 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN0, COMP1_INM, WKUP1, USART2_CTS, SPI2_SCK, USART4_TX, LPTIM1_OUT and COMP1_OUT alternate functions.
8 PA1 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN1, COMP1_INP, SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, USART4_RX, TIM15_CH1N, I2C1_SMBA and EVENTOUT alternate functions.
9 PA2 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN2, COMP2_INM, WKUP4, LSCO, SPI1_MOSI/I2S1_SD, USART2_TX, LPUART1_TX and COMP2_OUT alternate functions.
10 PA3 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN3, COMP2_INP, SPI2_MISO, USART2_RX, TIM2_CH4, LPUART1_RX and EVENTOUT alternate functions.
11 PA4 bidirectional 3.6 V tolerant I/O with analog switch function (TT_a), with ADC_IN4, DAC_OUT1, SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT and EVENTOUT alternate functions.
12 PA5 bidirectional 3.6 V tolerant I/O with analog switch function (TT_a), with ADC_IN5, DAC_OUT2, SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART3_TX, LPTIM2_ETR and EVENTOUT alternate functions.
13 PA6 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN6, SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART3_CTS, TIM16_CH1, LPUART1_CTS and COMP1_OUT alternate functions.
14 PA7 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN7, SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX and COMP2_OUT alternate functions.
15 PB0 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN8, SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX and COMP1_OUT alternate functions.
16 PB1 bidirectional 5 V tolerant I/O with analog switch function (FT_a), with ADC_IN9, COMP1_INM, TIM14_CH1, TIM3_CH4, TIM1_CH3N, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE and EVENTOUT alternate functions.
17 PB2 bidirectional 5 V tolerant I/O with analog switch function (FT_a) on the GP version, with ADC_IN10, COMP1_INP, SPI2_MISO, USART3_TX, LPTIM1_OUT and EVENTOUT alternate functions.
18 PA8 bidirectional 5 V tolerant I/O (FT_c, USB Type-C PD capable) with MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT, EVENTOUT and UCPD1_CC1 alternate functions; a reset-time pull-down may be present depending on PB0 level, removable by strobing UCPD1_STROBE in SYSCFG_CFGR1.
19 PA9 bidirectional Fm+-capable 5 V tolerant I/O with dead-battery function (FT_fd, USB Type-C PD) with MCO, USART1_TX, TIM1_CH2, SPI2_MISO, TIM15_BKIN, I2C1_SCL, EVENTOUT and UCPD1_DBCC1 alternate functions; can be remapped in place of PA11 via SYSCFG_CFGR1.
20 PC6 bidirectional 5 V tolerant I/O (FT) with UCPD1_FRSTX, TIM3_CH1 and TIM2_CH3 alternate functions.
21 PA10 bidirectional Fm+-capable 5 V tolerant I/O with dead-battery function (FT_fd, USB Type-C PD) with SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA, EVENTOUT and UCPD1_DBCC2 alternate functions; can be remapped in place of PA12 via SYSCFG_CFGR1.
22 PA11 [PA9] bidirectional Fm+-capable 5 V tolerant I/O (FT_f) with SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL and COMP1_OUT alternate functions; default mapping is PA11, remappable as PA9 via SYSCFG_CFGR1.
23 PA12 [PA10] bidirectional Fm+-capable 5 V tolerant I/O (FT_f) with SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA and COMP2_OUT alternate functions; default mapping is PA12, remappable as PA10 via SYSCFG_CFGR1.
24 PA13 bidirectional 5 V tolerant I/O (FT) that after reset is the SWDIO debug function with internal pull-up enabled; also IR_OUT and EVENTOUT alternate functions.
25 PA14-BOOT0 bidirectional 5 V tolerant I/O (FT) that after reset is the SWCLK debug function with internal pull-down enabled; it is also the BOOT0 boot-mode pin when enabled through the boot selector option bit, and has USART2_TX and EVENTOUT alternate functions.
26 PA15 bidirectional 5 V tolerant I/O (FT) on the GP version with SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, USART4_RTS_DE_CK, USART3_RTS_DE_CK and EVENTOUT alternate functions.
27 PB3 bidirectional 5 V tolerant I/O with analog switch function (FT_a) on the GP version, with COMP2_INM, SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK and EVENTOUT alternate functions.
28 PB4 bidirectional 5 V tolerant I/O with analog switch function (FT_a) on the GP version, with COMP2_INP, SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT alternate functions.
29 PB5 bidirectional 5 V tolerant I/O (FT) on the GP version with SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT and WKUP6 functions.
30 PB6 bidirectional Fm+-capable 5 V tolerant I/O with analog switch function (FT_fa) with USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT and COMP2_INP alternate functions.
31 PB7 bidirectional Fm+-capable 5 V tolerant I/O with analog switch function (FT_fa) with USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, COMP2_INM and PVD_IN alternate functions.
32 PB8 bidirectional Fm+-capable 5 V tolerant I/O (FT_f) with CEC, SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN, I2C1_SCL and EVENTOUT alternate functions.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: STM32G071KBU3
  • Footprint: Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
  • 3D model: UFQFPN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: stm32g071kbu3-etched.step / stm32g071kbu3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g071kbu3.step / stm32g071kbu3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (133 pp, sha256 96d7e9ca1500e794, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF