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STM32G071KBT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32g071kbt6factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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STM32G071KBT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM32G071KBT6 from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB9 bidirectional FT_f 5 V-tolerant Fm+-capable I/O with alternate functions IR_OUT, UCPD2_FRSTX, TIM17_CH1, USART3_RX, SPI2_NSS, I2C1_SDA, EVENTOUT.
2 PC14-OSC32_IN bidirectional FT I/O (PC14 at reset) that is the LSE 32.768 kHz oscillator input (OSC32_IN, also OSC_IN) or TIM1_BKIN2; supplied via power switch, output limited to 2 MHz with 30 pF max load and not usable as current source.
3 PC15-OSC32_OUT bidirectional FT I/O (PC15 at reset) that is the LSE oscillator output (OSC32_OUT) with alternate functions OSC32_EN, OSC_EN, TIM15_BKIN; supplied via power switch, output limited to 2 MHz with 30 pF max load.
4 VDD/VDDA power_in Supply pin for I/Os, internal regulator and analog (ADC, DAC, COMP) domains, 1.7 V to 3.6 V, decoupled with 100 nF + 4.7 µF; VBAT and VREF+ are internally connected to it on this package.
5 VSS/VSSA power_in Common digital and analog ground pin.
6 PF2-NRST bidirectional Bidirectional reset pin with embedded weak pull-up (FT, RST structure), also usable as PF2 with MCO alternate function.
7 PA0 bidirectional FT_a I/O with SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT alternate functions and COMP1_INM, ADC_IN0, TAMP_IN2, WKUP1 additional functions.
8 PA1 bidirectional FT_a I/O with SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT and additional functions COMP1_INP, ADC_IN1.
9 PA2 bidirectional FT_a I/O with SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT and additional functions COMP2_INM, ADC_IN2, WKUP4, LSCO.
10 PA3 bidirectional FT_a I/O with SPI2_MISO, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT and additional functions COMP2_INP, ADC_IN3.
11 PA4 bidirectional TT_a (3.6 V tolerant) I/O with SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT and additional functions ADC_IN4, DAC_OUT1, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2.
12 PA5 bidirectional TT_a (3.6 V tolerant) I/O with SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT and additional functions ADC_IN5, DAC_OUT2.
13 PA6 bidirectional FT_a I/O with SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT and additional function ADC_IN6.
14 PA7 bidirectional FT_a I/O with SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT and additional function ADC_IN7.
15 PB0 bidirectional FT_a I/O with SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT and additional function ADC_IN8.
16 PB1 bidirectional FT_a I/O with TIM14_CH1, TIM3_CH4, TIM1_CH3N, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, EVENTOUT and additional functions COMP1_INM, ADC_IN9.
17 PB2 bidirectional FT_a I/O with SPI2_MISO, USART3_TX, LPTIM1_OUT, EVENTOUT and additional functions COMP1_INP, ADC_IN10.
18 PA8 bidirectional FT_c USB Type-C PD capable I/O with MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT, EVENTOUT and additional function UCPD1_CC1; a pull-down may be present upon reset.
19 PA9 bidirectional FT_fd Fm+-capable, USB Type-C dead-battery I/O with MCO, USART1_TX, TIM1_CH2, SPI2_MISO, TIM15_BKIN, I2C1_SCL, EVENTOUT and additional function UCPD1_DBCC1; can be remapped in place of PA11.
20 PC6 bidirectional FT I/O with UCPD1_FRSTX, TIM3_CH1, TIM2_CH3 alternate functions.
21 PA10 bidirectional FT_fd Fm+-capable, USB Type-C dead-battery I/O with SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA, EVENTOUT and additional function UCPD1_DBCC2; can be remapped in place of PA12.
22 PA11 [PA9] bidirectional FT_f Fm+-capable I/O with SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL, COMP1_OUT; PA9 can be remapped onto this pin via SYSCFG_CFGR1.
23 PA12 [PA10] bidirectional FT_f Fm+-capable I/O with SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA, COMP2_OUT; PA10 can be remapped onto this pin via SYSCFG_CFGR1.
24 PA13 bidirectional FT I/O that is SWDIO at reset (internal pull-up active) with IR_OUT and EVENTOUT alternate functions.
25 PA14-BOOT0 bidirectional FT I/O that is SWCLK at reset (internal pull-down active) and the BOOT0 boot selection input, with USART2_TX and EVENTOUT alternate functions.
26 PA15 bidirectional FT I/O with SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, USART4_RTS_DE_CK, USART3_RTS_DE_CK, EVENTOUT alternate functions.
27 PB3 bidirectional FT_a I/O with SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK, EVENTOUT and additional function COMP2_INM.
28 PB4 bidirectional FT_a I/O with SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN, EVENTOUT and additional function COMP2_INP.
29 PB5 bidirectional FT I/O with SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT and additional function WKUP6.
30 PB6 bidirectional FT_fa Fm+-capable I/O with USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT and additional function COMP2_INP.
31 PB7 bidirectional FT_fa Fm+-capable I/O with USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT and additional functions COMP2_INM, PVD_IN.
32 PB8 bidirectional FT_f Fm+-capable I/O with CEC, SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

CAD (KiCad official)

  • Symbol: STM32G071KBT6
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32g071kbt6-etched.step / stm32g071kbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g071kbt6.step / stm32g071kbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (133 pp, sha256 96d7e9ca1500e794, retrieved 2026-09-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF