component
STM32G071C8U3
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32G071C8U3
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32G071C8U3 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC13 | bidirectional | 5 V-tolerant GPIO supplied via the power switch (output limited to 2 MHz, 30 pF, no LED drive); alternate TIM1_BKIN, additional TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. |
| 2 | PC14-OSC32_IN | bidirectional | 5 V-tolerant GPIO (PC14) supplied via the power switch, also the 32 kHz LSE oscillator input OSC32_IN; alternate TIM1_BKIN2. |
| 3 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant GPIO (PC15) supplied via the power switch, also the 32 kHz LSE oscillator output OSC32_OUT; alternates OSC32_EN, OSC_EN, TIM15_BKIN. |
| 4 | VBAT | power_in | Backup supply (1.55 V to 3.6 V) for RTC, TAMP, LSE oscillator and backup registers when VDD is not present. |
| 5 | VREF+ | power_in | Analog reference voltage input or output of the internal voltage reference buffer (VREF_OUT); must equal VDDA when VDDA < 2 V, between 2 V and VDDA otherwise. |
| 6 | VDD/VDDA | power_in | Digital and analog supply pin, 1.7 V to 3.6 V, to be decoupled with 100 nF + 4.7 µF ceramic capacitors placed close to the pin. |
| 7 | VSS/VSSA | power_in | Digital and analog ground pin. |
| 8 | PF0-OSC_IN | bidirectional | 5 V-tolerant GPIO (PF0) and HSE crystal oscillator input OSC_IN; alternate TIM14_CH1. |
| 9 | PF1-OSC_OUT | bidirectional | 5 V-tolerant GPIO (PF1) and HSE crystal oscillator output OSC_OUT; alternates OSC_EN, TIM15_CH1N. |
| 10 | PF2-NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up (NRST), also GPIO PF2 with MCO alternate function. |
| 11 | PA0 | bidirectional | 5 V-tolerant GPIO with analog function; SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, COMP1_OUT, COMP1_INM, ADC_IN0, TAMP_IN2, WKUP1. |
| 12 | PA1 | bidirectional | 5 V-tolerant GPIO with analog function; SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, I2C1_SMBA, COMP1_INP, ADC_IN1. |
| 13 | PA2 | bidirectional | 5 V-tolerant GPIO with analog function; SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, LPUART1_TX, COMP2_OUT, COMP2_INM, ADC_IN2, WKUP4, LSCO. |
| 14 | PA3 | bidirectional | 5 V-tolerant GPIO with analog function; SPI2_MISO, USART2_RX, TIM2_CH4, LPUART1_RX, COMP2_INP, ADC_IN3. |
| 15 | PA4 | bidirectional | 3.6 V-tolerant (TT) GPIO with analog function; SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT, ADC_IN4, DAC_OUT1, RTC_OUT2. |
| 16 | PA5 | bidirectional | 3.6 V-tolerant (TT) GPIO with analog function; SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART3_TX, LPTIM2_ETR, ADC_IN5, DAC_OUT2. |
| 17 | PA6 | bidirectional | 5 V-tolerant GPIO with analog function; SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, ADC_IN6. |
| 18 | PA7 | bidirectional | 5 V-tolerant GPIO with analog function; SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1, COMP2_OUT, ADC_IN7. |
| 19 | PB0 | bidirectional | 5 V-tolerant GPIO with analog function; SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX, LPTIM1_OUT, COMP1_OUT, ADC_IN8. |
| 20 | PB1 | bidirectional | 5 V-tolerant GPIO with analog function; TIM14_CH1, TIM3_CH4, TIM1_CH3N, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP1_INM, ADC_IN9. |
| 21 | PB2 | bidirectional | 5 V-tolerant GPIO with analog function; SPI2_MISO, USART3_TX, LPTIM1_OUT, COMP1_INP, ADC_IN10. |
| 22 | PB10 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog function; CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK, I2C2_SCL, COMP1_OUT, ADC_IN11. |
| 23 | PB11 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog function; SPI2_MOSI, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT, ADC_IN15. |
| 24 | PB12 | bidirectional | 5 V-tolerant GPIO with analog function; SPI2_NSS, LPUART1_RTS_DE, TIM1_BKIN, TIM15_BKIN, ADC_IN16. |
| 25 | PB13 | bidirectional | 5 V-tolerant Fm+ capable GPIO; SPI2_SCK, LPUART1_CTS, TIM1_CH1N, USART3_CTS, TIM15_CH1N, I2C2_SCL. |
| 26 | PB14 | bidirectional | 5 V-tolerant Fm+ capable GPIO; SPI2_MISO, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA. |
| 27 | PB15 | bidirectional | USB Type-C PD capable GPIO (FT_c, 5.0 V max input); SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, UCPD1_CC2, RTC_REFIN; a pull-down may be present on reset. |
| 28 | PA8 | bidirectional | USB Type-C PD capable GPIO (FT_c); MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT, UCPD1_CC1; a pull-down may be present on reset. |
| 29 | PA9 | bidirectional | 5 V-tolerant Fm+ capable GPIO with USB Type-C dead battery function; MCO, USART1_TX, TIM1_CH2, SPI2_MISO, I2C1_SCL, UCPD1_DBCC1. |
| 30 | PC6 | bidirectional | 5 V-tolerant GPIO; UCPD1_FRSTX, TIM3_CH1, TIM2_CH3. |
| 31 | PC7 | bidirectional | 5 V-tolerant GPIO; UCPD2_FRSTX, TIM3_CH2, TIM2_CH4. |
| 32 | PA10 | bidirectional | 5 V-tolerant Fm+ capable GPIO with USB Type-C dead battery function; SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA, UCPD1_DBCC2. |
| 33 | PA11 [PA9] | bidirectional | 5 V-tolerant Fm+ capable GPIO; SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL, COMP1_OUT; can be remapped to PA9 via SYSCFG_CFGR1. |
| 34 | PA12 [PA10] | bidirectional | 5 V-tolerant Fm+ capable GPIO; SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA, COMP2_OUT; can be remapped to PA10 via SYSCFG_CFGR1. |
| 35 | PA13 | bidirectional | 5 V-tolerant GPIO; SWDIO at reset with internal pull-up active, also IR_OUT, EVENTOUT. |
| 36 | PA14-BOOT0 | bidirectional | 5 V-tolerant GPIO; SWCLK at reset with internal pull-down active, also BOOT0, USART2_TX, EVENTOUT. |
| 37 | PA15 | bidirectional | 5 V-tolerant GPIO; SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, USART4_RTS_DE_CK, USART3_RTS_DE_CK, EVENTOUT. |
| 38 | PD0 | bidirectional | USB Type-C PD capable GPIO (FT_c); EVENTOUT, SPI2_NSS, TIM16_CH1, UCPD2_CC1; a pull-down may be present on reset. |
| 39 | PD1 | bidirectional | USB Type-C PD dead battery capable GPIO (FT_d); EVENTOUT, SPI2_SCK, TIM17_CH1, UCPD2_DBCC1. |
| 40 | PD2 | bidirectional | USB Type-C PD capable GPIO (FT_c); USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, UCPD2_CC2; a pull-down may be present on reset. |
| 41 | PD3 | bidirectional | USB Type-C PD dead battery capable GPIO (FT_d); USART2_CTS, SPI2_MISO, TIM1_CH2N, UCPD2_DBCC2. |
| 42 | PB3 | bidirectional | 5 V-tolerant GPIO with analog function; SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK, COMP2_INM. |
| 43 | PB4 | bidirectional | 5 V-tolerant GPIO with analog function; SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN, COMP2_INP. |
| 44 | PB5 | bidirectional | 5 V-tolerant GPIO; SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, WKUP6. |
| 45 | PB6 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog function; USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, COMP2_INP. |
| 46 | PB7 | bidirectional | 5 V-tolerant Fm+ capable GPIO with analog function; USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, COMP2_INM, PVD_IN. |
| 47 | PB8 | bidirectional | 5 V-tolerant Fm+ capable GPIO; CEC, SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN, I2C1_SCL. |
| 48 | PB9 | bidirectional | 5 V-tolerant Fm+ capable GPIO; IR_OUT, UCPD2_FRSTX, TIM17_CH1, USART3_RX, SPI2_NSS, I2C1_SDA. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32G071C8U3 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32g071c8u3-etched.step/stm32g071c8u3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32g071c8u3.step/stm32g071c8u3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (135 pp, sha256
5f6d9bac3422cd51, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).