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STM32G061F6P6

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STMICROELECTRONICS Global Sourcing Parts, TSSOP-20. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentglobal sourcing partsstm32g061f6p6factory-2.0.0extractor-text

Changed since verified STM32G061F6P6

by Ray · last 2 Nov 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 20 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: STM32G061F6P6 · TSSOP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 131-page datasheet
  • ✓distributor: lcsc C5270148, digikey 497-STM32G061F6P6-ND, mouser 511-STM32G061F6P6
  • ✓family: TSSOP-20_4.4x6.5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1s2ty0vl/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! stm32g061f6p6.kicad_sym✓ stm32g061f6p6.kicad_mod✓ stm32g061f6p6.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers stm32g061f6p6: symbol viewer · Ray 1d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
stm32g061f6p6-etched.glb Publish 0.1.0 · Ray 4d ago
stm32g061f6p6-etched.step stm32g061f6p6: factory component page (tier=mfr) · Ray 4d ago
stm32g061f6p6-hero.glb stm32g061f6p6: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
stm32g061f6p6-hero.overlay.json Publish 0.1.0 · Ray 4d ago
stm32g061f6p6.glb Publish 0.1.0 · Ray 4d ago
stm32g061f6p6.kicad_mod Publish 0.1.0 · Ray 4d ago
stm32g061f6p6.kicad_sym stm32g061f6p6: symbol repaired (body fitted to the names) · Ray 1d ago
stm32g061f6p6.lbr stm32g061f6p6: symbol repaired (body fitted to the names) · Ray 1d ago
stm32g061f6p6.step Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 20 pins · Ray 4d ago

STM32G061F6P6

STMICROELECTRONICS · Global Sourcing Parts · TSSOP-20

STM32G061F6P6 from STMICROELECTRONICS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB7/PB8 bidirectional PB7 is a 5 V-tolerant FT I/O with Fm+ capability (USART1_RX, I2C1_SDA, COMP2_INM7, PVD_IN) and PB8 is an FT I/O with Fm+ capability, as listed in Table 12 for this pin.
2 PC14-OSC32_IN bidirectional PC14 is a 5 V-tolerant FT I/O supplied through the power switch, which sinks only 3 mA, so its output use is limited to 2 MHz at 30 pF and it must not source current; it doubles as OSC32_IN.
3 PC15-OSC32_OUT bidirectional PC15 is a 5 V-tolerant FT I/O supplied through the power switch, which sinks only 3 mA, so its output use is limited to 2 MHz at 30 pF and it must not source current; it doubles as OSC32_OUT.
4 VDD/VDDA power_in Main supply pin for the device and the analog domain; the operating supply range is 1.7 V to 3.6 V.
5 VSS/VSSA power_in Ground reference pin for digital and analog circuits, to which all voltages are referenced.
6 PF2-NRST bidirectional Active-low reset pin with an embedded weak pull-up, which acts as an RST I/O when configured as reset and as an FT I/O when configured as GPIO.
7 PA0 bidirectional FT_a I/O with analog switch function that carries SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, LPTIM1_OUT and COMP1_OUT alternate functions, plus ADC_IN0, WKUP1 and TAMP_IN2.
8 PA1 bidirectional FT_ea I/O with analog switch and switchable diode to VDDIO1 that carries SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2 and ADC_IN1 functions.
9 PA2 bidirectional FT_a I/O with analog switch function that carries SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, LPUART1_TX and COMP2_OUT alternate functions, plus ADC_IN2 and WKUP4.
10 PA3 bidirectional FT_ea I/O with analog switch and switchable diode to VDDIO1 that carries SPI2_MISO, USART2_RX, TIM2_CH4, LPUART1_RX and ADC_IN3 functions.
11 PA4 bidirectional TT_a I/O (3.6 V tolerant) with analog switch function that carries SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1 and LPTIM2_OUT alternate functions, plus ADC_IN4, DAC1_OUT1 and RTC_OUT1 additional functions.
12 PA5 bidirectional TT_ea I/O (3.6 V tolerant) with analog switch and switchable diode to VDDIO1 that carries SPI1_SCK/I2S1_CK, TIM2_CH1_ETR and LPTIM2_ETR alternate functions, plus ADC_IN5 and DAC1_OUT2.
13 PA6 bidirectional FT_ea I/O with analog switch and switchable diode to VDDIO1 that carries SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, LPUART1_CTS and COMP1_OUT alternate functions, plus ADC_IN6.
14 PA7 bidirectional FT_a I/O with analog switch function that carries SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1 and COMP2_OUT alternate functions, plus ADC_IN7.
15 PB0/PB1/PB2/PA8 bidirectional Pin shared by PB0, PB1, PB2 and PA8 (Figure 3 grouping); PB0 is an FT_ea I/O with SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, LPTIM1_OUT, COMP1_OUT and ADC_IN8 functions, and PA8 is an FT I/O with MCO, SPI2_NSS, TIM1_CH1 and LPTIM2_OUT functions.
16 PA11 [PA9] bidirectional FT_fa I/O with Fm+ capability and analog switch function that carries SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL and COMP1_OUT alternate functions, plus ADC_IN15; PA9 remapping is selected through SYSCFG_CFGR1.
17 PA12 [PA10] bidirectional FT_fa I/O with Fm+ capability and analog switch function that carries SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA and COMP2_OUT alternate functions, plus ADC_IN16; PA10 remapping is selected through SYSCFG_CFGR1.
18 PA13 bidirectional FT_ea I/O with switchable diode to VDDIO1 that is configured as the SWDIO alternate function upon reset, with an internal pull-up enabled, and also carries IR_OUT, EVENTOUT and ADC_IN17.
19 PA15/PA14-BOOT0 bidirectional Pin shared by PA15 and PA14-BOOT0 (Figure 3 grouping); PA14 is an FT_a I/O that is SWCLK upon reset with an internal pull-down enabled and also acts as BOOT0, and PA15 is an FT I/O with SPI1_NSS/I2S1_WS, USART2_RX and TIM2_CH1_ETR alternate functions.
20 PB3/PB4/PB5/PB6 bidirectional Pin shared by PB3, PB4, PB5 and PB6 (Figure 3 grouping); PB3 is an FT_a I/O with SPI1_SCK/I2S1_CK and TIM1_CH2, PB4 is an FT_a I/O with SPI1_MISO/I2S1_MCK and TIM3_CH1, PB5 is an FT I/O with SPI1_MOSI/I2S1_SD and WKUP6, and PB6 is an FT_fa I/O with Fm+ capability, USART1_TX and I2C1_SCL.

Key specifications

Parameter Value
Manufacturer STMICROELECTRONICS
Package TSSOP-20
Category Global Sourcing Parts
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal AHB clock frequency fHCLK 0 64 MHz 48
Internal APB clock frequency fPCLK 0 64 MHz 48
Standard operating voltage VDD 1.7 3.6 V 48
Analog supply voltage VDDA 1.62 3.6 V For ADC and COMP operation 48
Analog supply voltage VDDA 1.8 3.6 V For DAC operation 48
Analog supply voltage VDDA 2.4 3.6 V For VREFBUF operation 48
Backup operating voltage VBAT 1.55 3.6 V 48
Ambient temperature suffix 6 TA -40 85 °C Suffix 6 48
Junction temperature suffix 6 TJ -40 105 °C Suffix 6 48
Voltage on TT_xx pins TT_xx -0.3 V Max is VDDA + 0.3 48
External supply voltage VDD -0.3 4 V 47
External supply voltage on VBAT pin VBAT -0.3 4 V 47
External voltage on VREF+ pin VREF+ -0.3 V Max is Min(VDD + 0.4, 4.0) 47
Input voltage on FT_xx VIN -0.3 V Max is VDD + 4.0 47
Input voltage on any other pin VIN -0.3 4 V 47
Current into VDD/VDDA power pin (source) IVDD/VDDA 100 mA 47
Current out of VSS/VSSA ground pin (sink) IVSS/VSSA 100 mA 47
Output current sunk by any I/O and control pin except FT_f IIO(PIN) 15 mA 47
Output current sunk by any FT_f pin IIO(PIN) 20 mA 47
Output current sourced by any I/O and control pin IIO(PIN) 15 mA 47
Total output current sunk by sum of all I/Os and control pins ΣIIO(PIN) 80 mA 48
Total output current sourced by sum of all I/Os and control pins ΣIIO(PIN) 80 mA 48
Injected current on a FT_xx pin IINJ(PIN) -5 mA Negative injection; NA for positive 48
Total injected current (sum of all I/Os and control pins) Σ/IINJ(PIN)/ 25 mA 48
Storage temperature range TSTG -65 150 °C 48
Maximum junction temperature TJ 150 °C 48
POR temporization when VDD crosses VPOR tRSTTEMPO 250 400 μs VDD rising 49
Power-on reset threshold VPOR 1.62 1.66 1.7 V 49
Power-down reset threshold VPDR 1.6 1.64 1.69 V 49
Brownout reset threshold 1 VBOR1 2.05 2.1 2.18 V VDD rising 49
Brownout reset threshold 1 VBOR1 1.95 2 2.08 V VDD falling 49
Internal reference voltage VREFINT 1.182 1.212 1.232 V -40°C < TJ < 130°C 50
Temperature coefficient TCoeff_vrefint 30 50 ppm/°C 50
Voltage coefficient VDDCoeff 250 1200 ppm/V 3.0 V < VDD < 3.6 V 50
Long term stability ACoeff 300 1000 ppm 1000 hours, T = 25 °C 50
Supply current in Run mode IDD(Run) 5.3 6.7 mA Range 1; PLL enabled; fHCLK = 64 MHz; flash memory; 25 °C (typ VDD 3.0 V, max VDD 3.6 V) 52
Supply current in Low-power run mode IDD(LPRun) 170 500 μA PLL disabled; fHCLK = 2 MHz; flash memory; 25 °C 53
Supply current in Sleep mode IDD(Sleep) 1.4 1.6 mA Range 1; fHCLK = 64 MHz; flash enabled; all peripherals disabled; 25 °C 55
Supply current in Stop 0 mode IDD(Stop 0) 270 300 μA HSI kernel enabled; VDD 3 V; 25 °C 55
Supply current in Stop 1 mode IDD(Stop 1) 4.8 16 μA Flash not powered; RTC disabled; VDD 3 V; 25 °C 56
Supply current in Standby mode IDD(Standby) 0.3 0.5 μA RTC disabled; VDD 3.0 V; 25 °C 56
Supply current in Shutdown mode IDD(Shutdown) 36 1400 nA RTC disabled; VDD 3.0 V; 25 °C 57
Supply current in VBAT mode IDD(VBAT) 5 nA RTC disabled; VDD 3.0 V; 25 °C 57
Wakeup time from Sleep to Run mode tWUSLEEP 11 11 CPU cycles 60
Wakeup time from Stop 0 tWUSTOP0 5.6 6 μs Transiting to Run mode, flash not powered in Stop 0; HCLK = HSI16 = 16 MHz; Regulator Range 1 or Range 2 60
Wakeup time from Standby mode tWUSTBY 14.5 30 μs Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator Range 1 61
Wakeup time from Shutdown mode tWUSHDN 258 340 μs Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator Range 1 61
High-speed external user clock source frequency fHSE_ext 8 48 MHz Voltage scaling Range 1 62
High-speed external user clock source frequency fHSE_ext 8 26 MHz Voltage scaling Range 2 62
OSC_IN high or low time tw(HSEH) tw(HSEL) 7 ns Voltage scaling Range 1 62
OSC_IN high or low time tw(HSEH) tw(HSEL) 18 ns Voltage scaling Range 2 62
Oscillator frequency fOSC_IN 4 8 48 MHz 63
HSI16 Frequency fHSI16 15.88 16.08 MHz VDD=3.0 V, TA=30 °C 66
HSI16 oscillator frequency drift over temperature ΔTemp(HSI16) -1 1 % TA = 0 to 85 °C 66
HSI16 oscillator frequency drift over temperature ΔTemp(HSI16) -2 1.5 % TA = -40 to 125 °C 66
HSI16 oscillator frequency drift over VDD ΔVDD(HSI16) -0.1 0.05 % VDD = 1.62 V to 3.6 V 66
Duty Cycle DHSI16 45 55 % 66
HSI16 oscillator start-up time tsu(HSI16) 0.8 1.2 μs 66
HSI16 oscillator stabilization time tstab(HSI16) 3 5 μs 66
HSI16 oscillator power consumption IDD(HSI16) 155 190 μA 66
LSI frequency fLSI 31.04 32.96 kHz VDD = 3.0 V, TA = 30 °C 67
LSI frequency fLSI 29.5 34 kHz VDD = 1.62 V to 3.6 V, TA = -40 to 125 °C 67
LSI oscillator start-up time tSU(LSI) 80 130 μs 67
LSI oscillator stabilization time tSTAB(LSI) 125 180 μs 5% of final frequency 67
LSI oscillator power consumption IDD(LSI) 110 180 nA 67
PLL input clock frequency fPLL_IN 2.66 16 MHz 68
PLL input clock duty cycle DPLL_IN 45 55 % 68
PLL VCO output fVCO_OUT 96 344 MHz Voltage scaling Range 1 68
PLL VCO output fVCO_OUT 96 128 MHz Voltage scaling Range 2 68
PLL lock time tLOCK 15 40 μs 68
PLL power consumption on VDD IDD(PLL) 200 260 μA VCO freq = 96 MHz 68
64-bit programming time tprog 85 125 μs 68
Page (2 Kbyte) erase time tERASE 22 40 ms 68
Mass erase time tME 22.1 40.1 ms 68
Endurance NEND 10 kcycles TA = -40 to +105 °C 69
I/O input low level voltage VIL 0.3 x VDDIO1 All; 1.62 V < VDDIO1 < 3.6 V 73
I/O input high level voltage VIH 0.7 x VDDIO1 All; 1.62 V < VDDIO1 < 3.6 V 73
Input leakage current Ilkg -70 70 nA 0 < VIN ≤ VDDIO1 73
Input leakage current Ilkg 600 nA VDDIO1 ≤ VIN ≤ VDDIO1+1 V 73
Weak pull-up equivalent resistor RPU 25 40 55 kΩ VIN = VSS 73
Weak pull-down equivalent resistor RPD 25 40 55 kΩ VIN = VDDIO1 73
Injected current on pin IINJ 5 mA FT_e I/Os 74
Voltage over VDDIO1 VDDIO1-VIN 2 V IINJ = 5 mA 74
Diode dynamic serial resistor Rd 300 Ω IINJ = 5 mA 74

CAD (KiCad official)

  • Symbol: STM32G061F6P6
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: stm32g061f6p6-etched.step / stm32g061f6p6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g061f6p6.step / stm32g061f6p6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMICROELECTRONICS datasheet (131 pp, sha256 5f69c1c8f85f6ca3, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF