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STM32G061C8T6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32G061C8T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

STM32G061C8T6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC13 bidirectional 5 V-tolerant (FT) GPIO supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz with a 30 pF load and the pin must not be used as a current source such as for an LED; alternates TIM1_BKIN, additional TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2.
2 PC14-OSC32_IN bidirectional 5 V-tolerant GPIO on the power-switch domain with the same 3 mA sink and 2 MHz / 30 pF output limits, also serving as the 32.768 kHz LSE oscillator input OSC32_IN.
3 PC15-OSC32_OUT bidirectional 5 V-tolerant GPIO on the power-switch domain with the same 3 mA sink and 2 MHz / 30 pF output limits, also serving as the LSE oscillator output OSC32_OUT.
4 VBAT power_in Backup-domain supply for the RTC, TAMP, the 32.768 kHz oscillator and backup registers, specified at 1.55 V to 3.6 V and used when VDD is not present.
5 VREF+ power_in Analog reference input for the ADC, DAC and comparators, which must equal VDDA when VDDA < 2 V and lie between 2 V and VDDA when VDDA ≥ 2 V, or serve as the VREFBUF output when the internal buffer is enabled.
6 VDD/VDDA power_in Main 1.7 V to 3.6 V supply for the internal regulator, I/O logic and analog blocks, with VDDA specified down to 1.62 V for the ADC and comparators, 1.8 V for the DAC and 2.4 V for the VREFBUF.
7 VSS/VSSA power_in Ground reference for digital and analog circuits; all device voltages are referenced to VSS.
8 PF0-OSC_IN bidirectional 5 V-tolerant GPIO with alternate TIM14_CH1 and additional function HSE crystal oscillator input OSC_IN.
9 PF1-OSC_OUT bidirectional 5 V-tolerant GPIO with alternates OSC_EN and TIM15_CH1N and additional function HSE crystal oscillator output OSC_OUT.
10 PF2-NRST bidirectional Bidirectional reset pin with an embedded weak pull-up whose default function is NRST, with MCO as alternate function; if used as a GPIO, other I/Os connected to this pin must be configured with care.
11 PA0 bidirectional 5 V-tolerant I/O with analog switch function, alternates SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, LPTIM1_OUT and COMP1_OUT, and additional functions ADC_IN0, COMP1_INM8, TAMP_IN2 and WKUP1.
12 PA1 bidirectional 5 V-tolerant I/O with switchable diode to VDD and analog switch function, alternates SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, TIM15_CH1N, I2C1_SMBA and EVENTOUT, and additional functions ADC_IN1 and COMP1_INP2.
13 PA2 bidirectional 5 V-tolerant I/O with analog switch function, alternates SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, TIM15_CH1, LPUART1_TX and COMP2_OUT, and additional functions ADC_IN2, COMP2_INM8, WKUP4 and LSCO.
14 PA3 bidirectional 5 V-tolerant I/O with switchable diode to VDD and analog switch function, alternates SPI2_MISO, USART2_RX, TIM2_CH4, TIM15_CH2, LPUART1_RX and EVENTOUT, and additional functions ADC_IN3 and COMP2_INP2.
15 PA4 bidirectional 5 V-tolerant I/O with analog switch function, alternates SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT and EVENTOUT, and additional functions ADC_IN4, DAC1_OUT1 and RTC_OUT2.
16 PA5 bidirectional 5 V-tolerant I/O with switchable diode to VDD and analog switch function, alternates SPI1_SCK/I2S1_CK, TIM2_CH1_ETR, LPTIM2_ETR and EVENTOUT, and additional functions ADC_IN5 and DAC1_OUT2.
17 PA6 bidirectional 5 V-tolerant I/O with switchable diode to VDD and analog switch function, alternates SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, TIM16_CH1, LPUART1_CTS and COMP1_OUT, and additional function ADC_IN6.
18 PA7 bidirectional 5 V-tolerant I/O with analog switch function, alternates SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1 and COMP2_OUT, and additional function ADC_IN7.
19 PB0 bidirectional 5 V-tolerant I/O with switchable diode to VDD and analog switch function, alternates SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, LPTIM1_OUT and COMP1_OUT, and additional function ADC_IN8.
20 PB1 bidirectional 5 V-tolerant I/O with switchable diode to VDD and analog switch function, alternates TIM14_CH1, TIM3_CH4, TIM1_CH3N, LPTIM2_IN1, LPUART1_RTS_DE and EVENTOUT, and additional functions ADC_IN9 and COMP1_INM6.
21 PB2 bidirectional 5 V-tolerant I/O with switchable diode to VDD and analog switch function, alternates SPI2_MISO, LPTIM1_OUT and EVENTOUT, and additional functions ADC_IN10 and COMP1_INP1.
22 PB10 bidirectional 5 V-tolerant I/O, Fm+ capable, with analog switch function, alternates LPUART1_RX, TIM2_CH3, SPI2_SCK, I2C2_SCL and COMP1_OUT, and additional function ADC_IN11.
23 PB11 bidirectional 5 V-tolerant I/O, Fm+ capable, with analog switch function, alternates SPI2_MOSI, LPUART1_TX, TIM2_CH4, I2C2_SDA and COMP2_OUT, and additional function ADC_IN15.
24 PB12 bidirectional 5 V-tolerant I/O with analog switch function, alternates SPI2_NSS, LPUART1_RTS_DE, TIM1_BKIN, TIM15_BKIN and EVENTOUT, and additional function ADC_IN16.
25 PB13 bidirectional 5 V-tolerant I/O, Fm+ capable, alternates SPI2_SCK, LPUART1_CTS, TIM1_CH1N, TIM15_CH1N, I2C2_SCL and EVENTOUT.
26 PB14 bidirectional 5 V-tolerant I/O, Fm+ capable, alternates SPI2_MISO, TIM1_CH2N, TIM15_CH1, I2C2_SDA and EVENTOUT.
27 PB15 bidirectional 5 V-tolerant I/O, alternates SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2 and EVENTOUT, and additional function RTC_REFIN.
28 PA8 bidirectional 5 V-tolerant I/O with alternates MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT and EVENTOUT.
29 PA9 bidirectional 5 V-tolerant I/O, Fm+ capable, with alternates MCO, USART1_TX, TIM1_CH2, SPI2_MISO, TIM15_BKIN, I2C1_SCL and EVENTOUT; it can be remapped in place of PA11 using SYSCFG_CFGR1.
30 PC6 bidirectional 5 V-tolerant I/O with alternates TIM3_CH1 and TIM2_CH3.
31 PC7 bidirectional 5 V-tolerant I/O with alternates TIM3_CH2 and TIM2_CH4.
32 PA10 bidirectional 5 V-tolerant I/O, Fm+ capable, with alternates SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA and EVENTOUT; it can be remapped in place of PA12 using SYSCFG_CFGR1.
33 PA11 [PA9] bidirectional 5 V-tolerant I/O, Fm+ capable, with analog switch function, default mapping of PA11 with alternates SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL and COMP1_OUT, and additional function ADC_IN15.
34 PA12 [PA10] bidirectional 5 V-tolerant I/O, Fm+ capable, with analog switch function, default mapping of PA12 with alternates SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA and COMP2_OUT, and additional function ADC_IN16.
35 PA13 bidirectional 5 V-tolerant I/O that is configured as the SWDIO alternate function with an internal pull-up enabled upon reset, with alternates IR_OUT and EVENTOUT and additional function ADC_IN17.
36 PA14-BOOT0 bidirectional 5 V-tolerant I/O that is configured as the SWCLK alternate function with an internal pull-down enabled upon reset, with alternates USART2_TX and EVENTOUT and additional functions ADC_IN18 and BOOT0 boot-mode selection.
37 PA15 bidirectional 5 V-tolerant I/O with alternates SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR and EVENTOUT.
38 PD0 bidirectional 5 V-tolerant I/O with alternates EVENTOUT, SPI2_NSS and TIM16_CH1.
39 PD1 bidirectional 5 V-tolerant I/O with alternates EVENTOUT, SPI2_SCK and TIM17_CH1.
40 PD2 bidirectional 5 V-tolerant I/O with alternates TIM3_ETR and TIM1_CH1N.
41 PD3 bidirectional 5 V-tolerant I/O with alternates USART2_CTS, SPI2_MISO and TIM1_CH2N.
42 PB3 bidirectional 5 V-tolerant I/O with analog switch function, alternates SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK and EVENTOUT, and additional function COMP2_INM6.
43 PB4 bidirectional 5 V-tolerant I/O with analog switch function, alternates SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT, and additional function COMP2_INP0.
44 PB5 bidirectional 5 V-tolerant I/O with alternates SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1, I2C1_SMBA and COMP2_OUT, and additional function WKUP6.
45 PB6 bidirectional 5 V-tolerant I/O, Fm+ capable, with analog switch function, alternates USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL and EVENTOUT, and additional function COMP2_INP1.
46 PB7 bidirectional 5 V-tolerant I/O, Fm+ capable, with analog switch function, alternates USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA and EVENTOUT, and additional functions ADC_IN11, COMP2_INM7 and PVD_IN.
47 PB8 bidirectional 5 V-tolerant I/O, Fm+ capable, with alternates SPI2_SCK, TIM16_CH1, TIM15_BKIN, I2C1_SCL and EVENTOUT.
48 PB9 bidirectional 5 V-tolerant I/O, Fm+ capable, with alternates IR_OUT, TIM17_CH1, SPI2_NSS, I2C1_SDA and EVENTOUT.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: STM32G061C8T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32g061c8t6-etched.step / stm32g061c8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g061c8t6.step / stm32g061c8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (126 pp, sha256 9d37a967fe2d67ec, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF