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stm32g041j6m6-hero.glb	stm32g041j6m6: hero GLB from the etched model (keeps the MPN mark) · Ray	16d ago
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STM32G041J6M6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · SOP-8

STM32G041J6M6 from STMicroelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PB7/PB8/PB9/PC14-OSC32_IN	bidirectional	Pin is a 5 V-tolerant FT I/O whose reset-default function is PC14 (OSC32_IN); PC13-PC15 are supplied through the power switch, which sinks only 3 mA, so their output use is limited to 2 MHz at 30 pF and they must not be used as current sources.
2	VDD/VDDA	power_in	Standard operating supply VDD is 1.7 V to 3.6 V (1.7 V being the POR release threshold), and VDDA is 1.62 V minimum for ADC operation and 2.4 V minimum for VREFBUF operation.
3	VSS/VSSA	power_in	Ground reference pin; all voltages on the device are referenced to VSS.
4	PA0/PA1/PA2/PF2-NRST	bidirectional	Bidirectional reset pin (NRST) with embedded weak pull-up, sharing the package pin with 5 V-tolerant FT I/Os PA0, PA1 and PA2 (ADC_IN0, ADC_IN1, ADC_IN2).
5	PA8/PA11[PA9]/PB0/PB1	bidirectional	Pin provides 5 V-tolerant FT I/Os PA8, PB0 and PB1 (PB0/PB1 with ADC_IN8/ADC_IN9) and PA11, where PA9 can be remapped in place of PA11 through the SYSCFG_CFGR1 register (default mapping is PA11).
6	PA12[PA10]	bidirectional	Fm+-capable 5 V-tolerant I/O (FT_fa) with ADC_IN16, where PA10 can be remapped in place of PA12 through the SYSCFG_CFGR1 register (default mapping is PA12).
7	PA13	bidirectional	Upon reset this pin is the SWDIO alternate function with the internal pull-up activated; it is a 5 V-tolerant FT_ea I/O (switchable diode to VDD) that also provides ADC_IN17.
8	PB5/PB6/PA14-BOOT0/PA15	bidirectional	Upon reset this pin is the SWCLK alternate function with the internal pull-down activated, and PA14 is shared with the BOOT0 boot-mode pin, which is enabled through the boot selector option bit.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SOP-8
Category	Embedded Processors & Controllers
Pins	8

CAD (KiCad official)

Symbol: STM32G041J6M6
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: stm32g041j6m6-etched.step / stm32g041j6m6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g041j6m6.step / stm32g041j6m6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (118 pp, sha256 586607fd294bd34f, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF