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STM32G031K8U6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-32(5x5). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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docs stm32g031k8u6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
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README.md Initial commit: component/stm32g031k8u6 · Ray 4d ago
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stm32g031k8u6-etched.step stm32g031k8u6: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
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STM32G031K8U6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-32(5x5)

STM32G031K8U6 from STMicroelectronics, in a UFQFPN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB9 bidirectional 5V-tolerant, Fm+ capable I/O, default analog input at reset; alternate functions IR_OUT, TIM17_CH1, SPI2_NSS, I2C1_SDA, EVENTOUT.
2 PC14-OSC32_IN bidirectional 5V-tolerant I/O shared with the 32.768 kHz LSE oscillator input and, on this package, also carries the OSC_IN (HSE) function; alternate function TIM1_BK2.
3 PC15-OSC32_OUT bidirectional 5V-tolerant I/O shared with the 32.768 kHz LSE oscillator output; alternate/enable functions OSC32_EN, OSC_EN.
4 VDD/VDDA power_in Digital and analog power supply input, 1.7 V (1.6 V min) to 3.6 V, also feeds VDDIO1 (I/O) and VDDA (ADC/VREFBUF) domains.
5 VSS/VSSA power_in Digital and analog ground reference pin.
6 PF2-NRST bidirectional Bidirectional reset I/O with embedded ~40 kΩ weak pull-up resistor, active low; also usable for the MCO alternate function.
7 PA0 bidirectional 5V-tolerant I/O with analog switch, default analog input at reset; alternate functions SPI2_SCK, USART2_CTS, TIM2_CH1_ETR, LPTIM1_OUT; additional functions ADC_IN0, TAMP_IN2, WKUP1.
8 PA1 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; alternate functions SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, I2C1_SMBA, EVENTOUT; additional function ADC_IN1.
9 PA2 bidirectional 5V-tolerant I/O with analog switch, default analog input at reset; alternate functions SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, LPUART1_TX; additional functions ADC_IN2, WKUP4, LSCO.
10 PA3 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; alternate functions SPI2_MISO, USART2_RX, TIM2_CH4, LPUART1_RX, EVENTOUT; additional function ADC_IN3.
11 PA4 bidirectional 5V-tolerant I/O with analog switch, default analog input at reset; alternate functions SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT, EVENTOUT; additional functions ADC_IN4, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2.
12 PA5 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; alternate functions SPI1_SCK/I2S1_CK, TIM2_CH1_ETR, LPTIM2_ETR, EVENTOUT; additional function ADC_IN5.
13 PA6 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BK, TIM16_CH1, LPUART1_CTS; additional function ADC_IN6.
14 PA7 bidirectional 5V-tolerant I/O with analog switch, default analog input at reset; alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1; additional function ADC_IN7.
15 PB0 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; alternate functions SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, LPTIM1_OUT; additional function ADC_IN8.
16 PB1 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; alternate functions TIM14_CH1, TIM3_CH4, TIM1_CH3N, LPTIM2_IN1, LPUART1_RTS_DE, EVENTOUT; additional function ADC_IN9.
17 PB2 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; alternate functions SPI2_MISO, LPTIM1_OUT, EVENTOUT; additional function ADC_IN10.
18 PA8 bidirectional 5V-tolerant I/O, default analog input at reset; alternate functions MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT, EVENTOUT.
19 PA9 bidirectional 5V-tolerant, Fm+ capable I/O, default analog input at reset; alternate functions MCO, USART1_TX, TIM1_CH2, SPI2_MISO, I2C1_SCL, EVENTOUT.
20 PC6 bidirectional 5V-tolerant I/O, default analog input at reset; alternate functions TIM3_CH1, TIM2_CH3.
21 PA10 bidirectional 5V-tolerant, Fm+ capable I/O, default analog input at reset; alternate functions SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BK, I2C1_SDA, EVENTOUT.
22 PA11 [PA9] bidirectional 5V-tolerant, Fm+ capable I/O with analog switch, remappable as PA9, default analog input at reset; alternate functions SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BK2, I2C2_SCL; additional function ADC_IN15.
23 PA12 [PA10] bidirectional 5V-tolerant, Fm+ capable I/O with analog switch, remappable as PA10, default analog input at reset; alternate functions SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA; additional function ADC_IN16.
24 PA13 bidirectional 5V-tolerant I/O with analog switch and switchable diode to VDD, default analog input at reset; primary alternate function SWDIO (serial-wire debug data), also IR_OUT, EVENTOUT; additional function ADC_IN17.
25 PA14-BOOT0 bidirectional 5V-tolerant I/O with analog switch, default analog input at reset and also samples BOOT0 boot-mode selection at reset when enabled by option byte; alternate functions SWCLK (serial-wire debug clock), USART2_TX, EVENTOUT; additional function ADC_IN18.
26 PA15 bidirectional 5V-tolerant I/O, default analog input at reset; alternate functions SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, EVENTOUT.
27 PB3 bidirectional 5V-tolerant I/O, default analog input at reset; alternate functions SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK, EVENTOUT.
28 PB4 bidirectional 5V-tolerant I/O, default analog input at reset; alternate functions SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BK, EVENTOUT.
29 PB5 bidirectional 5V-tolerant I/O, default analog input at reset; alternate functions SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BK, LPTIM1_IN1, I2C1_SMBA; additional function WKUP6.
30 PB6 bidirectional 5V-tolerant, Fm+ capable I/O, default analog input at reset; alternate functions USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL, EVENTOUT.
31 PB7 bidirectional 5V-tolerant, Fm+ capable I/O with analog switch, default analog input at reset; alternate functions USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA, EVENTOUT; additional functions ADC_IN11, PVD_IN.
32 PB8 bidirectional 5V-tolerant, Fm+ capable I/O, default analog input at reset; alternate functions SPI2_SCK, TIM16_CH1, I2C1_SCL, EVENTOUT.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: STM32G031K8U6
  • Footprint: Package_DFN_QFN:UFQFPN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm
  • 3D model: UFQFPN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: stm32g031k8u6-etched.step / stm32g031k8u6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32g031k8u6.step / stm32g031k8u6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (117 pp, sha256 95ae804dbf135590, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF