component
STM32G031C6U6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
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STM32G031C6U6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32G031C6U6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC13 | bidirectional | 5 V-tolerant I/O (FT) with alternate function TIM1_BK and additional functions TAMP_IN1, RTC_TS, RTC_OUT1 and WKUP2. |
| 2 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O (FT) that doubles as the 32.768 kHz low-speed oscillator input OSC32_IN, with alternate function TIM1_BK2. |
| 3 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O (FT) that doubles as the 32.768 kHz low-speed oscillator output OSC32_OUT, with alternate functions OSC32_EN and OSC_EN. |
| 4 | VBAT | power_in | Backup-domain supply input (1.55 V to 3.6 V) that powers the RTC, TAMP, LSE oscillator and backup registers when VDD is not present. |
| 5 | VREF+ | power_in | ADC reference input or output of the internal voltage reference buffer when enabled; when VDDA < 2 V it must equal VDDA, and when VDDA ≥ 2 V it must be between 2 V and VDDA. |
| 6 | VDD/VDDA | power_in | Main supply pin of 1.7 V to 3.6 V for the core, I/O ring and analog blocks (ADC requires VDDA ≥ 1.62 V and VREFBUF requires VDDA ≥ 2.4 V). |
| 7 | VSS/VSSA | power_in | Ground pin for the digital and analog supplies, which must always be connected to the external ground. |
| 8 | PF0-OSC_IN | bidirectional | 5 V-tolerant I/O (FT) that doubles as the high-speed oscillator input OSC_IN, with alternate function TIM14_CH1. |
| 9 | PF1-OSC_OUT | bidirectional | 5 V-tolerant I/O (FT) that doubles as the high-speed oscillator output OSC_OUT, with alternate function OSC_EN. |
| 10 | PF2-NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor (NRST), which also carries alternate function MCO on PF2. |
| 11 | PA0 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI2_SCK, USART2_CTS, TIM2_CH1_ETR and LPTIM1_OUT, plus ADC_IN0, TAMP_IN2 and WKUP1 as additional functions. |
| 12 | PA1 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, I2C1_SMBA and EVENTOUT, plus ADC_IN1. |
| 13 | PA2 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3 and LPUART1_TX, plus ADC_IN2, WKUP4 and LSCO. |
| 14 | PA3 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI2_MISO, USART2_RX, TIM2_CH4, LPUART1_RX and EVENTOUT, plus ADC_IN3. |
| 15 | PA4 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT and EVENTOUT, plus ADC_IN4 and RTC_OUT2. |
| 16 | PA5 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_SCK/I2S1_CK, TIM2_CH1_ETR, LPTIM2_ETR and EVENTOUT, plus ADC_IN5. |
| 17 | PA6 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BK, TIM16_CH1 and LPUART1_CTS, plus ADC_IN6. |
| 18 | PA7 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1 and TIM17_CH1, plus ADC_IN7. |
| 19 | PB0 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N and LPTIM1_OUT, plus ADC_IN8. |
| 20 | PB1 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering TIM14_CH1, TIM3_CH4, TIM1_CH3N, LPTIM2_IN1, LPUART1_RTS_DE and EVENTOUT, plus ADC_IN9. |
| 21 | PB2 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI2_MISO, LPTIM1_OUT and EVENTOUT, plus ADC_IN10. |
| 22 | PB10 | bidirectional | 5 V-tolerant I/O with Fm+ capability and analog switch function (FT_fa) offering LPUART1_RX, TIM2_CH3, SPI2_SCK and I2C2_SCL, plus ADC_IN11. |
| 23 | PB11 | bidirectional | 5 V-tolerant I/O with Fm+ capability and analog switch function (FT_fa) offering SPI2_MOSI, LPUART1_TX, TIM2_CH4 and I2C2_SDA, plus ADC_IN15. |
| 24 | PB12 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI2_NSS, LPUART1_RTS_DE, TIM1_BK and EVENTOUT, plus ADC_IN16. |
| 25 | PB13 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_SCK, LPUART1_CTS, TIM1_CH1N, I2C2_SCL and EVENTOUT. |
| 26 | PB14 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_MISO, TIM1_CH2N, I2C2_SDA and EVENTOUT. |
| 27 | PB15 | bidirectional | 5 V-tolerant I/O (FT) offering SPI2_MOSI, TIM1_CH3N and EVENTOUT, with RTC_REFIN as an additional function. |
| 28 | PA8 | bidirectional | 5 V-tolerant I/O (FT) offering MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT and EVENTOUT. |
| 29 | PA9 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering MCO, USART1_TX, TIM1_CH2, SPI2_MISO, I2C1_SCL and EVENTOUT. |
| 30 | PC6 | bidirectional | 5 V-tolerant I/O (FT) offering TIM3_CH1 and TIM2_CH3. |
| 31 | PC7 | bidirectional | 5 V-tolerant I/O (FT) offering TIM3_CH2 and TIM2_CH4. |
| 32 | PA10 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA and EVENTOUT. |
| 33 | PA11 [PA9] | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2 and I2C2_SCL; the bracketed PA9 is the remap alternative name. |
| 34 | PA12 [PA10] | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN and I2C2_SDA; the bracketed PA10 is the remap alternative name. |
| 35 | PA13 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SWDIO, IR_OUT and EVENTOUT, plus ADC_IN17. |
| 36 | PA14-BOOT0 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SWCLK, USART2_TX and EVENTOUT, which also serves as the BOOT0 boot-mode pin and ADC_IN18 input. |
| 37 | PA15 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR and EVENTOUT. |
| 38 | PD0 | bidirectional | 5 V-tolerant I/O (FT) offering EVENTOUT, SPI2_NSS and TIM16_CH1. |
| 39 | PD1 | bidirectional | 5 V-tolerant I/O (FT) offering EVENTOUT, SPI2_SCK and TIM17_CH1. |
| 40 | PD2 | bidirectional | 5 V-tolerant I/O (FT) offering TIM3_ETR and TIM1_CH1N. |
| 41 | PD3 | bidirectional | 5 V-tolerant I/O (FT) offering USART2_CTS, SPI2_MISO and TIM1_CH2N. |
| 42 | PB3 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK and EVENTOUT. |
| 43 | PB4 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT. |
| 44 | PB5 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1 and I2C1_SMBA, with WKUP6 as an additional function. |
| 45 | PB6 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL and EVENTOUT. |
| 46 | PB7 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA and EVENTOUT, with PVD_IN as an additional function. |
| 47 | PB8 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_SCK, TIM16_CH1, I2C1_SCL and EVENTOUT. |
| 48 | PB9 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering IR_OUT, TIM17_CH1, SPI2_NSS, I2C1_SDA and EVENTOUT. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32G031C6U6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32g031c6u6-etched.step/stm32g031c6u6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32g031c6u6.step/stm32g031c6u6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (117 pp, sha256
95ae804dbf135590, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM32G031C6U6
**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32G031C6U6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PC13 | bidirectional | 5 V-tolerant I/O (FT) with alternate function TIM1_BK and additional functions TAMP_IN1, RTC_TS, RTC_OUT1 and WKUP2. |
| 2 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O (FT) that doubles as the 32.768 kHz low-speed oscillator input OSC32_IN, with alternate function TIM1_BK2. |
| 3 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O (FT) that doubles as the 32.768 kHz low-speed oscillator output OSC32_OUT, with alternate functions OSC32_EN and OSC_EN. |
| 4 | VBAT | power_in | Backup-domain supply input (1.55 V to 3.6 V) that powers the RTC, TAMP, LSE oscillator and backup registers when VDD is not present. |
| 5 | VREF+ | power_in | ADC reference input or output of the internal voltage reference buffer when enabled; when VDDA < 2 V it must equal VDDA, and when VDDA ≥ 2 V it must be between 2 V and VDDA. |
| 6 | VDD/VDDA | power_in | Main supply pin of 1.7 V to 3.6 V for the core, I/O ring and analog blocks (ADC requires VDDA ≥ 1.62 V and VREFBUF requires VDDA ≥ 2.4 V). |
| 7 | VSS/VSSA | power_in | Ground pin for the digital and analog supplies, which must always be connected to the external ground. |
| 8 | PF0-OSC_IN | bidirectional | 5 V-tolerant I/O (FT) that doubles as the high-speed oscillator input OSC_IN, with alternate function TIM14_CH1. |
| 9 | PF1-OSC_OUT | bidirectional | 5 V-tolerant I/O (FT) that doubles as the high-speed oscillator output OSC_OUT, with alternate function OSC_EN. |
| 10 | PF2-NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor (NRST), which also carries alternate function MCO on PF2. |
| 11 | PA0 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI2_SCK, USART2_CTS, TIM2_CH1_ETR and LPTIM1_OUT, plus ADC_IN0, TAMP_IN2 and WKUP1 as additional functions. |
| 12 | PA1 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, I2C1_SMBA and EVENTOUT, plus ADC_IN1. |
| 13 | PA2 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3 and LPUART1_TX, plus ADC_IN2, WKUP4 and LSCO. |
| 14 | PA3 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI2_MISO, USART2_RX, TIM2_CH4, LPUART1_RX and EVENTOUT, plus ADC_IN3. |
| 15 | PA4 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, LPTIM2_OUT and EVENTOUT, plus ADC_IN4 and RTC_OUT2. |
| 16 | PA5 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_SCK/I2S1_CK, TIM2_CH1_ETR, LPTIM2_ETR and EVENTOUT, plus ADC_IN5. |
| 17 | PA6 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BK, TIM16_CH1 and LPUART1_CTS, plus ADC_IN6. |
| 18 | PA7 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1 and TIM17_CH1, plus ADC_IN7. |
| 19 | PB0 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N and LPTIM1_OUT, plus ADC_IN8. |
| 20 | PB1 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering TIM14_CH1, TIM3_CH4, TIM1_CH3N, LPTIM2_IN1, LPUART1_RTS_DE and EVENTOUT, plus ADC_IN9. |
| 21 | PB2 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SPI2_MISO, LPTIM1_OUT and EVENTOUT, plus ADC_IN10. |
| 22 | PB10 | bidirectional | 5 V-tolerant I/O with Fm+ capability and analog switch function (FT_fa) offering LPUART1_RX, TIM2_CH3, SPI2_SCK and I2C2_SCL, plus ADC_IN11. |
| 23 | PB11 | bidirectional | 5 V-tolerant I/O with Fm+ capability and analog switch function (FT_fa) offering SPI2_MOSI, LPUART1_TX, TIM2_CH4 and I2C2_SDA, plus ADC_IN15. |
| 24 | PB12 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SPI2_NSS, LPUART1_RTS_DE, TIM1_BK and EVENTOUT, plus ADC_IN16. |
| 25 | PB13 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_SCK, LPUART1_CTS, TIM1_CH1N, I2C2_SCL and EVENTOUT. |
| 26 | PB14 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_MISO, TIM1_CH2N, I2C2_SDA and EVENTOUT. |
| 27 | PB15 | bidirectional | 5 V-tolerant I/O (FT) offering SPI2_MOSI, TIM1_CH3N and EVENTOUT, with RTC_REFIN as an additional function. |
| 28 | PA8 | bidirectional | 5 V-tolerant I/O (FT) offering MCO, SPI2_NSS, TIM1_CH1, LPTIM2_OUT and EVENTOUT. |
| 29 | PA9 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering MCO, USART1_TX, TIM1_CH2, SPI2_MISO, I2C1_SCL and EVENTOUT. |
| 30 | PC6 | bidirectional | 5 V-tolerant I/O (FT) offering TIM3_CH1 and TIM2_CH3. |
| 31 | PC7 | bidirectional | 5 V-tolerant I/O (FT) offering TIM3_CH2 and TIM2_CH4. |
| 32 | PA10 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA and EVENTOUT. |
| 33 | PA11 [PA9] | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2 and I2C2_SCL; the bracketed PA9 is the remap alternative name. |
| 34 | PA12 [PA10] | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN and I2C2_SDA; the bracketed PA10 is the remap alternative name. |
| 35 | PA13 | bidirectional | 5 V-tolerant I/O with analog switch and switchable VDD diode (FT_ea) offering SWDIO, IR_OUT and EVENTOUT, plus ADC_IN17. |
| 36 | PA14-BOOT0 | bidirectional | 5 V-tolerant I/O with analog switch function (FT_a) offering SWCLK, USART2_TX and EVENTOUT, which also serves as the BOOT0 boot-mode pin and ADC_IN18 input. |
| 37 | PA15 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR and EVENTOUT. |
| 38 | PD0 | bidirectional | 5 V-tolerant I/O (FT) offering EVENTOUT, SPI2_NSS and TIM16_CH1. |
| 39 | PD1 | bidirectional | 5 V-tolerant I/O (FT) offering EVENTOUT, SPI2_SCK and TIM17_CH1. |
| 40 | PD2 | bidirectional | 5 V-tolerant I/O (FT) offering TIM3_ETR and TIM1_CH1N. |
| 41 | PD3 | bidirectional | 5 V-tolerant I/O (FT) offering USART2_CTS, SPI2_MISO and TIM1_CH2N. |
| 42 | PB3 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART1_RTS_DE_CK and EVENTOUT. |
| 43 | PB4 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN and EVENTOUT. |
| 44 | PB5 | bidirectional | 5 V-tolerant I/O (FT) offering SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, LPTIM1_IN1 and I2C1_SMBA, with WKUP6 as an additional function. |
| 45 | PB6 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, LPTIM1_ETR, I2C1_SCL and EVENTOUT. |
| 46 | PB7 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering USART1_RX, SPI2_MOSI, TIM17_CH1N, LPTIM1_IN2, I2C1_SDA and EVENTOUT, with PVD_IN as an additional function. |
| 47 | PB8 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering SPI2_SCK, TIM16_CH1, I2C1_SCL and EVENTOUT. |
| 48 | PB9 | bidirectional | 5 V-tolerant I/O with Fm+ capability (FT_f) offering IR_OUT, TIM17_CH1, SPI2_NSS, I2C1_SDA and EVENTOUT. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `STM32G031C6U6`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm32g031c6u6-etched.step` / `stm32g031c6u6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32g031c6u6.step` / `stm32g031c6u6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886244483084288) (117 pp, sha256 `95ae804dbf135590`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm32g031c6u6-datasheet.pdf)