Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

STM32F765VGT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F765VGT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	output	Trace clock, SPI4 serial clock, SAI1 master clock alternative A, QUADSPI bank 1 IO2, Ethernet MII transmit data 3, FMC address line 23
2	PE3	output	Trace data 0, SAI1 serial data alternative B, FMC address line 19
3	PE4	output	Trace data 1, TIM9 channel 1, SPI4 chip select, SAI1 frame sync alternative A, DFSDM1 data in 3, FMC address line 20, DCMI data 4, LCD blue 0
4	PE5	output	Trace data 2, TIM9 channel 1, SPI4 MISO, SAI1 serial clock alternative A, DFSDM1 clock in 3, FMC address line 21, DCMI data 6, LCD green 0
5	PE6	output	Trace data 3, TIM1 break in 2, TIM9 channel 2, SPI4 MOSI, SAI1 serial data alternative A, SAI2 master clock alternative B, FMC address line 22, DCMI data 7, LCD green 1
6	VBAT	power_in	Backup battery supply pin for RTC and backup registers, 1.7 to 3.6 V
7	PC13	bidirectional	RTC alarm output or tamper input, oscillator mode, 5 V tolerant I/O supplied through power switch limited to 3 mA
8	PC14-OSC32_IN	input	32 kHz oscillator input pin, oscillator mode
9	PC15-OSC32_OUT	output	32 kHz oscillator output pin, oscillator mode
10	VSS	power_in	Ground supply pin connected to 0 V
11	VDD	power_in	Main digital supply pin, 1.7 to 3.6 V
12	PH0-OSC_IN	input	Main oscillator input pin for 4 to 26 MHz crystal, oscillator mode
13	PH1-OSC_OUT	output	Main oscillator output pin for 4 to 26 MHz crystal, oscillator mode
14	NRST	bidirectional	Reset pin with internal weak pull-up, active low, with optional capacitor filtering
15	PC0	bidirectional	DFSDM1 clock in 0, DFSDM1 data in 4, SAI2 frame sync alternative B, OTG HS ULPI stop, FMC SDNWE, LCD red 5, ADC1/2/3 channel 10
16	PC1	bidirectional	Trace data 0, DFSDM1 data in 0, SPI2 MOSI, SAI1 serial data alternative A, DFSDM1 clock in 4, Ethernet MDC, MDIOS MDC, ADC1/2/3 channel 11, RTC tamper 3
17	PC2	bidirectional	DFSDM1 clock in 1, SPI2 MISO, DFSDM1 clock out, OTG HS ULPI direction, Ethernet MII transmit data 2, FMC SDNE0, ADC1/2/3 channel 12
18	PC3	bidirectional	DFSDM1 data in 1, SPI2 MOSI, OTG HS ULPI next, Ethernet MII transmit clock, FMC SDCKE0, ADC1/2/3 channel 13
19	VSSA	power_in	Analog ground supply pin for ADC
20	VREF+	power_in	ADC positive reference voltage, 0.75 to VDD
21	VDDA	power_in	Analog supply pin for ADC, 1.7 to 3.6 V
22	PA0-WKUP	bidirectional	TIM2 channel 1 or ETR, TIM5 channel 1, TIM8 ETR, USART2 CTS, UART4 TX, SAI2 serial data alternative B, Ethernet MII CRS, ADC1/2/3 channel 0, wakeup pin 1
23	PA1	bidirectional	TIM2 channel 2, TIM5 channel 2, USART2 RTS, UART4 RX, QUADSPI bank 1 IO3, SAI2 master clock alternative B, Ethernet MII RX_CLK/RMII REF_CLK, LCD red 2, ADC1/2/3 channel 1
24	PA2	bidirectional	TIM2 channel 3, TIM5 channel 3, TIM9 channel 1, USART2 TX, SAI2 serial clock alternative B, Ethernet MDIO, MDIOS MDIO, LCD red 1, ADC1/2/3 channel 2, wakeup pin 2
25	PA3	bidirectional	TIM2 channel 4, TIM5 channel 4, TIM9 channel 2, USART2 RX, LCD blue 2, OTG HS ULPI data 0, Ethernet MII COL, LCD blue 5, ADC1/2/3 channel 3
26	VSS	power_in	Ground supply pin connected to 0 V
27	VDD	power_in	Main digital supply pin, 1.7 to 3.6 V
28	PA4	bidirectional	SPI1 chip select or I2S1 word select, SPI3 chip select, USART2 clock, SPI6 chip select, OTG HS SOF, DCMI HSYNC, LCD VSYNC, DAC1 output, ADC1/2 channel 4
29	PA5	bidirectional	TIM2 channel 1 or ETR, TIM8 channel 1N, SPI1 clock, SPI6 clock, OTG HS ULPI clock, LCD red 4, DAC2 output, ADC1/2 channel 5
30	PA6	bidirectional	TIM1 break in, TIM3 channel 1, TIM8 break in, SPI1 MISO, SPI6 MISO, TIM13 channel 1, MDIOS MDC, DCMI PIXCLK, LCD green 2, ADC1/2 channel 6
31	PA7	bidirectional	TIM1 channel 1N, TIM3 channel 2, TIM8 channel 1N, SPI1 MOSI or I2S1 serial data, SPI6 MOSI, TIM14 channel 1, Ethernet MII RX_DV or RMII CRS_DV, FMC SDNWE, ADC1/2 channel 7
32	PC4	bidirectional	DFSDM1 clock in 2, I2S1 master clock, SPDIF receiver 2, Ethernet MII RXD0 or RMII RXD0, FMC SDNE0, ADC1/2 channel 14
33	PC5	bidirectional	DFSDM1 data in 2, SPDIF receiver 3, Ethernet MII RXD1 or RMII RXD1, FMC SDCKE0, ADC1/2 channel 15
34	PB0	bidirectional	TIM1 channel 2N, TIM3 channel 3, TIM8 channel 2N, DFSDM1 clock out, UART4 CTS, LCD red 3, OTG HS ULPI data 1, Ethernet MII RXD2, LCD green 1, ADC1/2 channel 8
35	PB1	bidirectional	TIM1 channel 3N, TIM3 channel 4, TIM8 channel 3N, DFSDM1 data in 1, LCD red 6, OTG HS ULPI data 2, Ethernet MII RXD3, LCD green 0, ADC1/2 channel 9
36	PB2	bidirectional	SAI1 serial data alternative A, SPI3 MOSI or I2S3 serial data, QUADSPI clock, DFSDM1 clock in 1
37	PE7	bidirectional	TIM1 ETR, DFSDM1 data in 2, UART7 RX, QUADSPI bank 2 IO0, FMC data 4
38	PE8	bidirectional	TIM1 channel 1N, DFSDM1 clock in 2, UART7 TX, QUADSPI bank 2 IO1, FMC data 5
39	PE9	bidirectional	TIM1 channel 1, DFSDM1 clock out, UART7 RTS, QUADSPI bank 2 IO2, FMC data 6
40	PE10	bidirectional	TIM1 channel 2N, DFSDM1 data in 4, UART7 CTS, QUADSPI bank 2 IO3, FMC data 7
41	PE11	bidirectional	TIM1 channel 2, SPI4 chip select, DFSDM1 clock in 4, SAI2 serial data alternative B, FMC data 8, LCD green 3
42	PE12	bidirectional	TIM1 channel 3N, SPI4 clock, DFSDM1 data in 5, SAI2 serial clock alternative B, FMC data 9, LCD blue 4
43	PE13	bidirectional	TIM1 channel 3, SPI4 MISO, DFSDM1 clock in 5, SAI2 frame sync alternative B, FMC data 10, LCD display enable
44	PE14	bidirectional	TIM1 channel 4, SPI4 MOSI, SAI2 master clock alternative B, FMC data 11, LCD clock
45	PE15	bidirectional	TIM1 break in, FMC data 12, LCD red 7
46	PB10	bidirectional	TIM2 channel 3, I2C2 clock, SPI2 clock or I2S2 clock, DFSDM1 data in 7, USART3 TX, QUADSPI bank 1 chip select, OTG HS ULPI data 3, Ethernet MII RX_ER, LCD green 4
47	PB11	bidirectional	TIM2 channel 4, I2C2 data, DFSDM1 clock in 7, USART3 RX, OTG HS ULPI data 4, Ethernet MII TX_EN or RMII TX_EN, DSI TE, LCD green 5
48	VCAP_1	passive	Capacitor pin for voltage regulator, connect 1 µF to 10 µF ceramic capacitor to VSS
49	VSS	power_in	Ground supply pin connected to 0 V
50	VDD	power_in	Main digital supply pin, 1.7 to 3.6 V
51	PB12	bidirectional	TIM1 break in, I2C2 SMB alert, SPI2 chip select or I2S2 word select, DFSDM1 data in 1, USART3 clock, UART5 RX, CAN2 RX, OTG HS ULPI data 5, Ethernet MII TXD0 or RMII TXD0, OTG HS ID
52	PB13	bidirectional	TIM1 channel 1N, SPI2 clock or I2S2 clock, DFSDM1 clock in 1, USART3 CTS, UART5 TX, CAN2 TX, OTG HS ULPI data 6, Ethernet MII TXD1 or RMII TXD1, OTG HS VBUS
53	PB14	bidirectional	TIM1 channel 2N, TIM8 channel 2N, USART1 TX, SPI2 MISO, DFSDM1 data in 2, USART3 RTS, UART4 RTS, TIM12 channel 1, SDMMC2 data 0, OTG HS DM
54	PB15	bidirectional	RTC reference input, TIM1 channel 3N, TIM8 channel 3N, USART1 RX, SPI2 MOSI or I2S2 serial data, DFSDM1 clock in 2, UART4 CTS, TIM12 channel 2, SDMMC2 data 1, OTG HS DP
55	PD8	bidirectional	DFSDM1 clock in 3, USART3 TX, SPDIF receiver 1, FMC data 13
56	PD9	bidirectional	DFSDM1 data in 3, USART3 RX, FMC data 14
57	PD10	bidirectional	DFSDM1 clock out, USART3 clock, FMC data 15, LCD blue 3
58	PD11	bidirectional	I2C4 SMB alert, USART3 CTS, QUADSPI bank 1 IO0, SAI2 serial data alternative A, FMC address line 16 or CLE
59	PD12	bidirectional	TIM4 channel 1, LPTIM1 IN1, I2C4 clock, USART3 RTS, QUADSPI bank 1 IO1, SAI2 frame sync alternative A, FMC address line 17 or ALE
60	PD13	bidirectional	TIM4 channel 2, LPTIM1 OUT, I2C4 data, QUADSPI bank 1 IO3, SAI2 serial clock alternative A, FMC address line 18
61	PD14	bidirectional	TIM4 channel 3, UART8 CTS, FMC data 0
62	PD15	bidirectional	TIM4 channel 4, UART8 RTS, FMC data 1
63	PC6	bidirectional	TIM3 channel 1, TIM8 channel 1, I2S2 master clock, DFSDM1 clock in 3, USART6 TX, FMC NWAIT, SDMMC2 data 6, SDMMC1 data 6, DCMI data 0, LCD HSYNC
64	PC7	bidirectional	TIM3 channel 2, TIM8 channel 2, I2S3 master clock, DFSDM1 data in 3, USART6 RX, FMC NE1, SDMMC2 data 7, SDMMC1 data 7, DCMI data 1, LCD green 6
65	PC8	bidirectional	Trace data 1, TIM3 channel 3, TIM8 channel 3, UART5 RTS, USART6 clock, FMC NE2 or NCE, SDMMC1 data 0, DCMI data 2
66	PC9	bidirectional	MCO2 clock output, TIM3 channel 4, TIM8 channel 4, I2C3 serial data, I2S clock input, UART5 CTS, QUADSPI bank 1 IO0, LCD green 3, SDMMC1 data 1, DCMI data 3, LCD blue 2
67	PA8	bidirectional	MCO1 clock output, TIM1 channel 1, TIM8 break in 2, I2C3 clock, USART1 clock, OTG FS SOF, CAN3 RX, UART7 RX, LCD blue 3, LCD red 6
68	PA9	bidirectional	TIM1 channel 2, I2C3 SMB alert, SPI2 clock or I2S2 clock, USART1 TX, DCMI data 0, LCD red 5, OTG FS VBUS
69	PA10	bidirectional	TIM1 channel 3, USART1 RX, LCD blue 4, OTG FS ID, MDIOS MDIO, DCMI data 1, LCD blue 1
70	PA11	bidirectional	TIM1 channel 4, SPI2 chip select or I2S2 word select, UART4 RX, USART1 CTS, CAN1 RX, OTG FS DM, LCD red 4
71	PA12	bidirectional	TIM1 ETR, SPI2 clock or I2S2 clock, UART4 TX, USART1 RTS, SAI2 frame sync alternative B, CAN1 TX, OTG FS DP, LCD red 5
72	PA13(JTMS-SWDIO)	bidirectional	JTAG TMS or SWD data I/O pin for debug interface
73	VCAP_2	passive	Capacitor pin for voltage regulator, connect 1 µF to 10 µF ceramic capacitor to VSS
74	VSS	power_in	Ground supply pin connected to 0 V
75	VDD	power_in	Main digital supply pin, 1.7 to 3.6 V
76	PA14(JTCK-SWCLK)	bidirectional	JTAG TCK or SWD clock pin for debug interface
77	PA15(JTDI)	bidirectional	JTAG TDI, TIM2 channel 1 or ETR, HDMI CEC, SPI1 chip select, SPI3 chip select, SPI6 chip select, UART4 RTS, CAN3 TX, UART7 TX
78	PC10	bidirectional	DFSDM1 clock in 5, SPI3 clock or I2S3 clock, USART3 TX, UART4 TX, QUADSPI bank 1 IO1, SDMMC1 data 2, DCMI data 8, LCD red 2
79	PC11	bidirectional	DFSDM1 data in 5, SPI3 MISO, USART3 RX, UART4 RX, QUADSPI bank 2 chip select, SDMMC1 data 3, DCMI data 4
80	PC12	bidirectional	Trace data 3, SPI3 MOSI or I2S3 serial data, USART3 clock, UART5 TX, SDMMC1 clock, DCMI data 9
81	PD0	bidirectional	DFSDM1 clock in 6, DFSDM1 data in 7, UART4 RX, CAN1 RX, FMC data 2
82	PD1	bidirectional	DFSDM1 data in 6, DFSDM1 clock in 7, UART4 TX, CAN1 TX, FMC data 3
83	PD2	bidirectional	Trace data 2, TIM3 ETR, UART5 RX, SDMMC1 command, DCMI data 11
84	PD3	bidirectional	DFSDM1 clock out, SPI2 clock or I2S2 clock, DFSDM1 data in 0, USART2 CTS, FMC clock, DCMI data 5, LCD green 7
85	PD4	bidirectional	DFSDM1 clock in 0, USART2 RTS, FMC read enable
86	PD5	bidirectional	USART2 TX, FMC write enable
87	PD6	bidirectional	DFSDM1 clock in 4, SPI3 MOSI or I2S3 serial data, SAI1 serial data alternative A, USART2 RX, DFSDM1 data in 1, SDMMC2 clock, FMC NWAIT, DCMI data 10, LCD blue 2
88	PD7	bidirectional	DFSDM1 data in 4, SPI1 MOSI or I2S1 serial data, DFSDM1 clock in 1, USART2 clock, SPDIF receiver 0, SDMMC2 command, FMC NE1
89	PB3(JTDO/TRACESWO)	bidirectional	JTAG TDO or SWO trace output, TIM2 channel 2, SPI1 clock or I2S1 clock, SPI3 clock or I2S3 clock, SPI6 clock, SDMMC2 data 2, CAN3 RX, UART7 RX
90	PB4(NJTRST)	bidirectional	JTAG NTRST, TIM3 channel 1, SPI1 MISO, SPI3 MISO, SPI2 chip select or I2S2 word select, SPI6 MISO, SDMMC2 data 3, CAN3 TX, UART7 TX
91	PB5	bidirectional	UART5 RX, TIM3 channel 2, I2C1 SMB alert, SPI1 MOSI or I2S1 serial data, SPI3 MOSI or I2S3 serial data, SPI6 MOSI, CAN2 RX, OTG HS ULPI data 7, Ethernet PPS OUT, FMC SDCKE1, DCMI data 10, LCD green 7
92	PB6	bidirectional	UART5 TX, TIM4 channel 1, HDMI CEC, I2C1 clock, DFSDM1 data in 5, USART1 TX, CAN2 TX, QUADSPI bank 1 chip select, I2C4 clock, FMC SDNE1, DCMI data 5
93	PB7	bidirectional	TIM4 channel 2, I2C1 data, DFSDM1 clock in 5, USART1 RX, I2C4 data, FMC NL, DCMI VSYNC
94	BOOT0	input	Boot pin, logic 0 selects boot from Flash memory or Option Bytes, logic 1 selects boot from System memory
95	PB8	bidirectional	I2C4 clock, TIM4 channel 3, TIM10 channel 1, I2C1 clock, DFSDM1 clock in 7, UART5 RX, CAN1 RX, SDMMC2 data 4, Ethernet MII TXD3, SDMMC1 data 4, DCMI data 6, LCD blue 6
96	PB9	bidirectional	I2C4 data, TIM4 channel 4, TIM11 channel 1, I2C1 data, SPI2 chip select or I2S2 word select, DFSDM1 data in 7, UART5 TX, CAN1 TX, SDMMC2 data 5, I2C4 SMB alert, SDMMC1 data 5, DCMI data 7, LCD blue 7
97	PE0	bidirectional	TIM4 ETR, LPTIM1 ETR, UART8 RX, SAI2 master clock alternative A, FMC NBL0, DCMI data 2
98	PE1	bidirectional	LPTIM1 IN2, UART8 TX, FMC NBL1, DCMI data 3
99	VSS	power_in	Ground supply pin connected to 0 V
100	VDD	power_in	Main digital supply pin, 1.7 to 3.6 V

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

CAD (KiCad official)

Symbol: STM32F765VGT6
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: stm32f765vgt6-etched.step / stm32f765vgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f765vgt6.step / stm32f765vgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (255 pp, sha256 6ed07ca1dc9c1c0f, retrieved 2026-09-24, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF