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STM32F722RET7

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f722ret7factory-2.0.0extractor-text
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STM32F722RET7

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STM32F722RET7 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply for the RTC, 32x32-bit backup registers and 4 Kbytes of backup SRAM; with internal reset OFF the VBAT functionality is lost and the pin should be connected to VDD.
2 PC13 bidirectional 5 V tolerant GPIO on the backup domain, supplied through the power switch (3 mA sink limit), so output speed must not exceed 2 MHz at 30 pF and it must not source current such as an LED; also RTC_TAMP1/RTC_TS/RTC_OUT and WKUP4.
3 PC14-OSC32_IN bidirectional 5 V tolerant backup-domain GPIO with the same 3 mA switch limit (2 MHz at 30 pF max, no current sourcing) that doubles as the 32 kHz LSE oscillator input OSC32_IN.
4 PC15-OSC32_OUT bidirectional 5 V tolerant backup-domain GPIO with the same 3 mA switch limit (2 MHz at 30 pF max, no current sourcing) that doubles as the 32 kHz LSE oscillator output OSC32_OUT.
5 PH0-OSC_IN bidirectional 5 V tolerant GPIO that serves as the HSE oscillator input OSC_IN for the 4-to-26 MHz crystal oscillator.
6 PH1-OSC_OUT bidirectional 5 V tolerant GPIO that serves as the HSE oscillator output OSC_OUT for the 4-to-26 MHz crystal oscillator.
7 NRST bidirectional Active-low bidirectional reset pin with a weak pull-up resistor (RST type), with its characteristics given in section 6.3.21.
8 PC0 bidirectional 5 V tolerant GPIO (FT) with ADC1/2/3_IN10 analog input and alternate functions SAI2_FS_B, OTG_HS_ULPI_STP and FMC_SDNWE.
9 PC1 bidirectional 5 V tolerant GPIO (FT) with ADC1/2/3_IN11 and RTC_TAMP3/WKUP3 functions, plus TRACED0, SPI2_MOSI/I2S2_SD and SAI1_SD_A alternate functions.
10 PC2 bidirectional 5 V tolerant GPIO (FT) with ADC1/2/3_IN12 analog input and alternate functions SPI2_MISO, OTG_HS_ULPI_DIR and FMC_SDNE0.
11 PC3 bidirectional 5 V tolerant GPIO (FT) with ADC1/2/3_IN13 analog input and alternate functions SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT and FMC_SDCKE0.
12 VSSA power_in Analog ground pin for the ADC, DAC and reference, referenced to VSS per the datasheet convention.
13 VDDA power_in Analog supply pin for the ADC, DAC and PLL blocks as drawn in the LQFP64 pinout figure; Table 10 instead labels this pin VREF+ (see review notes).
14 PA0-WKUP bidirectional 5 V tolerant GPIO with ADC1/2/3_IN0 and WKUP1 wake-up functions that becomes the internal reset input (active low) when the device is in regulator OFF / internal reset ON mode.
15 PA1 bidirectional 5 V tolerant GPIO (FT) with ADC1/2/3_IN1 analog input and alternate functions TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX and QUADSPI_BK1_IO3.
16 PA2 bidirectional 5 V tolerant GPIO (FT) with ADC1/2/3_IN2 and WKUP2 functions, plus TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX and SAI2_SCK_B.
17 PA3 bidirectional 5 V tolerant GPIO (FT) with ADC1/2/3_IN3 analog input and alternate functions TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX and OTG_HS_ULPI_D0.
18 VSS power_in Digital ground pin; all voltages are referenced to VSS.
19 VDD power_in Application supply pin for I/Os and internal regulator, operating over 1.7 V to 3.6 V.
20 PA4 bidirectional TTa I/O (3.3 V tolerant, directly connected to ADC) with ADC1/2_IN4 and DAC_OUT1 functions, plus SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS and USART2_CK.
21 PA5 bidirectional TTa I/O (3.3 V tolerant, directly connected to ADC) with ADC1/2_IN5 and DAC_OUT2 functions, plus TIM2_CH1/TIM2_ETR, SPI1_SCK/I2S1_CK and OTG_HS_ULPI_CK.
22 PA6 bidirectional 5 V tolerant GPIO (FT) with ADC1/2_IN6 analog input and alternate functions TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO and TIM13_CH1.
23 PA7 bidirectional 5 V tolerant GPIO (FT) with ADC1/2_IN7 analog input and alternate functions TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD and FMC_SDNWE.
24 PC4 bidirectional 5 V tolerant GPIO (FT) with ADC1/2_IN14 analog input and alternate functions I2S1_MCK and FMC_SDNE0.
25 PB0 bidirectional 5 V tolerant GPIO (FT) with ADC1/2_IN8 analog input and alternate functions TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS and OTG_HS_ULPI_D1.
26 PB1 bidirectional 5 V tolerant GPIO (FT) with ADC1/2_IN9 analog input and alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N and OTG_HS_ULPI_D2.
27 PB2 bidirectional 5 V tolerant GPIO (FT) with alternate functions SAI1_SD_A, SPI3_MOSI/I2S3_SD and QUADSPI_CLK.
28 PB10 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX and OTG_HS_ULPI_D3.
29 PB11 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions TIM2_CH4, I2C2_SDA, USART3_RX and OTG_HS_ULPI_D4.
30 VCAP_1 passive Voltage regulator output pin VCAP_1 that requires the external capacitor described in section 6.3.2 for regulator stability.
31 VSS power_in Digital ground pin; all voltages are referenced to VSS.
32 VDD power_in Application supply pin for I/Os and internal regulator, operating over 1.7 V to 3.6 V.
33 PB12 bidirectional 5 V tolerant GPIO with FTf-style I/O (FT structure) and alternate functions TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK and OTG_HS_ID.
34 PB13 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS and OTG_HS_ULPI_D6, plus OTG_HS_VBUS.
35 PB14 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, SDMMC2_D0 and OTG_HS_DM.
36 PB15 bidirectional 5 V tolerant GPIO (FT) with alternate functions RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, SDMMC2_D1 and OTG_HS_DP.
37 PC6 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDMMC2_D6 and SDMMC1_D6.
38 PC7 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC2_D7 and SDMMC1_D7.
39 PC8 bidirectional 5 V tolerant GPIO (FT) with alternate functions TRACED1, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK and SDMMC1_D0.
40 PC9 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN and SDMMC1_D1.
41 PA8 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions MCO1, TIM1_CH1, I2C3_SCL, USART1_CK and OTG_FS_SOF.
42 PA9 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX and OTG_FS_VBUS.
43 PA10 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM1_CH3, USART1_RX and OTG_FS_ID.
44 PA11 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM1_CH4, USART1_CTS, CAN1_RX and OTG_FS_DM.
45 PA12 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM1_ETR, USART1_RTS, SAI2_FS_B, CAN1_TX and OTG_FS_DP.
46 PA13(JTMS-SWDIO) bidirectional 5 V tolerant GPIO (FT) that carries the JTMS-SWDIO debug function of the SWJ port.
47 VSS power_in Digital ground pin; all voltages are referenced to VSS.
48 VDD power_in Application supply pin for I/Os and internal regulator, operating over 1.7 V to 3.6 V.
49 PA14(JTCK-SWCLK) bidirectional 5 V tolerant GPIO (FT) that carries the JTCK-SWCLK debug clock function of the SWJ port.
50 PA15(JTDI) bidirectional 5 V tolerant GPIO (FT) that carries the JTDI debug input function, also TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS and UART4_RTS.
51 PC10 bidirectional 5 V tolerant GPIO (FT) with alternate functions SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1 and SDMMC1_D2.
52 PC11 bidirectional 5 V tolerant GPIO (FT) with alternate functions SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS and SDMMC1_D3.
53 PC12 bidirectional 5 V tolerant GPIO (FT) with alternate functions TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX and SDMMC1_CK.
54 PD2 bidirectional 5 V tolerant GPIO (FT) with alternate functions TRACED2, TIM3_ETR, UART5_RX and SDMMC1_CMD.
55 PB3(JTDO/TRACESWO) bidirectional 5 V tolerant GPIO (FT) that carries the JTDO/TRACESWO debug function, also TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK and SDMMC2_D2.
56 PB4(NJTRST) bidirectional 5 V tolerant GPIO (FT) that carries the NJTRST debug reset function, also TIM3_CH1, SPI1_MISO, SPI3_MISO and SDMMC2_D3.
57 PB5 bidirectional 5 V tolerant GPIO (FT) with alternate functions TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, OTG_HS_ULPI_D7 and FMC_SDCKE1.
58 PB6 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions TIM4_CH1, I2C1_SCL, USART1_TX, QUADSPI_BK1_NCS and FMC_SDNE1.
59 PB7 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions TIM4_CH2, I2C1_SDA, USART1_RX and FMC_NL.
60 BOOT0 input Dedicated boot pin (BOOT0, also VPP) that selects the boot mode at startup and is shared with the Flash programming voltage function.
61 PB8 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDMMC2_D4 and SDMMC1_D4.
62 PB9 bidirectional 5 V tolerant GPIO with FTf structure (I2C Fm+ option) and alternate functions TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDMMC2_D5 and SDMMC1_D5.
63 VSS power_in Digital ground pin; all voltages are referenced to VSS.
64 VDD power_in Application supply pin for I/Os and internal regulator, operating over 1.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: STM32F722RET7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stm32f722ret7-etched.step / stm32f722ret7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f722ret7.step / stm32f722ret7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (230 pp, sha256 796622f99c268e7a, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF