component
STM32F429NIH6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-216. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
5 files changed
+941−552
README.md+122−68@@ -11,12 +11,41 @@ STM32F429NIH6 from STMicroelectronics, in a TFBGA-216. Pinout and pin descriptio | A1 | PE4 | bidirectional | GPIO Port E pin 4, 5V tolerant I/O for TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4, LCD_B0 | | A2 | PE3 | bidirectional | GPIO Port E pin 3, 5V tolerant I/O for TRACED0, SAI1_SD_B, FMC_A19 | | A3 | PE2 | bidirectional | GPIO Port E pin 2, 5V tolerant I/O for TRACECLK, SPI4_SCK, SAI1_MCLK_A, ETH_MII_TXD3, FMC_A23 |+| A4 | PG14 | bidirectional | |+| A5 | PE1 | bidirectional | |+| A6 | PE0 | bidirectional | |+| A7 | PB8 | bidirectional | |+| A8 | PB5 | bidirectional | |+| A9 | PB4 | bidirectional | | | B1 | PE5 | bidirectional | GPIO Port E pin 5, 5V tolerant I/O for TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, LCD_G0 | | B2 | PE6 | bidirectional | GPIO Port E pin 6, 5V tolerant I/O for TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, LCD_G1 |+| B3 | PG13 | bidirectional | |+| B4 | PB9 | bidirectional | |+| B5 | PB7 | bidirectional | |+| B6 | PB6 | bidirectional | |+| B7 | PG15 | bidirectional | |+| B8 | PG11 | bidirectional | |+| B9 | PJ13 | bidirectional | | | C1 | VBAT | power_in | Backup domain supply pin 1.8V to 3.6V for RTC and backup registers | | C2 | PI8 | bidirectional | GPIO Port I pin 8, 5V tolerant I/O with power switch (3mA limit), alternate function EVENTOUT, additional function TAMP_2 |+| C3 | PI4 | bidirectional | |+| C4 | PK7 | bidirectional | |+| C5 | PK6 | bidirectional | |+| C6 | PK5 | bidirectional | |+| C7 | PG12 | bidirectional | |+| C8 | PG10 | bidirectional | |+| C9 | PJ14 | bidirectional | | | D1 | PC13 | bidirectional | GPIO Port C pin 13, 5V tolerant I/O with power switch (3mA limit), alternate function EVENTOUT, additional function TAMP_1 |-| E1 | PC14 | bidirectional | GPIO Port C pin 14 OSC32_IN, 5V tolerant I/O with power switch, alternate functions: EVENTOUT, OSC32_IN |+| D2 | PF0 | bidirectional | |+| D3 | PI5 | bidirectional | |+| D4 | PI7 | bidirectional | |+| D5 | PI10 | bidirectional | GPIO Port I pin 10, 5V tolerant I/O for ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT |+| D6 | PI6 | bidirectional | |+| D7 | PK4 | bidirectional | |+| D8 | PK3 | bidirectional | |+| D9 | PG9 | bidirectional | |+| E1 | PC14/OSC32_IN | bidirectional | GPIO Port C pin 14 OSC32_IN, 5V tolerant I/O with power switch, alternate functions: EVENTOUT, OSC32_IN |+| E2 | PF1 | bidirectional | | | E3 | PI12 | bidirectional | GPIO Port I pin 12, 5V tolerant I/O for LCD_HSYNC, EVENTOUT | | E4 | PI9 | bidirectional | GPIO Port I pin 9, 5V tolerant I/O for CAN1_RX, FMC_D30, LCD_VSYNC, EVENTOUT | | E5 | PDR_ON | input | Power down reset control input pin |@@ -24,63 +53,33 @@ STM32F429NIH6 from STMicroelectronics, in a TFBGA-216. Pinout and pin descriptio | E7 | VDD | power_in | 3.3V main supply pin | | E8 | VDD | power_in | 3.3V main supply pin | | E9 | VDD | power_in | 3.3V main supply pin |-| E10 | VDD | power_in | 3.3V main supply pin |-| E11 | VCAP_2 | passive | External capacitor pin for on-chip regulator, 1µF capacitor required |-| E12 | PH13 | bidirectional | GPIO Port H pin 13, 5V tolerant I/O for TIM8_CH1N, CAN1_TX, FMC_D21, LCD_G2, EVENTOUT |-| E13 | PH14 | bidirectional | GPIO Port H pin 14, 5V tolerant I/O for TIM8_CH2N, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT |-| E14 | PI0 | bidirectional | GPIO Port I pin 0, 5V tolerant I/O for TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, DCMI_D13, LCD_G5, EVENTOUT |-| E15 | PA9 | bidirectional | GPIO Port A pin 9, 5V tolerant I/O for TIM1_CH2, I2C3_SMBA, USART1_TX, DCMI_D0, additional function OTG_FS_VBUS |-| F1 | PC15 | bidirectional | GPIO Port C pin 15 OSC32_OUT, 5V tolerant I/O with power switch, alternate functions: EVENTOUT, OSC32_OUT |-| F2 | PI11 | bidirectional | GPIO Port I pin 11, 5V tolerant I/O for OTG_HS_ULPI_DIR, EVENTOUT |-| F3 | PI10 | bidirectional | GPIO Port I pin 10, 5V tolerant I/O for ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT |+| F1 | PC15/OSC32_OUT | bidirectional | GPIO Port C pin 15 OSC32_OUT, 5V tolerant I/O with power switch, alternate functions: EVENTOUT, OSC32_OUT |+| F2 | VSS | power_in | Ground return pin |+| F3 | PI11 | bidirectional | GPIO Port I pin 11, 5V tolerant I/O for OTG_HS_ULPI_DIR, EVENTOUT | | F4 | VDD | power_in | 3.3V main supply pin | | F5 | VDD | power_in | 3.3V main supply pin | | F6 | VSS | power_in | Ground return pin | | F7 | VSS | power_in | Ground return pin | | F8 | VSS | power_in | Ground return pin | | F9 | VSS | power_in | Ground return pin |-| F10 | VSS | power_in | Ground return pin |-| F11 | VDD | power_in | 3.3V main supply pin |-| F12 | PK1 | bidirectional | GPIO Port K pin 1, 5V tolerant I/O for LCD_G6, EVENTOUT |-| F13 | PK2 | bidirectional | GPIO Port K pin 2, 5V tolerant I/O for LCD_G7, EVENTOUT |-| F14 | PC9 | bidirectional | GPIO Port C pin 9, 5V tolerant I/O for MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, SDIO_D1, DCMI_D3, EVENTOUT |-| F15 | PA8 | bidirectional | GPIO Port A pin 8, 5V tolerant I/O for MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, LCD_R6, EVENTOUT |-| G1 | PH0 | bidirectional | GPIO Port H pin 0 OSC_IN, 5V tolerant I/O, alternate functions: EVENTOUT, OSC_IN |+| G1 | PH0/OSC_IN | bidirectional | GPIO Port H pin 0 OSC_IN, 5V tolerant I/O, alternate functions: EVENTOUT, OSC_IN | | G2 | PF2 | bidirectional | GPIO Port F pin 2, 5V tolerant I/O for I2C2_SMBA, FMC_A2, EVENTOUT, additional function ADC3_IN4 | | G3 | PI13 | bidirectional | GPIO Port I pin 13, 5V tolerant I/O for LCD_VSYNC, EVENTOUT | | G4 | PI15 | bidirectional | GPIO Port I pin 15, 5V tolerant I/O for LCD_R0, EVENTOUT | | G5 | VDD | power_in | 3.3V main supply pin | | G6 | VSS | power_in | Ground return pin |-| G10 | VSS | power_in | Ground return pin |-| G11 | VDD | power_in | 3.3V main supply pin |-| G12 | PJ11 | bidirectional | GPIO Port J pin 11, 5V tolerant I/O for LCD_G4, EVENTOUT |-| G13 | PK0 | bidirectional | GPIO Port K pin 0, 5V tolerant I/O for LCD_G5, EVENTOUT |-| G14 | PC8 | bidirectional | GPIO Port C pin 8, 5V tolerant I/O for TIM3_CH3, TIM8_CH3, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT |-| G15 | PC7 | bidirectional | GPIO Port C pin 7, 5V tolerant I/O for TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDIO_D7, DCMI_D1, LCD_G6, EVENTOUT |-| H1 | PH1 | bidirectional | GPIO Port H pin 1 OSC_OUT, 5V tolerant I/O, alternate functions: EVENTOUT, OSC_OUT |+| H1 | PH1/OSC_OUT | bidirectional | GPIO Port H pin 1 OSC_OUT, 5V tolerant I/O, alternate functions: EVENTOUT, OSC_OUT | | H2 | PF3 | bidirectional | GPIO Port F pin 3, 5V tolerant I/O for FMC_A3, EVENTOUT, additional function ADC3_IN9 | | H3 | PI14 | bidirectional | GPIO Port I pin 14, 5V tolerant I/O for LCD_CLK, EVENTOUT | | H4 | PH4 | bidirectional | GPIO Port H pin 4, 5V tolerant I/O for I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT | | H5 | VDD | power_in | 3.3V main supply pin | | H6 | VSS | power_in | Ground return pin |-| H10 | VSS | power_in | Ground return pin |-| H11 | VDD | power_in | 3.3V main supply pin |-| H12 | PJ8 | bidirectional | GPIO Port J pin 8, 5V tolerant I/O for LCD_G1, EVENTOUT |-| H13 | PJ10 | bidirectional | GPIO Port J pin 10, 5V tolerant I/O for LCD_G3, EVENTOUT |-| H14 | PG8 | bidirectional | GPIO Port G pin 8, 5V tolerant I/O for SPI6_NSS, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, EVENTOUT |-| H15 | PC6 | bidirectional | GPIO Port C pin 6, 5V tolerant I/O for TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, LCD_HSYNC, EVENTOUT |-| J1 | NRST | bidirectional | Reset input pin with internal weak pull-up resistor for manual reset or watchdog reset |+| J1 | NRST | input | Reset input pin with internal weak pull-up resistor for manual reset or watchdog reset | | J2 | PF4 | bidirectional | GPIO Port F pin 4, 5V tolerant I/O for FMC_A4, EVENTOUT, additional function ADC3_IN14 | | J3 | PH5 | bidirectional | GPIO Port H pin 5, 5V tolerant I/O for I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT | | J4 | PH3 | bidirectional | GPIO Port H pin 3, 5V tolerant I/O for ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT | | J5 | VDD | power_in | 3.3V main supply pin | | J6 | VSS | power_in | Ground return pin |-| J10 | VSS | power_in | Ground return pin |-| J11 | VDD | power_in | 3.3V main supply pin |-| J12 | PJ7 | bidirectional | GPIO Port J pin 7, 5V tolerant I/O for LCD_G0, EVENTOUT |-| J13 | PJ9 | bidirectional | GPIO Port J pin 9, 5V tolerant I/O for LCD_G2, EVENTOUT |-| J14 | PG7 | bidirectional | GPIO Port G pin 7, 5V tolerant I/O for USART6_CK, FMC_INT3, DCMI_D13, LCD_CLK, EVENTOUT |-| J15 | PG6 | bidirectional | GPIO Port G pin 6, 5V tolerant I/O for FMC_INT2, DCMI_D12, LCD_R7, EVENTOUT | | K1 | PF7 | bidirectional | GPIO Port F pin 7, 5V tolerant I/O for TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_Tx, FMC_NREG, EVENTOUT, additional function ADC3_IN5 | | K2 | PF6 | bidirectional | GPIO Port F pin 6, 5V tolerant I/O for TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_Rx, FMC_NIORD, EVENTOUT, additional function ADC3_IN4 | | K3 | PF5 | bidirectional | GPIO Port F pin 5, 5V tolerant I/O for FMC_A5, EVENTOUT, additional function ADC3_IN15 |@@ -90,12 +89,6 @@ STM32F429NIH6 from STMicroelectronics, in a TFBGA-216. Pinout and pin descriptio | K7 | VSS | power_in | Ground return pin | | K8 | VSS | power_in | Ground return pin | | K9 | VSS | power_in | Ground return pin |-| K10 | VSS | power_in | Ground return pin |-| K11 | VDD | power_in | 3.3V main supply pin |-| K12 | PJ6 | bidirectional | GPIO Port J pin 6, 5V tolerant I/O for LCD_R7, EVENTOUT |-| K13 | PD15 | bidirectional | GPIO Port D pin 15, 5V tolerant I/O for TIM4_CH4, FMC_D1, EVENTOUT |-| K14 | PB13 | bidirectional | GPIO Port B pin 13, 5V tolerant I/O for TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, additional function OTG_HS_VBUS |-| K15 | PD10 | bidirectional | GPIO Port D pin 10, 5V tolerant I/O for USART3_CK, FMC_D15, LCD_B3, EVENTOUT | | L1 | PF10 | bidirectional | GPIO Port F pin 10, 5V tolerant I/O for FMC_INTR, DCMI_D11, LCD_DE, EVENTOUT, additional function ADC3_IN8 | | L2 | PF9 | bidirectional | GPIO Port F pin 9, 5V tolerant I/O for SPI5_MOSI, SAI1_FS_B, TIM14_CH1, FMC_CD, EVENTOUT, additional function ADC3_IN7 | | L3 | PF8 | bidirectional | GPIO Port F pin 8, 5V tolerant I/O for SPI5_MISO, SAI1_SCK_B, TIM13_CH1, FMC_NIOWR, EVENTOUT, additional function ADC3_IN6 |@@ -105,41 +98,24 @@ STM32F429NIH6 from STMicroelectronics, in a TFBGA-216. Pinout and pin descriptio | L7 | VDD | power_in | 3.3V main supply pin | | L8 | VDD | power_in | 3.3V main supply pin | | L9 | VDD | power_in | 3.3V main supply pin |-| L10 | VDD | power_in | 3.3V main supply pin |-| L11 | VCAP_1 | passive | External capacitor pin for on-chip regulator, 1µF capacitor required |-| L12 | PD14 | bidirectional | GPIO Port D pin 14, 5V tolerant I/O for TIM4_CH3, FMC_D0, EVENTOUT |-| L13 | PB12 | bidirectional | GPIO Port B pin 12, 5V tolerant I/O for TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OTG_HS_ID, EVENTOUT |-| L14 | PD9 | bidirectional | GPIO Port D pin 9, 5V tolerant I/O for USART3_RX, FMC_D14, EVENTOUT |-| L15 | PD8 | bidirectional | GPIO Port D pin 8, 5V tolerant I/O for USART3_TX, FMC_D13, EVENTOUT | | M1 | VSSA | power_in | Analog ground return pin | | M2 | PC0 | bidirectional | GPIO Port C pin 0, 5V tolerant I/O for OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT, additional function ADC123_IN10 | | M3 | PC1 | bidirectional | GPIO Port C pin 1, 5V tolerant I/O for ETH_MDC, EVENTOUT, additional function ADC123_IN11 | | M4 | PC2 | bidirectional | GPIO Port C pin 2, 5V tolerant I/O for SPI2_MISO, I2S2ext_SD, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT, additional function ADC123_IN12 |-| M5 | PB2 | bidirectional | GPIO Port B pin 2 BOOT1, 5V tolerant I/O for EVENTOUT |+| M5 | PB2/BOOT1 | bidirectional | GPIO Port B pin 2 BOOT1, 5V tolerant I/O for EVENTOUT | | M6 | PF12 | bidirectional | GPIO Port F pin 12, 5V tolerant I/O for FMC_A6, EVENTOUT | | M7 | PG1 | bidirectional | GPIO Port G pin 1, 5V tolerant I/O for FMC_A11, EVENTOUT | | M8 | PF15 | bidirectional | GPIO Port F pin 15, 5V tolerant I/O for FMC_A9, EVENTOUT | | M9 | PJ4 | bidirectional | GPIO Port J pin 4, 5V tolerant I/O for LCD_R5, EVENTOUT |-| M10 | PD11 | bidirectional | GPIO Port D pin 11, 5V tolerant I/O for USART3_CTS, FMC_A16, EVENTOUT |-| M11 | PD12 | bidirectional | GPIO Port D pin 12, 5V tolerant I/O for TIM4_CH1, USART3_RTS, FMC_A17, EVENTOUT |-| M12 | PG3 | bidirectional | GPIO Port G pin 3, 5V tolerant I/O for FMC_A13, EVENTOUT |-| M13 | PG2 | bidirectional | GPIO Port G pin 2, 5V tolerant I/O for FMC_A12, EVENTOUT |-| M14 | PJ5 | bidirectional | GPIO Port J pin 5, 5V tolerant I/O for LCD_R6, EVENTOUT |-| M15 | PH12 | bidirectional | GPIO Port H pin 12, 5V tolerant I/O for TIM5_CH3, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT | | N1 | VREF- | power_in | Analog reference negative voltage pin for ADC | | N2 | PA1 | bidirectional | GPIO Port A pin 1, 5V tolerant I/O for TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, ETH_MII_RX_CLK/ETH_RMII_REF_CLK, EVENTOUT, additional function ADC123_IN1 |-| N3 | PA0 | bidirectional | GPIO Port A pin 0 WKUP, 5V tolerant I/O for TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, ETH_MII_CRS, EVENTOUT, additional function ADC123_IN0/WKUP |+| N3 | PA0/WKUP | bidirectional | GPIO Port A pin 0 WKUP, 5V tolerant I/O for TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, ETH_MII_CRS, EVENTOUT, additional function ADC123_IN0/WKUP | | N4 | PA4 | bidirectional | GPIO Port A pin 4, 3.3V tolerant I/O for SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, EVENTOUT, additional function ADC12_IN4/DAC_OUT1 | | N5 | PC4 | bidirectional | GPIO Port C pin 4, 5V tolerant I/O for ETH_MII_RXD0/ETH_RMII_RXD0, EVENTOUT, additional function ADC12_IN14 | | N6 | PF13 | bidirectional | GPIO Port F pin 13, 5V tolerant I/O for FMC_A7, EVENTOUT | | N7 | PG0 | bidirectional | GPIO Port G pin 0, 5V tolerant I/O for FMC_A10, EVENTOUT | | N8 | PJ3 | bidirectional | GPIO Port J pin 3, 5V tolerant I/O for LCD_R4, EVENTOUT | | N9 | PE8 | bidirectional | GPIO Port E pin 8, 5V tolerant I/O for TIM1_CH1N, UART7_Tx, FMC_D5, EVENTOUT |-| N11 | PG5 | bidirectional | GPIO Port G pin 5, 5V tolerant I/O for FMC_A15/FMC_BA1, EVENTOUT |-| N12 | PG4 | bidirectional | GPIO Port G pin 4, 5V tolerant I/O for FMC_A14/FMC_BA0, EVENTOUT |-| N13 | PH7 | bidirectional | GPIO Port H pin 7, 5V tolerant I/O for I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT |-| N14 | PH9 | bidirectional | GPIO Port H pin 9, 5V tolerant I/O for I2C3_SMBA, TIM12_CH2, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT |-| N15 | PH11 | bidirectional | GPIO Port H pin 11, 5V tolerant I/O for TIM5_CH2, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT | | P1 | VREF+ | power_in | Analog reference positive voltage pin for ADC, connect to VDDA or separate reference | | P2 | PA2 | bidirectional | GPIO Port A pin 2, 5V tolerant I/O for TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, ETH_MDIO, EVENTOUT, additional function ADC123_IN2 | | P3 | PA6 | bidirectional | GPIO Port A pin 6, 5V tolerant I/O for TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM13_CH1, DCMI_PIXCLK, LCD_G2, EVENTOUT, additional function ADC12_IN6 |@@ -149,12 +125,6 @@ STM32F429NIH6 from STMicroelectronics, in a TFBGA-216. Pinout and pin descriptio | P7 | PJ2 | bidirectional | GPIO Port J pin 2, 5V tolerant I/O for LCD_R3, EVENTOUT | | P8 | PF11 | bidirectional | GPIO Port F pin 11, 5V tolerant I/O for SPI5_MOSI, FMC_SDNRAS, DCMI_D12, EVENTOUT | | P9 | PE9 | bidirectional | GPIO Port E pin 9, 5V tolerant I/O for TIM1_CH1, FMC_D6, EVENTOUT |-| P10 | PE11 | bidirectional | GPIO Port E pin 11, 5V tolerant I/O for TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3, EVENTOUT |-| P11 | PE14 | bidirectional | GPIO Port E pin 14, 5V tolerant I/O for TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK, EVENTOUT |-| P12 | PB10 | bidirectional | GPIO Port B pin 10, 5V tolerant I/O for TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT |-| P13 | PH6 | bidirectional | GPIO Port H pin 6, 5V tolerant I/O for I2C2_SMBA, SPI5_SCK, TIM12_CH1, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT |-| P14 | PH8 | bidirectional | GPIO Port H pin 8, 5V tolerant I/O for I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT |-| P15 | PH10 | bidirectional | GPIO Port H pin 10, 5V tolerant I/O for TIM5_CH1, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT | | R1 | VDDA | power_in | Analog power supply pin 1.8V to 3.6V for ADC, DAC, and analog circuits | | R2 | PA3 | bidirectional | GPIO Port A pin 3, 5V tolerant I/O for TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, EVENTOUT, additional function ADC123_IN3 | | R3 | PA7 | bidirectional | GPIO Port A pin 7, 5V tolerant I/O for TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI, TIM14_CH1, ETH_MII_RX_DV/ETH_RMII_CRS_DV, EVENTOUT, additional function ADC12_IN7 |@@ -164,6 +134,90 @@ STM32F429NIH6 from STMicroelectronics, in a TFBGA-216. Pinout and pin descriptio | R7 | PJ1 | bidirectional | GPIO Port J pin 1, 5V tolerant I/O for LCD_R2, EVENTOUT | | R8 | PE7 | bidirectional | GPIO Port E pin 7, 5V tolerant I/O for TIM1_ETR, UART7_Rx, FMC_D4, EVENTOUT | | R9 | PE10 | bidirectional | GPIO Port E pin 10, 5V tolerant I/O for TIM1_CH2N, FMC_D7, EVENTOUT |+| A10 | PB3 | bidirectional | |+| A11 | PD7 | bidirectional | |+| A12 | PC12 | bidirectional | |+| A13 | PA15 | bidirectional | |+| A14 | PA14 | bidirectional | |+| A15 | PA13 | bidirectional | |+| B10 | PJ12 | bidirectional | |+| B11 | PD6 | bidirectional | |+| B12 | PD0 | bidirectional | |+| B13 | PC11 | bidirectional | |+| B14 | PC10 | bidirectional | |+| B15 | PA12 | bidirectional | |+| C10 | PD5 | bidirectional | |+| C11 | PD3 | bidirectional | |+| C12 | PD1 | bidirectional | |+| C13 | PI3 | bidirectional | |+| C14 | PI2 | bidirectional | |+| C15 | PA11 | bidirectional | |+| D10 | PJ15 | bidirectional | |+| D11 | PD4 | bidirectional | |+| D12 | PD2 | bidirectional | |+| D13 | PH15 | bidirectional | |+| D14 | PI1 | bidirectional | |+| D15 | PA10 | bidirectional | |+| E10 | VDD | power_in | 3.3V main supply pin |+| E11 | VCAP_2 | power_in | External capacitor pin for on-chip regulator, 1µF capacitor required |+| E12 | PH13 | bidirectional | GPIO Port H pin 13, 5V tolerant I/O for TIM8_CH1N, CAN1_TX, FMC_D21, LCD_G2, EVENTOUT |+| E13 | PH14 | bidirectional | GPIO Port H pin 14, 5V tolerant I/O for TIM8_CH2N, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT |+| E14 | PI0 | bidirectional | GPIO Port I pin 0, 5V tolerant I/O for TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, DCMI_D13, LCD_G5, EVENTOUT |+| E15 | PA9 | bidirectional | GPIO Port A pin 9, 5V tolerant I/O for TIM1_CH2, I2C3_SMBA, USART1_TX, DCMI_D0, additional function OTG_FS_VBUS |+| F10 | VSS | power_in | Ground return pin |+| F11 | VDD | power_in | 3.3V main supply pin |+| F12 | PK1 | bidirectional | GPIO Port K pin 1, 5V tolerant I/O for LCD_G6, EVENTOUT |+| F13 | PK2 | bidirectional | GPIO Port K pin 2, 5V tolerant I/O for LCD_G7, EVENTOUT |+| F14 | PC9 | bidirectional | GPIO Port C pin 9, 5V tolerant I/O for MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, SDIO_D1, DCMI_D3, EVENTOUT |+| F15 | PA8 | bidirectional | GPIO Port A pin 8, 5V tolerant I/O for MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, LCD_R6, EVENTOUT |+| G10 | VSS | power_in | Ground return pin |+| G11 | VDD | power_in | 3.3V main supply pin |+| G12 | PJ11 | bidirectional | GPIO Port J pin 11, 5V tolerant I/O for LCD_G4, EVENTOUT |+| G13 | PK0 | bidirectional | GPIO Port K pin 0, 5V tolerant I/O for LCD_G5, EVENTOUT |+| G14 | PC8 | bidirectional | GPIO Port C pin 8, 5V tolerant I/O for TIM3_CH3, TIM8_CH3, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT |+| G15 | PC7 | bidirectional | GPIO Port C pin 7, 5V tolerant I/O for TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDIO_D7, DCMI_D1, LCD_G6, EVENTOUT |+| H10 | VSS | power_in | Ground return pin |+| H11 | VDD | power_in | 3.3V main supply pin |+| H12 | PJ8 | bidirectional | GPIO Port J pin 8, 5V tolerant I/O for LCD_G1, EVENTOUT |+| H13 | PJ10 | bidirectional | GPIO Port J pin 10, 5V tolerant I/O for LCD_G3, EVENTOUT |+| H14 | PG8 | bidirectional | GPIO Port G pin 8, 5V tolerant I/O for SPI6_NSS, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, EVENTOUT |+| H15 | PC6 | bidirectional | GPIO Port C pin 6, 5V tolerant I/O for TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, LCD_HSYNC, EVENTOUT |+| J10 | VSS | power_in | Ground return pin |+| J11 | VDD | power_in | 3.3V main supply pin |+| J12 | PJ7 | bidirectional | GPIO Port J pin 7, 5V tolerant I/O for LCD_G0, EVENTOUT |+| J13 | PJ9 | bidirectional | GPIO Port J pin 9, 5V tolerant I/O for LCD_G2, EVENTOUT |+| J14 | PG7 | bidirectional | GPIO Port G pin 7, 5V tolerant I/O for USART6_CK, FMC_INT3, DCMI_D13, LCD_CLK, EVENTOUT |+| J15 | PG6 | bidirectional | GPIO Port G pin 6, 5V tolerant I/O for FMC_INT2, DCMI_D12, LCD_R7, EVENTOUT |+| K10 | VSS | power_in | Ground return pin |+| K11 | VDD | power_in | 3.3V main supply pin |+| K12 | PJ6 | bidirectional | GPIO Port J pin 6, 5V tolerant I/O for LCD_R7, EVENTOUT |+| K13 | PD15 | bidirectional | GPIO Port D pin 15, 5V tolerant I/O for TIM4_CH4, FMC_D1, EVENTOUT |+| K14 | PB13 | bidirectional | GPIO Port B pin 13, 5V tolerant I/O for TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, additional function OTG_HS_VBUS |+| K15 | PD10 | bidirectional | GPIO Port D pin 10, 5V tolerant I/O for USART3_CK, FMC_D15, LCD_B3, EVENTOUT |+| L10 | VDD | power_in | 3.3V main supply pin |+| L11 | VCAP_1 | power_in | External capacitor pin for on-chip regulator, 1µF capacitor required |+| L12 | PD14 | bidirectional | GPIO Port D pin 14, 5V tolerant I/O for TIM4_CH3, FMC_D0, EVENTOUT |+| L13 | PB12 | bidirectional | GPIO Port B pin 12, 5V tolerant I/O for TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OTG_HS_ID, EVENTOUT |+| L14 | PD9 | bidirectional | GPIO Port D pin 9, 5V tolerant I/O for USART3_RX, FMC_D14, EVENTOUT |+| L15 | PD8 | bidirectional | GPIO Port D pin 8, 5V tolerant I/O for USART3_TX, FMC_D13, EVENTOUT |+| M10 | PD12 | bidirectional | GPIO Port D pin 12, 5V tolerant I/O for TIM4_CH1, USART3_RTS, FMC_A17, EVENTOUT |+| M11 | PD13 | bidirectional | |+| M12 | PG3 | bidirectional | GPIO Port G pin 3, 5V tolerant I/O for FMC_A13, EVENTOUT |+| M13 | PG2 | bidirectional | GPIO Port G pin 2, 5V tolerant I/O for FMC_A12, EVENTOUT |+| M14 | PJ5 | bidirectional | GPIO Port J pin 5, 5V tolerant I/O for LCD_R6, EVENTOUT |+| M15 | PH12 | bidirectional | GPIO Port H pin 12, 5V tolerant I/O for TIM5_CH3, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT |+| N10 | PD11 | bidirectional | GPIO Port D pin 11, 5V tolerant I/O for USART3_CTS, FMC_A16, EVENTOUT |+| N11 | PG5 | bidirectional | GPIO Port G pin 5, 5V tolerant I/O for FMC_A15/FMC_BA1, EVENTOUT |+| N12 | PG4 | bidirectional | GPIO Port G pin 4, 5V tolerant I/O for FMC_A14/FMC_BA0, EVENTOUT |+| N13 | PH7 | bidirectional | GPIO Port H pin 7, 5V tolerant I/O for I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT |+| N14 | PH9 | bidirectional | GPIO Port H pin 9, 5V tolerant I/O for I2C3_SMBA, TIM12_CH2, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT |+| N15 | PH11 | bidirectional | GPIO Port H pin 11, 5V tolerant I/O for TIM5_CH2, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT |+| P10 | PE11 | bidirectional | GPIO Port E pin 11, 5V tolerant I/O for TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3, EVENTOUT |+| P11 | PE14 | bidirectional | GPIO Port E pin 14, 5V tolerant I/O for TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK, EVENTOUT |+| P12 | PB10 | bidirectional | GPIO Port B pin 10, 5V tolerant I/O for TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT |+| P13 | PH6 | bidirectional | GPIO Port H pin 6, 5V tolerant I/O for I2C2_SMBA, SPI5_SCK, TIM12_CH1, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT |+| P14 | PH8 | bidirectional | GPIO Port H pin 8, 5V tolerant I/O for I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT |+| P15 | PH10 | bidirectional | GPIO Port H pin 10, 5V tolerant I/O for TIM5_CH1, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT | | R10 | PE12 | bidirectional | GPIO Port E pin 12, 5V tolerant I/O for TIM1_CH3N, SPI4_SCK, FMC_D9, LCD_B4, EVENTOUT | | R11 | PE15 | bidirectional | GPIO Port E pin 15, 5V tolerant I/O for TIM1_BKIN, FMC_D12, LCD_R7, EVENTOUT | | R12 | PE13 | bidirectional | GPIO Port E pin 13, 5V tolerant I/O for TIM1_CH3N, SPI4_MISO, FMC_D10, LCD_DE, EVENTOUT |
package.json+2−2@@ -1,6 +1,6 @@ { "slug": "stm32f429nih6",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-216. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.", "tags": [@@ -1057,4 +1057,4 @@ "footprint": "viewers/footprint.html" } }-}+}
page.json+4−4@@ -4,7 +4,7 @@ "slug": "stm32f429nih6", "title": "STM32F429NIH6", "brief": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-216. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -1084,7 +1084,7 @@ "viewers/symbol.html", "viewers/footprint.html" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-216. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "org": "adom" }
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name="PI12" x="-17.78" y="-22.86" length="middle" direction="io"/>+ <pin name="PI9" x="-17.78" y="-25.4" length="middle" direction="io"/>+ <pin name="PDR_ON" x="-17.78" y="-27.94" length="middle" direction="in"/>+ <pin name="BOOT0" x="-17.78" y="-30.48" length="middle" direction="in"/>+ <pin name="VDD" x="-17.78" y="-33.02" length="middle" direction="pwr"/>+ <pin name="VDD@2" x="-17.78" y="-35.56" length="middle" direction="pwr"/>+ <pin name="VDD@3" x="-17.78" y="-38.1" length="middle" direction="pwr"/>+ <pin name="VDD@4" x="-17.78" y="-40.64" length="middle" direction="pwr"/>+ <pin name="VCAP_2" x="-17.78" y="-43.18" length="middle" direction="pwr"/>+ <pin name="PH13" x="-17.78" y="-45.72" length="middle" direction="io"/>+ <pin name="PH14" x="-17.78" y="-48.26" length="middle" direction="io"/>+ <pin name="PI0" x="-17.78" y="-50.8" length="middle" direction="io"/>+ <pin name="PA9" x="-17.78" y="-53.34" length="middle" direction="io"/>+ <pin name="PC15/OSC32_OUT" x="-17.78" y="-55.88" length="middle" direction="io"/>+ <pin name="VSS" x="-17.78" y="-58.42" length="middle" direction="pwr"/>+ <pin name="PI11" x="-17.78" y="-60.96" length="middle" direction="io"/>+ <pin name="VDD@5" x="-17.78" y="-63.5" length="middle" direction="pwr"/>+ <pin name="VDD@6" x="-17.78" y="-66.04" length="middle" direction="pwr"/>+ <pin name="VSS@2" x="-17.78" y="-68.58" length="middle" direction="pwr"/>+ <pin name="VSS@3" x="-17.78" y="-71.12" length="middle" direction="pwr"/>+ <pin name="VSS@4" x="-17.78" y="-73.66" length="middle" direction="pwr"/>+ <pin name="VSS@5" x="-17.78" y="-76.2" length="middle" direction="pwr"/>+ <pin name="VSS@6" x="-17.78" y="-78.74" length="middle" direction="pwr"/>+ <pin name="VDD@7" x="-17.78" y="-81.28" length="middle" direction="pwr"/>+ <pin name="PK1" x="-17.78" y="-83.82" length="middle" direction="io"/>+ <pin name="PK2" x="-17.78" y="-86.36" length="middle" direction="io"/>+ <pin name="PC9" x="-17.78" y="-88.9" length="middle" direction="io"/>+ <pin name="PA8" x="-17.78" y="-91.44" length="middle" direction="io"/>+ <pin name="PH0/OSC_IN" x="-17.78" y="-93.98" length="middle" direction="io"/>+ <pin name="PF2" x="-17.78" y="-96.52" length="middle" direction="io"/>+ <pin name="PI13" x="-17.78" y="-99.06" length="middle" direction="io"/>+ <pin name="PI15" x="-17.78" y="-101.6" length="middle" direction="io"/>+ <pin name="VDD@8" x="-17.78" y="-104.14" length="middle" direction="pwr"/>+ <pin name="VSS@7" x="-17.78" y="-106.68" length="middle" direction="pwr"/>+ <pin name="VSS@8" x="-17.78" y="-109.22" length="middle" direction="pwr"/>+ <pin name="VDD@9" x="-17.78" y="-111.76" length="middle" direction="pwr"/>+ <pin name="PJ11" x="-17.78" y="-114.3" length="middle" direction="io"/>+ <pin name="PK0" x="-17.78" y="-116.84" length="middle" direction="io"/>+ <pin name="PC8" x="-17.78" y="-119.38" length="middle" direction="io"/>+ <pin name="PC7" x="-17.78" y="-121.92" length="middle" direction="io"/>+ <pin name="PH1/OSC_OUT" x="-17.78" y="-124.46" length="middle" direction="io"/>+ <pin name="PF3" x="-17.78" y="-127" length="middle" direction="io"/>+ <pin name="PI14" x="-17.78" y="-129.54" length="middle" direction="io"/>+ <pin name="PH4" x="-17.78" y="-132.08" length="middle" direction="io"/>+ <pin name="VDD@10" x="-17.78" y="-134.62" length="middle" direction="pwr"/>+ <pin name="VSS@9" x="-17.78" y="-137.16" length="middle" direction="pwr"/>+ <pin name="PB15" x="17.78" y="134.62" length="middle" direction="io" rot="R180"/>+ <pin name="PB14" x="17.78" y="132.08" length="middle" direction="io" rot="R180"/>+ <pin name="PB11" x="17.78" y="129.54" length="middle" direction="io" rot="R180"/>+ <pin name="PE13" x="17.78" y="127" length="middle" direction="io" rot="R180"/>+ <pin name="PE15" x="17.78" y="124.46" length="middle" direction="io" rot="R180"/>+ <pin name="PE12" x="17.78" y="121.92" length="middle" direction="io" rot="R180"/>+ <pin name="PE10" x="17.78" y="119.38" length="middle" direction="io" rot="R180"/>+ <pin name="PE7" x="17.78" y="116.84" length="middle" direction="io" rot="R180"/>+ <pin name="PJ1" x="17.78" y="114.3" length="middle" direction="io" rot="R180"/>+ <pin name="PJ0" x="17.78" y="111.76" length="middle" direction="io" rot="R180"/>+ <pin name="PB0" x="17.78" y="109.22" length="middle" direction="io" rot="R180"/>+ <pin name="PB1" x="17.78" y="106.68" length="middle" direction="io" rot="R180"/>+ <pin name="PA7" x="17.78" y="104.14" length="middle" direction="io" rot="R180"/>+ <pin name="PA3" x="17.78" y="101.6" length="middle" direction="io" rot="R180"/>+ <pin name="VDDA" x="17.78" y="99.06" length="middle" direction="pwr" rot="R180"/>+ <pin name="PH10" x="17.78" y="96.52" length="middle" direction="io" rot="R180"/>+ <pin name="PH8" x="17.78" y="93.98" length="middle" direction="io" rot="R180"/>+ <pin name="PH6" x="17.78" y="91.44" length="middle" direction="io" rot="R180"/>+ <pin name="PB10" x="17.78" y="88.9" length="middle" direction="io" rot="R180"/>+ <pin name="PE14" x="17.78" y="86.36" length="middle" direction="io" rot="R180"/>+ <pin name="PE11" x="17.78" y="83.82" length="middle" direction="io" rot="R180"/>+ <pin name="PE9" x="17.78" y="81.28" length="middle" direction="io" rot="R180"/>+ <pin name="PF11" x="17.78" y="78.74" length="middle" direction="io" rot="R180"/>+ <pin name="PJ2" x="17.78" y="76.2" length="middle" direction="io" rot="R180"/>+ <pin name="PF14" x="17.78" y="73.66" length="middle" direction="io" rot="R180"/>+ <pin name="PC5" x="17.78" y="71.12" length="middle" direction="io" rot="R180"/>+ <pin name="PA5" x="17.78" y="68.58" length="middle" direction="io" rot="R180"/>+ <pin name="PA6" x="17.78" y="66.04" length="middle" direction="io" rot="R180"/>+ <pin name="PA2" x="17.78" y="63.5" length="middle" direction="io" rot="R180"/>+ <pin name="VREF+" x="17.78" y="60.96" length="middle" direction="pwr" rot="R180"/>+ <pin name="PH11" x="17.78" y="58.42" length="middle" direction="io" rot="R180"/>+ <pin name="PH9" x="17.78" y="55.88" length="middle" direction="io" rot="R180"/>+ <pin name="PH7" x="17.78" y="53.34" length="middle" direction="io" rot="R180"/>+ <pin name="PG4" x="17.78" y="50.8" length="middle" direction="io" rot="R180"/>+ <pin name="PG5" x="17.78" y="48.26" length="middle" direction="io" rot="R180"/>+ <pin name="PD11" x="17.78" y="45.72" length="middle" direction="io" rot="R180"/>+ <pin name="PE8" x="17.78" y="43.18" length="middle" direction="io" rot="R180"/>+ <pin name="PJ3" x="17.78" y="40.64" length="middle" direction="io" rot="R180"/>+ <pin name="PG0" x="17.78" y="38.1" length="middle" direction="io" rot="R180"/>+ <pin name="PF13" x="17.78" y="35.56" length="middle" direction="io" rot="R180"/>+ <pin name="PC4" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/>+ <pin name="PA4" x="17.78" y="30.48" length="middle" direction="io" rot="R180"/>+ <pin name="PA0/WKUP" x="17.78" y="27.94" length="middle" direction="io" rot="R180"/>+ <pin name="PA1" x="17.78" y="25.4" length="middle" direction="io" rot="R180"/>+ <pin name="VREF-" x="17.78" y="22.86" length="middle" direction="pwr" rot="R180"/>+ <pin name="PH12" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PJ5" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PG2" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PG3" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PD13" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PD12" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PJ4" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="PF15" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PG1" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="PF12" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PB2/BOOT1" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>+ <pin name="PC2" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PC1" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PC0" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="VSSA" x="17.78" y="-15.24" length="middle" direction="pwr" rot="R180"/>+ <pin name="PD8" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PD9" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PB12" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>+ <pin name="PD14" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>+ <pin name="VCAP_1" x="17.78" y="-27.94" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@11" x="17.78" y="-30.48" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@12" x="17.78" y="-33.02" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@13" x="17.78" y="-35.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@14" x="17.78" y="-38.1" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@10" x="17.78" y="-40.64" length="middle" direction="pwr" rot="R180"/>+ <pin name="BYPASS_REG" x="17.78" y="-43.18" length="middle" direction="in" rot="R180"/>+ <pin name="PC3" x="17.78" y="-45.72" length="middle" direction="io" rot="R180"/>+ <pin name="PF8" x="17.78" y="-48.26" length="middle" direction="io" rot="R180"/>+ <pin name="PF9" x="17.78" y="-50.8" length="middle" direction="io" rot="R180"/>+ <pin name="PF10" x="17.78" y="-53.34" length="middle" direction="io" rot="R180"/>+ <pin name="PD10" x="17.78" y="-55.88" length="middle" direction="io" rot="R180"/>+ <pin name="PB13" x="17.78" y="-58.42" length="middle" direction="io" rot="R180"/>+ <pin name="PD15" x="17.78" y="-60.96" length="middle" direction="io" rot="R180"/>+ <pin name="PJ6" x="17.78" y="-63.5" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@15" x="17.78" y="-66.04" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@11" x="17.78" y="-68.58" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@12" x="17.78" y="-71.12" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@13" x="17.78" y="-73.66" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@14" x="17.78" y="-76.2" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@15" x="17.78" y="-78.74" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@16" x="17.78" y="-81.28" length="middle" direction="pwr" rot="R180"/>+ <pin name="PH2" x="17.78" y="-83.82" length="middle" direction="io" rot="R180"/>+ <pin name="PF5" x="17.78" y="-86.36" length="middle" direction="io" rot="R180"/>+ <pin name="PF6" x="17.78" y="-88.9" length="middle" direction="io" rot="R180"/>+ <pin name="PF7" x="17.78" y="-91.44" length="middle" direction="io" rot="R180"/>+ <pin name="PG6" x="17.78" y="-93.98" length="middle" direction="io" rot="R180"/>+ <pin name="PG7" x="17.78" y="-96.52" length="middle" direction="io" rot="R180"/>+ <pin name="PJ9" x="17.78" y="-99.06" length="middle" direction="io" rot="R180"/>+ <pin name="PJ7" x="17.78" y="-101.6" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@17" x="17.78" y="-104.14" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@16" x="17.78" y="-106.68" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@17" x="17.78" y="-109.22" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@18" x="17.78" y="-111.76" length="middle" direction="pwr" rot="R180"/>+ <pin name="PH3" x="17.78" y="-114.3" length="middle" direction="io" rot="R180"/>+ <pin name="PH5" x="17.78" y="-116.84" length="middle" direction="io" rot="R180"/>+ <pin name="PF4" x="17.78" y="-119.38" length="middle" direction="io" rot="R180"/>+ <pin name="NRST" x="17.78" y="-121.92" length="middle" direction="in" rot="R180"/>+ <pin name="PC6" x="17.78" y="-124.46" length="middle" direction="io" rot="R180"/>+ <pin name="PG8" x="17.78" y="-127" length="middle" direction="io" rot="R180"/>+ <pin name="PJ10" x="17.78" y="-129.54" length="middle" direction="io" rot="R180"/>+ <pin name="PJ8" x="17.78" y="-132.08" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@19" x="17.78" y="-134.62" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@18" x="17.78" y="-137.16" length="middle" direction="pwr" rot="R180"/> </symbol> </symbols> <devicesets> <deviceset name="STM32F429NIH6" prefix="U">- <description></description>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), TFBGA-216. Pinout checked against ST's open pin data</description> <gates> <gate name="G$1" symbol="STM32F429NIH6" x="0" y="0"/> </gates>@@ -472,12 +527,65 @@ <connect gate="G$1" pin="PE4" pad="A1"/> <connect gate="G$1" pin="PE3" pad="A2"/> <connect gate="G$1" pin="PE2" pad="A3"/>+ <connect gate="G$1" pin="PG14" pad="A4"/>+ <connect gate="G$1" pin="PE1" pad="A5"/>+ <connect gate="G$1" pin="PE0" pad="A6"/>+ <connect gate="G$1" pin="PB8" pad="A7"/>+ <connect gate="G$1" pin="PB5" pad="A8"/>+ <connect gate="G$1" pin="PB4" pad="A9"/>+ <connect gate="G$1" pin="PB3" pad="A10"/>+ <connect gate="G$1" pin="PD7" pad="A11"/>+ <connect gate="G$1" pin="PC12" pad="A12"/>+ <connect gate="G$1" pin="PA15" pad="A13"/>+ <connect gate="G$1" pin="PA14" pad="A14"/>+ <connect gate="G$1" pin="PA13" pad="A15"/> <connect gate="G$1" pin="PE5" pad="B1"/> <connect gate="G$1" pin="PE6" pad="B2"/>+ <connect gate="G$1" pin="PG13" pad="B3"/>+ <connect gate="G$1" pin="PB9" pad="B4"/>+ <connect gate="G$1" pin="PB7" pad="B5"/>+ <connect gate="G$1" pin="PB6" pad="B6"/>+ <connect gate="G$1" pin="PG15" pad="B7"/>+ <connect gate="G$1" pin="PG11" pad="B8"/>+ <connect gate="G$1" pin="PJ13" pad="B9"/>+ <connect gate="G$1" pin="PJ12" pad="B10"/>+ <connect gate="G$1" pin="PD6" pad="B11"/>+ <connect gate="G$1" pin="PD0" pad="B12"/>+ <connect gate="G$1" pin="PC11" pad="B13"/>+ <connect gate="G$1" pin="PC10" pad="B14"/>+ <connect gate="G$1" pin="PA12" pad="B15"/> <connect gate="G$1" pin="VBAT" pad="C1"/> <connect gate="G$1" pin="PI8" pad="C2"/>+ <connect gate="G$1" pin="PI4" pad="C3"/>+ <connect gate="G$1" pin="PK7" pad="C4"/>+ <connect gate="G$1" pin="PK6" pad="C5"/>+ <connect gate="G$1" pin="PK5" pad="C6"/>+ <connect gate="G$1" pin="PG12" pad="C7"/>+ <connect gate="G$1" pin="PG10" pad="C8"/>+ <connect gate="G$1" pin="PJ14" pad="C9"/>+ <connect gate="G$1" pin="PD5" pad="C10"/>+ <connect gate="G$1" pin="PD3" pad="C11"/>+ <connect gate="G$1" pin="PD1" pad="C12"/>+ <connect gate="G$1" pin="PI3" pad="C13"/>+ <connect gate="G$1" pin="PI2" pad="C14"/>+ <connect gate="G$1" pin="PA11" pad="C15"/> <connect gate="G$1" pin="PC13" pad="D1"/>- <connect gate="G$1" pin="PC14" pad="E1"/>+ <connect gate="G$1" pin="PF0" pad="D2"/>+ <connect gate="G$1" pin="PI5" pad="D3"/>+ <connect gate="G$1" pin="PI7" pad="D4"/>+ <connect gate="G$1" pin="PI10" pad="D5"/>+ <connect gate="G$1" pin="PI6" pad="D6"/>+ <connect gate="G$1" pin="PK4" pad="D7"/>+ <connect gate="G$1" pin="PK3" pad="D8"/>+ <connect gate="G$1" pin="PG9" pad="D9"/>+ <connect gate="G$1" pin="PJ15" pad="D10"/>+ <connect gate="G$1" pin="PD4" pad="D11"/>+ <connect gate="G$1" pin="PD2" pad="D12"/>+ <connect gate="G$1" pin="PH15" pad="D13"/>+ <connect gate="G$1" pin="PI1" pad="D14"/>+ <connect gate="G$1" pin="PA10" pad="D15"/>+ <connect gate="G$1" pin="PC14/OSC32_IN" pad="E1"/>+ <connect gate="G$1" pin="PF1" pad="E2"/> <connect gate="G$1" pin="PI12" pad="E3"/> <connect gate="G$1" pin="PI9" pad="E4"/> <connect gate="G$1" pin="PDR_ON" pad="E5"/>@@ -491,65 +599,39 @@ <connect gate="G$1" pin="PH14" pad="E13"/> <connect gate="G$1" pin="PI0" pad="E14"/> <connect gate="G$1" pin="PA9" pad="E15"/>- <connect gate="G$1" pin="PC15" pad="F1"/>- <connect gate="G$1" pin="PI11" pad="F2"/>- <connect gate="G$1" pin="PI10" pad="F3"/>+ <connect gate="G$1" pin="PC15/OSC32_OUT" pad="F1"/>+ <connect gate="G$1" pin="VSS" pad="F2"/>+ <connect gate="G$1" pin="PI11" pad="F3"/> <connect gate="G$1" pin="VDD@5" pad="F4"/> <connect gate="G$1" pin="VDD@6" pad="F5"/>- <connect gate="G$1" pin="VSS" pad="F6"/>- <connect gate="G$1" pin="VSS@2" pad="F7"/>- <connect gate="G$1" pin="VSS@3" pad="F8"/>- <connect gate="G$1" pin="VSS@4" pad="F9"/>- <connect gate="G$1" pin="VSS@5" pad="F10"/>+ <connect gate="G$1" pin="VSS@2" pad="F6"/>+ <connect gate="G$1" pin="VSS@3" pad="F7"/>+ <connect gate="G$1" pin="VSS@4" pad="F8"/>+ <connect gate="G$1" pin="VSS@5" pad="F9"/>+ <connect gate="G$1" pin="VSS@6" pad="F10"/> <connect gate="G$1" pin="VDD@7" pad="F11"/> <connect gate="G$1" pin="PK1" pad="F12"/> <connect gate="G$1" pin="PK2" pad="F13"/> <connect gate="G$1" pin="PC9" pad="F14"/> <connect gate="G$1" pin="PA8" pad="F15"/>- <connect gate="G$1" pin="PH0" pad="G1"/>+ <connect gate="G$1" pin="PH0/OSC_IN" pad="G1"/> <connect gate="G$1" pin="PF2" pad="G2"/> <connect gate="G$1" pin="PI13" pad="G3"/> <connect gate="G$1" pin="PI15" pad="G4"/> <connect gate="G$1" pin="VDD@8" pad="G5"/>- <connect gate="G$1" pin="VSS@6" pad="G6"/>- <connect gate="G$1" pin="VSS@7" pad="G10"/>+ <connect gate="G$1" pin="VSS@7" pad="G6"/>+ <connect gate="G$1" pin="VSS@8" pad="G10"/> <connect gate="G$1" pin="VDD@9" pad="G11"/> <connect gate="G$1" pin="PJ11" pad="G12"/> <connect gate="G$1" pin="PK0" pad="G13"/> <connect gate="G$1" pin="PC8" pad="G14"/> <connect gate="G$1" pin="PC7" pad="G15"/>- <connect gate="G$1" pin="PH1" pad="H1"/>+ <connect gate="G$1" pin="PH1/OSC_OUT" pad="H1"/> <connect gate="G$1" pin="PF3" pad="H2"/> <connect gate="G$1" pin="PI14" pad="H3"/> <connect gate="G$1" pin="PH4" pad="H4"/> <connect gate="G$1" pin="VDD@10" pad="H5"/>- <connect gate="G$1" pin="VSS@8" pad="H6"/>- <connect gate="G$1" pin="VSS@9" pad="H10"/>- <connect gate="G$1" pin="VDD@11" pad="H11"/>- <connect gate="G$1" pin="PJ8" pad="H12"/>- <connect gate="G$1" pin="PJ10" pad="H13"/>- <connect gate="G$1" pin="PG8" pad="H14"/>- <connect gate="G$1" pin="PC6" pad="H15"/>- <connect gate="G$1" pin="NRST" pad="J1"/>- <connect gate="G$1" pin="PF4" pad="J2"/>- <connect gate="G$1" pin="PH5" pad="J3"/>- <connect gate="G$1" pin="PH3" pad="J4"/>- <connect gate="G$1" pin="VDD@12" pad="J5"/>- <connect gate="G$1" pin="VSS@10" pad="J6"/>- <connect gate="G$1" pin="VSS@11" pad="J10"/>- <connect gate="G$1" pin="VDD@13" pad="J11"/>- <connect gate="G$1" pin="PJ7" pad="J12"/>- <connect gate="G$1" pin="PJ9" pad="J13"/>- <connect gate="G$1" pin="PG7" pad="J14"/>- <connect gate="G$1" pin="PG6" pad="J15"/>- <connect gate="G$1" pin="PF7" pad="K1"/>- <connect gate="G$1" pin="PF6" pad="K2"/>- <connect gate="G$1" pin="PF5" pad="K3"/>- <connect gate="G$1" pin="PH2" pad="K4"/>- <connect gate="G$1" pin="VDD@14" pad="K5"/>- <connect gate="G$1" pin="VSS@12" pad="K6"/>- <connect gate="G$1" pin="VSS@13" pad="K7"/>- <connect gate="G$1" pin="VSS@14" pad="K8"/>+ <connect gate="G$1" pin="VSS@9" pad="H6"/> <connect gate="G$1" pin="PB15" pad="R15"/> <connect gate="G$1" pin="PB14" pad="R14"/> <connect gate="G$1" pin="PB11" pad="R13"/>@@ -585,26 +667,27 @@ <connect gate="G$1" pin="PH7" pad="N13"/> <connect gate="G$1" pin="PG4" pad="N12"/> <connect gate="G$1" pin="PG5" pad="N11"/>+ <connect gate="G$1" pin="PD11" pad="N10"/> <connect gate="G$1" pin="PE8" pad="N9"/> <connect gate="G$1" pin="PJ3" pad="N8"/> <connect gate="G$1" pin="PG0" pad="N7"/> <connect gate="G$1" pin="PF13" pad="N6"/> <connect gate="G$1" pin="PC4" pad="N5"/> <connect gate="G$1" pin="PA4" pad="N4"/>- <connect gate="G$1" pin="PA0" pad="N3"/>+ <connect gate="G$1" pin="PA0/WKUP" pad="N3"/> <connect gate="G$1" pin="PA1" pad="N2"/>- <connect gate="G$1" pin="VREF" pad="N1"/>+ <connect gate="G$1" pin="VREF-" pad="N1"/> <connect gate="G$1" pin="PH12" pad="M15"/> <connect gate="G$1" pin="PJ5" pad="M14"/> <connect gate="G$1" pin="PG2" pad="M13"/> <connect gate="G$1" pin="PG3" pad="M12"/>- <connect gate="G$1" pin="PD12" pad="M11"/>- <connect gate="G$1" pin="PD11" pad="M10"/>+ <connect gate="G$1" pin="PD13" pad="M11"/>+ <connect gate="G$1" pin="PD12" pad="M10"/> <connect gate="G$1" pin="PJ4" pad="M9"/> <connect gate="G$1" pin="PF15" pad="M8"/> <connect gate="G$1" pin="PG1" pad="M7"/> <connect gate="G$1" pin="PF12" pad="M6"/>- <connect gate="G$1" pin="PB2" pad="M5"/>+ <connect gate="G$1" pin="PB2/BOOT1" pad="M5"/> <connect gate="G$1" pin="PC2" pad="M4"/> <connect gate="G$1" pin="PC1" pad="M3"/> <connect gate="G$1" pin="PC0" pad="M2"/>@@ -614,11 +697,11 @@ <connect gate="G$1" pin="PB12" pad="L13"/> <connect gate="G$1" pin="PD14" pad="L12"/> <connect gate="G$1" pin="VCAP_1" pad="L11"/>- <connect gate="G$1" pin="VDD@15" pad="L10"/>- <connect gate="G$1" pin="VDD@16" pad="L9"/>- <connect gate="G$1" pin="VDD@17" pad="L8"/>- <connect gate="G$1" pin="VDD@18" pad="L7"/>- <connect gate="G$1" pin="VSS@15" pad="L6"/>+ <connect gate="G$1" pin="VDD@11" pad="L10"/>+ <connect gate="G$1" pin="VDD@12" pad="L9"/>+ <connect gate="G$1" pin="VDD@13" pad="L8"/>+ <connect gate="G$1" pin="VDD@14" pad="L7"/>+ <connect gate="G$1" pin="VSS@10" pad="L6"/> <connect gate="G$1" pin="BYPASS_REG" pad="L5"/> <connect gate="G$1" pin="PC3" pad="L4"/> <connect gate="G$1" pin="PF8" pad="L3"/>@@ -628,11 +711,47 @@ <connect gate="G$1" pin="PB13" pad="K14"/> <connect gate="G$1" pin="PD15" pad="K13"/> <connect gate="G$1" pin="PJ6" pad="K12"/>- <connect gate="G$1" pin="VDD@19" pad="K11"/>- <connect gate="G$1" pin="VSS@16" pad="K10"/>- <connect gate="G$1" pin="VSS@17" pad="K9"/>+ <connect gate="G$1" pin="VDD@15" pad="K11"/>+ <connect gate="G$1" pin="VSS@11" pad="K10"/>+ <connect gate="G$1" pin="VSS@12" pad="K9"/>+ <connect gate="G$1" pin="VSS@13" pad="K8"/>+ <connect gate="G$1" pin="VSS@14" pad="K7"/>+ <connect gate="G$1" pin="VSS@15" pad="K6"/>+ <connect gate="G$1" pin="VDD@16" pad="K5"/>+ <connect gate="G$1" pin="PH2" pad="K4"/>+ <connect gate="G$1" pin="PF5" pad="K3"/>+ <connect gate="G$1" pin="PF6" pad="K2"/>+ <connect gate="G$1" pin="PF7" pad="K1"/>+ <connect gate="G$1" pin="PG6" pad="J15"/>+ <connect gate="G$1" pin="PG7" pad="J14"/>+ <connect gate="G$1" pin="PJ9" pad="J13"/>+ <connect gate="G$1" pin="PJ7" pad="J12"/>+ <connect gate="G$1" pin="VDD@17" pad="J11"/>+ <connect gate="G$1" pin="VSS@16" pad="J10"/>+ <connect gate="G$1" pin="VSS@17" pad="J6"/>+ <connect gate="G$1" pin="VDD@18" pad="J5"/>+ <connect gate="G$1" pin="PH3" pad="J4"/>+ <connect gate="G$1" pin="PH5" pad="J3"/>+ <connect gate="G$1" pin="PF4" pad="J2"/>+ <connect gate="G$1" pin="NRST" pad="J1"/>+ <connect gate="G$1" pin="PC6" pad="H15"/>+ <connect gate="G$1" pin="PG8" pad="H14"/>+ <connect gate="G$1" pin="PJ10" pad="H13"/>+ <connect gate="G$1" pin="PJ8" pad="H12"/>+ <connect gate="G$1" pin="VDD@19" pad="H11"/>+ <connect gate="G$1" pin="VSS@18" pad="H10"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="STM32F429NIH6" constant="no"/>+ <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588950074281349120" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32f429nih6" constant="no"/>+ <attribute name="MOUSER_PN" value="511-STM32F429NIH6" constant="no"/>+ <attribute name="DIGIKEY_PN" value="497-17457-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C710318" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>