component
STM32F427VIT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
5 files changed
+503−492
README.md+99−99@@ -8,106 +8,106 @@ STM32F427VIT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin desc | Pin | Name | Type | Function | |---|---|---|---|-| 1 | PE2 | output | Port E pin 2; alternate functions: TRACECLK, SPI4_SCK, SAI1_MCLK_A, FMC_A23 |-| 2 | PE3 | output | Port E pin 3; alternate functions: TRACED0, SAI1_SD_B, FMC_A19 |-| 3 | PE4 | output | Port E pin 4; alternate functions: TRACED1, SPI4_NSS, SAI1_FS_A, DCMI_D4, LCD_B0 |-| 4 | PE5 | output | Port E pin 5; alternate functions: TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, DCMI_D6, LCD_G0 |-| 5 | PE6 | output | Port E pin 6; alternate functions: TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, DCMI_D7, LCD_G1 |+| 1 | PE2 | bidirectional | Port E pin 2; alternate functions: TRACECLK, SPI4_SCK, SAI1_MCLK_A, FMC_A23 |+| 2 | PE3 | bidirectional | Port E pin 3; alternate functions: TRACED0, SAI1_SD_B, FMC_A19 |+| 3 | PE4 | bidirectional | Port E pin 4; alternate functions: TRACED1, SPI4_NSS, SAI1_FS_A, DCMI_D4, LCD_B0 |+| 4 | PE5 | bidirectional | Port E pin 5; alternate functions: TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, DCMI_D6, LCD_G0 |+| 5 | PE6 | bidirectional | Port E pin 6; alternate functions: TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, DCMI_D7, LCD_G1 | | 6 | VBAT | power_in | Backup power supply (1.65 V to 3.6 V) |-| 7 | PC13 | output | Port C pin 13; backup domain pin, can be used as tamper input TAMP_1 |-| 8 | PC14-OSC32_IN | input | Port C pin 14 / 32 kHz oscillator input (OSC32_IN) |-| 9 | PC15-OSC32_OUT | output | Port C pin 15 / 32 kHz oscillator output (OSC32_OUT) |-| 10 | PF0 | output | Port F pin 0; alternate functions: I2C2_SDA, FMC_A0 |-| 11 | PF1 | output | Port F pin 1; alternate functions: I2C2_SCL, FMC_A1 |-| 12 | PF2 | output | Port F pin 2; alternate functions: I2C2_SMBA, FMC_A2 |-| 13 | PF3 | output | Port F pin 3; alternate functions: FMC_A3, ADC3_IN9 |-| 14 | PF4 | output | Port F pin 4; alternate functions: FMC_A4, ADC3_IN14 |-| 15 | PF5 | output | Port F pin 5; alternate functions: FMC_A5, ADC3_IN15 |-| 16 | PH0-OSC_IN | input | Port H pin 0 / High-speed oscillator input (OSC_IN) |-| 17 | PH1-OSC_OUT | output | Port H pin 1 / High-speed oscillator output (OSC_OUT) |-| 18 | NRST | input | Active-low asynchronous reset with internal pull-up |-| 19 | PC0 | output | Port C pin 0; alternate functions: OTG_HS_ULPI_STP, FMC_SDNWE, ADC123_IN10 |-| 20 | PC1 | output | Port C pin 1; alternate functions: ETH_MDC, ADC123_IN11 |-| 21 | PC2 | output | Port C pin 2; alternate functions: SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, ADC123_IN12 |-| 22 | PC3 | output | Port C pin 3; alternate functions: SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, ADC123_IN13 |-| 23 | PC4 | output | Port C pin 4; alternate functions: ETH_MII_RXD0/ETH_RMII_RXD0, ADC12_IN14 |-| 24 | PC5 | output | Port C pin 5; alternate functions: ETH_MII_RXD1/ETH_RMII_RXD1, ADC12_IN15 |-| 25 | PB0 | output | Port B pin 0; alternate functions: TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, ADC12_IN8 |-| 26 | PB1 | output | Port B pin 1; alternate functions: TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, ADC12_IN9 |-| 27 | PB2-BOOT1 | output | Port B pin 2 / Boot configuration pin 1 |-| 28 | PE7 | output | Port E pin 7; alternate functions: TIM1_ETR, UART7_Rx, FMC_D4 |-| 29 | PE8 | output | Port E pin 8; alternate functions: TIM1_CH1N, UART7_Tx, FMC_D5 |-| 30 | PE9 | output | Port E pin 9; alternate functions: TIM1_CH1, FMC_D6 |-| 31 | PE10 | output | Port E pin 10; alternate functions: TIM1_CH2N, FMC_D7 |-| 32 | PE11 | output | Port E pin 11; alternate functions: TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3 |-| 33 | PE12 | output | Port E pin 12; alternate functions: TIM1_CH3N, SPI4_SCK, FMC_D9, LCD_B4 |-| 34 | PE13 | output | Port E pin 13; alternate functions: TIM1_CH3, SPI4_MISO, FMC_D10, LCD_DE |-| 35 | PE14 | output | Port E pin 14; alternate functions: TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK |-| 36 | PE15 | output | Port E pin 15; alternate functions: TIM1_BKIN, FMC_D12, LCD_R7 |-| 37 | PB10 | output | Port B pin 10; alternate functions: TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4 |-| 38 | PB11 | output | Port B pin 11; alternate functions: TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_TX_EN, LCD_G5 |-| 39 | VCAP_1 | power_in | Capacitor connection point for 1.2 V internal voltage regulator (2.2 µF external capacitor required) |-| 40 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |-| 41 | PB12 | output | Port B pin 12; alternate functions: TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OTG_HS_ID |-| 42 | PB13 | output | Port B pin 13; alternate functions: TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, OTG_HS_VBUS |-| 43 | PB14 | output | Port B pin 14; alternate functions: TIM1_CH2N, TIM8_CH2N, SPI2_MISO, I2S2ext_SD, USART3_RTS, TIM12_CH1, OTG_HS_DM |-| 44 | PB15 | output | Port B pin 15; alternate functions: RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP |-| 45 | PD8 | output | Port D pin 8; alternate functions: USART3_TX, FMC_D13 |-| 46 | PD9 | output | Port D pin 9; alternate functions: USART3_RX, FMC_D14 |-| 47 | PD10 | output | Port D pin 10; alternate functions: USART3_CK, FMC_D15, LCD_B3 |-| 48 | PD11 | output | Port D pin 11; alternate functions: USART3_CTS, FMC_A16 |-| 49 | PD12 | output | Port D pin 12; alternate functions: TIM4_CH1, USART3_RTS, FMC_A17 |-| 50 | PD13 | output | Port D pin 13; alternate functions: TIM4_CH2, FMC_A18 |-| 51 | PD14 | output | Port D pin 14; alternate functions: TIM4_CH3, FMC_D0 |-| 52 | PD15 | output | Port D pin 15; alternate functions: TIM4_CH4, FMC_D1 |-| 53 | PC6 | output | Port C pin 6; alternate functions: TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, LCD_HSYNC |-| 54 | PC7 | output | Port C pin 7; alternate functions: TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDIO_D7, DCMI_D1, LCD_G6 |-| 55 | PC8 | output | Port C pin 8; alternate functions: TIM3_CH3, TIM8_CH3, USART6_CK, SDIO_D0, DCMI_D2 |-| 56 | PC9 | output | Port C pin 9; alternate functions: MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, SDIO_D1, DCMI_D3 |-| 57 | PA8 | output | Port A pin 8; alternate functions: MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, LCD_R6 |-| 58 | PA9 | output | Port A pin 9; alternate functions: TIM1_CH2, I2C3_SMBA, USART1_TX, DCMI_D0, OTG_FS_VBUS |-| 59 | PA10 | output | Port A pin 10; alternate functions: TIM1_CH3, USART1_RX, OTG_FS_ID, DCMI_D1 |-| 60 | PA11 | output | Port A pin 11; alternate functions: TIM1_CH4, USART1_CTS, CAN1_RX, LCD_R4, OTG_FS_DM |-| 61 | PA12 | output | Port A pin 12; alternate functions: TIM1_ETR, USART1_RTS, CAN1_TX, LCD_R5, OTG_FS_DP |-| 62 | PA13 (JTMS-SWDIO) | output | Port A pin 13 / JTAG Test Mode Select / Serial Wire Debug I/O |-| 63 | VCAP_2 | power_in | Capacitor connection point for 1.2 V internal voltage regulator (2.2 µF external capacitor required) |-| 64 | VSS | power_in | Ground (negative power supply) |-| 65 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |-| 66 | PA14 (JTCK-SWCLK) | output | Port A pin 14 / JTAG Test Clock / Serial Wire Debug Clock |-| 67 | PA15 (JTDI) | output | Port A pin 15 / JTAG Test Data Input; alternate functions: TIM2_CH1/TIM2_ETR, SPI1_NSS, SPI3_NSS/I2S3_WS |-| 68 | PC10 | output | Port C pin 10; alternate functions: SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, SDIO_D2, DCMI_D8, LCD_R2 |-| 69 | PC11 | output | Port C pin 11; alternate functions: I2S3ext_SD, SPI3_MISO, USART3_RX, UART4_RX, SDIO_D3, DCMI_D4 |-| 70 | PC12 | output | Port C pin 12; alternate functions: SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9 |-| 71 | PD0 | output | Port D pin 0; alternate functions: CAN1_RX, FMC_D2 |-| 72 | PD1 | output | Port D pin 1; alternate functions: CAN1_TX, FMC_D3 |-| 73 | PD2 | output | Port D pin 2; alternate functions: TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11 |-| 74 | PD3 | output | Port D pin 3; alternate functions: SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, DCMI_D5, LCD_G7 |-| 75 | PD4 | output | Port D pin 4; alternate functions: USART2_RTS, FMC_NOE |-| 76 | PD5 | output | Port D pin 5; alternate functions: USART2_TX, FMC_NWE |-| 77 | PD6 | output | Port D pin 6; alternate functions: SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, FMC_NWAIT, DCMI_D10, LCD_B2 |-| 78 | PD7 | output | Port D pin 7; alternate functions: USART2_CK, FMC_NE1/FMC_NCE2 |-| 79 | PG11 | output | Port G pin 11; alternate functions: ETH_MII_TX_EN/ETH_RMII_TX_EN, FMC_NCE4_2, DCMI_D3, LCD_B3 |-| 80 | PG12 | output | Port G pin 12; alternate functions: SPI6_MISO, USART6_RTS, LCD_B4, FMC_NE4, LCD_B1 |-| 81 | PG13 | output | Port G pin 13; alternate functions: SPI6_SCK, USART6_CTS, ETH_MII_TXD0/ETH_RMII_TXD0, FMC_A24 |-| 82 | PG14 | output | Port G pin 14; alternate functions: SPI6_MOSI, USART6_TX, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_A25 |-| 83 | PG15 | output | Port G pin 15; alternate functions: USART6_CTS, FMC_SDNCAS, DCMI_D13 |-| 84 | PH13 | output | Port H pin 13; alternate functions: TIM8_CH1N, CAN1_TX, FMC_D21, LCD_G2 |-| 85 | PH14 | output | Port H pin 14; alternate functions: TIM8_CH2N, FMC_D22, DCMI_D4, LCD_G3 |-| 86 | PH15 | output | Port H pin 15; alternate functions: TIM8_CH3N, FMC_D23, DCMI_D11, LCD_G4 |-| 87 | PI0 | output | Port I pin 0; alternate functions: TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, DCMI_D13, LCD_G5 |-| 88 | PI1 | output | Port I pin 1; alternate functions: SPI2_SCK/I2S2_CK, FMC_D25, DCMI_D8, LCD_G6 |-| 89 | PI2 | output | Port I pin 2; alternate functions: TIM8_CH4, SPI2_MISO, I2S2ext_SD, FMC_D26, DCMI_D9, LCD_G7 |-| 90 | PI3 | output | Port I pin 3; alternate functions: TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, DCMI_D10 |-| 91 | VSS | power_in | Ground (negative power supply) |-| 92 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |-| 93 | PB3 (JTDO/TRACESWO) | output | Port B pin 3 / JTAG Test Data Output / Trace Serial Wire Output; alternate functions: TIM2_CH2, SPI1_SCK, SPI3_SCK/I2S3_CK |-| 94 | PB4 (NJTRST) | output | Port B pin 4 / JTAG NTRST pin; alternate functions: TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD |-| 95 | PB5 | output | Port B pin 5; alternate functions: TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10 |-| 96 | BOOT0 | input | Boot configuration pin 0 for selecting boot mode at reset |-| 97 | PB8 | output | Port B pin 8; alternate functions: TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, ETH_MII_TXD3, SDIO_D4, DCMI_D6, LCD_B6 |-| 98 | PB9 | output | Port B pin 9; alternate functions: TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDIO_D5, DCMI_D7, LCD_B7 |-| 99 | PE0 | output | Port E pin 0; alternate functions: TIM4_ETR, UART8_RX, FMC_NBL0, DCMI_D2 |-| 100 | PE1 | output | Port E pin 1; alternate functions: UART8_Tx, FMC_NBL1, DCMI_D3 |+| 7 | PC13 | bidirectional | Port C pin 13; backup domain pin, can be used as tamper input TAMP_1 |+| 8 | PC14/OSC32_IN | bidirectional | Port C pin 14 / 32 kHz oscillator input (OSC32_IN) |+| 9 | PC15/OSC32_OUT | bidirectional | Port C pin 15 / 32 kHz oscillator output (OSC32_OUT) |+| 10 | VSS | power_in | Ground (negative power supply) |+| 11 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |+| 12 | PH0/OSC_IN | bidirectional | Port H pin 0 / High-speed oscillator input (OSC_IN) |+| 13 | PH1/OSC_OUT | bidirectional | Port H pin 1 / High-speed oscillator output (OSC_OUT) |+| 14 | NRST | input | Active-low asynchronous reset with internal pull-up |+| 15 | PC0 | bidirectional | Port C pin 0; alternate functions: OTG_HS_ULPI_STP, FMC_SDNWE, ADC123_IN10 |+| 16 | PC1 | bidirectional | Port C pin 1; alternate functions: ETH_MDC, ADC123_IN11 |+| 17 | PC2 | bidirectional | Port C pin 2; alternate functions: SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, ADC123_IN12 |+| 18 | PC3 | bidirectional | Port C pin 3; alternate functions: SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, ADC123_IN13 |+| 19 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |+| 20 | VSSA | power_in | |+| 21 | VREF+ | power_in | |+| 22 | VDDA | power_in | |+| 23 | PA0/WKUP | bidirectional | |+| 24 | PA1 | bidirectional | |+| 25 | PA2 | bidirectional | |+| 26 | PA3 | bidirectional | |+| 27 | VSS | power_in | Ground (negative power supply) |+| 28 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |+| 29 | PA4 | bidirectional | |+| 30 | PA5 | bidirectional | |+| 31 | PA6 | bidirectional | |+| 32 | PA7 | bidirectional | |+| 33 | PC4 | bidirectional | Port C pin 4; alternate functions: ETH_MII_RXD0/ETH_RMII_RXD0, ADC12_IN14 |+| 34 | PC5 | bidirectional | Port C pin 5; alternate functions: ETH_MII_RXD1/ETH_RMII_RXD1, ADC12_IN15 |+| 35 | PB0 | bidirectional | Port B pin 0; alternate functions: TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, ADC12_IN8 |+| 36 | PB1 | bidirectional | Port B pin 1; alternate functions: TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, ADC12_IN9 |+| 37 | PB2/BOOT1 | bidirectional | Port B pin 2 / Boot configuration pin 1 |+| 38 | PE7 | bidirectional | Port E pin 7; alternate functions: TIM1_ETR, UART7_Rx, FMC_D4 |+| 39 | PE8 | bidirectional | Port E pin 8; alternate functions: TIM1_CH1N, UART7_Tx, FMC_D5 |+| 40 | PE9 | bidirectional | Port E pin 9; alternate functions: TIM1_CH1, FMC_D6 |+| 41 | PE10 | bidirectional | Port E pin 10; alternate functions: TIM1_CH2N, FMC_D7 |+| 42 | PE11 | bidirectional | Port E pin 11; alternate functions: TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3 |+| 43 | PE12 | bidirectional | Port E pin 12; alternate functions: TIM1_CH3N, SPI4_SCK, FMC_D9, LCD_B4 |+| 44 | PE13 | bidirectional | Port E pin 13; alternate functions: TIM1_CH3, SPI4_MISO, FMC_D10, LCD_DE |+| 45 | PE14 | bidirectional | Port E pin 14; alternate functions: TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK |+| 46 | PE15 | bidirectional | Port E pin 15; alternate functions: TIM1_BKIN, FMC_D12, LCD_R7 |+| 47 | PB10 | bidirectional | Port B pin 10; alternate functions: TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4 |+| 48 | PB11 | bidirectional | Port B pin 11; alternate functions: TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_RMII_TX_EN, LCD_G5 |+| 49 | VCAP_1 | power_in | Capacitor connection point for 1.2 V internal voltage regulator (2.2 µF external capacitor required) |+| 50 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |+| 51 | PB12 | bidirectional | Port B pin 12; alternate functions: TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RMII_TXD0, OTG_HS_ID |+| 52 | PB13 | bidirectional | Port B pin 13; alternate functions: TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RMII_TXD1, OTG_HS_VBUS |+| 53 | PB14 | bidirectional | Port B pin 14; alternate functions: TIM1_CH2N, TIM8_CH2N, SPI2_MISO, I2S2ext_SD, USART3_RTS, TIM12_CH1, OTG_HS_DM |+| 54 | PB15 | bidirectional | Port B pin 15; alternate functions: RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP |+| 55 | PD8 | bidirectional | Port D pin 8; alternate functions: USART3_TX, FMC_D13 |+| 56 | PD9 | bidirectional | Port D pin 9; alternate functions: USART3_RX, FMC_D14 |+| 57 | PD10 | bidirectional | Port D pin 10; alternate functions: USART3_CK, FMC_D15, LCD_B3 |+| 58 | PD11 | bidirectional | Port D pin 11; alternate functions: USART3_CTS, FMC_A16 |+| 59 | PD12 | bidirectional | Port D pin 12; alternate functions: TIM4_CH1, USART3_RTS, FMC_A17 |+| 60 | PD13 | bidirectional | Port D pin 13; alternate functions: TIM4_CH2, FMC_A18 |+| 61 | PD14 | bidirectional | Port D pin 14; alternate functions: TIM4_CH3, FMC_D0 |+| 62 | PD15 | bidirectional | Port D pin 15; alternate functions: TIM4_CH4, FMC_D1 |+| 63 | PC6 | bidirectional | Port C pin 6; alternate functions: TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, LCD_HSYNC |+| 64 | PC7 | bidirectional | Port C pin 7; alternate functions: TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDIO_D7, DCMI_D1, LCD_G6 |+| 65 | PC8 | bidirectional | Port C pin 8; alternate functions: TIM3_CH3, TIM8_CH3, USART6_CK, SDIO_D0, DCMI_D2 |+| 66 | PC9 | bidirectional | Port C pin 9; alternate functions: MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, SDIO_D1, DCMI_D3 |+| 67 | PA8 | bidirectional | Port A pin 8; alternate functions: MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, LCD_R6 |+| 68 | PA9 | bidirectional | Port A pin 9; alternate functions: TIM1_CH2, I2C3_SMBA, USART1_TX, DCMI_D0, OTG_FS_VBUS |+| 69 | PA10 | bidirectional | Port A pin 10; alternate functions: TIM1_CH3, USART1_RX, OTG_FS_ID, DCMI_D1 |+| 70 | PA11 | bidirectional | Port A pin 11; alternate functions: TIM1_CH4, USART1_CTS, CAN1_RX, LCD_R4, OTG_FS_DM |+| 71 | PA12 | bidirectional | Port A pin 12; alternate functions: TIM1_ETR, USART1_RTS, CAN1_TX, LCD_R5, OTG_FS_DP |+| 72 | PA13 | bidirectional | |+| 73 | VCAP_2 | power_in | Capacitor connection point for 1.2 V internal voltage regulator (2.2 µF external capacitor required) |+| 74 | VSS | power_in | Ground (negative power supply) |+| 75 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic |+| 76 | PA14 | bidirectional | |+| 77 | PA15 | bidirectional | |+| 78 | PC10 | bidirectional | Port C pin 10; alternate functions: SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, SDIO_D2, DCMI_D8, LCD_R2 |+| 79 | PC11 | bidirectional | Port C pin 11; alternate functions: I2S3ext_SD, SPI3_MISO, USART3_RX, UART4_RX, SDIO_D3, DCMI_D4 |+| 80 | PC12 | bidirectional | Port C pin 12; alternate functions: SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9 |+| 81 | PD0 | bidirectional | Port D pin 0; alternate functions: CAN1_RX, FMC_D2 |+| 82 | PD1 | bidirectional | Port D pin 1; alternate functions: CAN1_TX, FMC_D3 |+| 83 | PD2 | bidirectional | Port D pin 2; alternate functions: TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11 |+| 84 | PD3 | bidirectional | Port D pin 3; alternate functions: SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, DCMI_D5, LCD_G7 |+| 85 | PD4 | bidirectional | Port D pin 4; alternate functions: USART2_RTS, FMC_NOE |+| 86 | PD5 | bidirectional | Port D pin 5; alternate functions: USART2_TX, FMC_NWE |+| 87 | PD6 | bidirectional | Port D pin 6; alternate functions: SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, FMC_NWAIT, DCMI_D10, LCD_B2 |+| 88 | PD7 | bidirectional | Port D pin 7; alternate functions: USART2_CK, FMC_NE1/FMC_NCE2 |+| 89 | PB3 | bidirectional | |+| 90 | PB4 | bidirectional | |+| 91 | PB5 | bidirectional | Port B pin 5; alternate functions: TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10 |+| 92 | PB6 | bidirectional | |+| 93 | PB7 | bidirectional | |+| 94 | BOOT0 | input | Boot configuration pin 0 for selecting boot mode at reset |+| 95 | PB8 | bidirectional | Port B pin 8; alternate functions: TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, ETH_MII_TXD3, SDIO_D4, DCMI_D6, LCD_B6 |+| 96 | PB9 | bidirectional | Port B pin 9; alternate functions: TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDIO_D5, DCMI_D7, LCD_B7 |+| 97 | PE0 | bidirectional | Port E pin 0; alternate functions: TIM4_ETR, UART8_RX, FMC_NBL0, DCMI_D2 |+| 98 | PE1 | bidirectional | Port E pin 1; alternate functions: UART8_Tx, FMC_NBL1, DCMI_D3 |+| 99 | VSS | power_in | Ground (negative power supply) |+| 100 | VDD | power_in | Main positive power supply (1.7 V to 3.6 V), I/O and internal logic | ## Key specifications
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direction="out" rot="R180"/>- <pin name="PA10" x="17.78" y="-43.18" length="middle" direction="out" rot="R180"/>- <pin name="PA9" x="17.78" y="-45.72" length="middle" direction="out" rot="R180"/>- <pin name="PA8" x="17.78" y="-48.26" length="middle" direction="out" rot="R180"/>- <pin name="PC9" x="17.78" y="-50.8" length="middle" direction="out" rot="R180"/>- <pin name="PC8" x="17.78" y="-53.34" length="middle" direction="out" rot="R180"/>- <pin name="PC7" x="17.78" y="-55.88" length="middle" direction="out" rot="R180"/>- <pin name="PC6" x="17.78" y="-58.42" length="middle" direction="out" rot="R180"/>- <pin name="PD15" x="17.78" y="-60.96" length="middle" direction="out" rot="R180"/>- <pin name="PD14" x="17.78" y="-63.5" length="middle" direction="out" rot="R180"/>+ <pin name="PC13" x="-17.78" y="45.72" length="middle" direction="io"/>+ <pin name="PC14/OSC32_IN" x="-17.78" y="43.18" length="middle" direction="io"/>+ <pin name="PC15/OSC32_OUT" x="-17.78" y="40.64" length="middle" direction="io"/>+ <pin name="VSS" x="-17.78" y="38.1" length="middle" direction="pwr"/>+ <pin name="VDD" x="-17.78" y="35.56" length="middle" direction="pwr"/>+ <pin name="PH0/OSC_IN" x="-17.78" y="33.02" length="middle" direction="io"/>+ <pin name="PH1/OSC_OUT" x="-17.78" y="30.48" length="middle" direction="io"/>+ <pin name="NRST" x="-17.78" y="27.94" length="middle" direction="in"/>+ <pin name="PC0" x="-17.78" y="25.4" length="middle" direction="io"/>+ <pin name="PC1" x="-17.78" y="22.86" length="middle" direction="io"/>+ <pin name="PC2" x="-17.78" y="20.32" length="middle" direction="io"/>+ <pin name="PC3" x="-17.78" y="17.78" length="middle" direction="io"/>+ <pin name="VDD@2" x="-17.78" y="15.24" length="middle" direction="pwr"/>+ <pin name="VSSA" x="-17.78" y="12.7" length="middle" direction="pwr"/>+ <pin name="VREF+" x="-17.78" y="10.16" length="middle" direction="pwr"/>+ <pin name="VDDA" x="-17.78" y="7.62" length="middle" direction="pwr"/>+ <pin name="PA0/WKUP" x="-17.78" y="5.08" length="middle" direction="io"/>+ <pin name="PA1" x="-17.78" y="2.54" length="middle" direction="io"/>+ <pin name="PA2" x="-17.78" y="0" length="middle" direction="io"/>+ <pin name="PA3" x="-17.78" y="-2.54" length="middle" direction="io"/>+ <pin name="VSS@2" x="-17.78" y="-5.08" length="middle" direction="pwr"/>+ <pin name="VDD@3" x="-17.78" y="-7.62" length="middle" direction="pwr"/>+ <pin name="PA4" x="-17.78" y="-10.16" length="middle" direction="io"/>+ <pin name="PA5" x="-17.78" y="-12.7" length="middle" direction="io"/>+ <pin name="PA6" x="-17.78" y="-15.24" length="middle" direction="io"/>+ <pin name="PA7" x="-17.78" y="-17.78" length="middle" direction="io"/>+ <pin name="PC4" x="-17.78" y="-20.32" length="middle" direction="io"/>+ <pin name="PC5" x="-17.78" y="-22.86" length="middle" direction="io"/>+ <pin name="PB0" x="-17.78" y="-25.4" length="middle" direction="io"/>+ <pin name="PB1" x="-17.78" y="-27.94" length="middle" direction="io"/>+ <pin name="PB2/BOOT1" x="-17.78" y="-30.48" length="middle" direction="io"/>+ <pin name="PE7" x="-17.78" y="-33.02" length="middle" direction="io"/>+ <pin name="PE8" x="-17.78" y="-35.56" length="middle" direction="io"/>+ <pin name="PE9" x="-17.78" y="-38.1" length="middle" direction="io"/>+ <pin name="PE10" x="-17.78" y="-40.64" length="middle" direction="io"/>+ <pin name="PE11" x="-17.78" y="-43.18" length="middle" direction="io"/>+ <pin name="PE12" x="-17.78" y="-45.72" length="middle" direction="io"/>+ <pin name="PE13" x="-17.78" y="-48.26" length="middle" direction="io"/>+ <pin name="PE14" x="-17.78" y="-50.8" length="middle" direction="io"/>+ <pin name="PE15" x="-17.78" y="-53.34" length="middle" direction="io"/>+ <pin name="PB10" x="-17.78" y="-55.88" length="middle" direction="io"/>+ <pin name="PB11" x="-17.78" y="-58.42" length="middle" direction="io"/>+ <pin name="VCAP_1" x="-17.78" y="-60.96" length="middle" direction="pwr"/>+ <pin name="VDD@4" x="-17.78" y="-63.5" length="middle" direction="pwr"/>+ <pin name="VDD@5" x="17.78" y="60.96" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@3" x="17.78" y="58.42" length="middle" direction="pwr" rot="R180"/>+ <pin name="PE1" x="17.78" y="55.88" length="middle" direction="io" rot="R180"/>+ <pin name="PE0" x="17.78" y="53.34" length="middle" direction="io" rot="R180"/>+ <pin name="PB9" x="17.78" y="50.8" length="middle" direction="io" rot="R180"/>+ <pin name="PB8" x="17.78" y="48.26" length="middle" direction="io" rot="R180"/>+ <pin name="BOOT0" x="17.78" y="45.72" length="middle" direction="in" rot="R180"/>+ <pin name="PB7" x="17.78" y="43.18" length="middle" direction="io" rot="R180"/>+ <pin name="PB6" x="17.78" y="40.64" length="middle" direction="io" rot="R180"/>+ <pin name="PB5" x="17.78" y="38.1" length="middle" direction="io" rot="R180"/>+ <pin name="PB4" x="17.78" y="35.56" length="middle" direction="io" rot="R180"/>+ <pin name="PB3" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/>+ <pin name="PD7" x="17.78" y="30.48" length="middle" direction="io" rot="R180"/>+ <pin name="PD6" x="17.78" y="27.94" length="middle" direction="io" rot="R180"/>+ <pin name="PD5" x="17.78" y="25.4" length="middle" direction="io" rot="R180"/>+ <pin name="PD4" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>+ <pin name="PD3" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PD2" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PD1" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PD0" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PC12" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PC11" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PC10" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="PA15" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PA14" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@6" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@4" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/>+ <pin name="VCAP_2" x="17.78" y="-7.62" length="middle" direction="pwr" rot="R180"/>+ <pin name="PA13" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PA12" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PA11" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PA10" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PA9" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PA8" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>+ <pin name="PC9" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>+ <pin name="PC8" x="17.78" y="-27.94" length="middle" direction="io" rot="R180"/>+ <pin name="PC7" x="17.78" y="-30.48" length="middle" direction="io" rot="R180"/>+ <pin name="PC6" x="17.78" y="-33.02" length="middle" direction="io" rot="R180"/>+ <pin name="PD15" x="17.78" y="-35.56" length="middle" direction="io" rot="R180"/>+ <pin name="PD14" x="17.78" y="-38.1" length="middle" direction="io" rot="R180"/>+ <pin name="PD13" x="17.78" y="-40.64" length="middle" direction="io" rot="R180"/>+ <pin name="PD12" x="17.78" y="-43.18" length="middle" direction="io" rot="R180"/>+ <pin name="PD11" x="17.78" y="-45.72" length="middle" direction="io" rot="R180"/>+ <pin name="PD10" x="17.78" y="-48.26" length="middle" direction="io" rot="R180"/>+ <pin name="PD9" x="17.78" y="-50.8" length="middle" direction="io" rot="R180"/>+ <pin name="PD8" x="17.78" y="-53.34" length="middle" direction="io" rot="R180"/>+ <pin name="PB15" x="17.78" y="-55.88" length="middle" direction="io" rot="R180"/>+ <pin name="PB14" x="17.78" y="-58.42" length="middle" direction="io" rot="R180"/>+ <pin name="PB13" x="17.78" y="-60.96" length="middle" direction="io" rot="R180"/>+ <pin name="PB12" x="17.78" y="-63.5" length="middle" direction="io" rot="R180"/> </symbol> </symbols> <devicesets> <deviceset name="STM32F427VIT6" prefix="U">- <description></description>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data</description> <gates> <gate name="G$1" symbol="STM32F427VIT6" x="0" y="0"/> </gates>@@ -304,101 +305,111 @@ <connect gate="G$1" pin="PE6" pad="5"/> <connect gate="G$1" pin="VBAT" pad="6"/> <connect gate="G$1" pin="PC13" pad="7"/>- <connect gate="G$1" pin="PC14-OSC32_IN" pad="8"/>- <connect gate="G$1" pin="PC15-OSC32_OUT" pad="9"/>- <connect gate="G$1" pin="PF0" pad="10"/>- <connect gate="G$1" pin="PF1" pad="11"/>- <connect gate="G$1" pin="PF2" pad="12"/>- <connect gate="G$1" pin="PF3" pad="13"/>- <connect gate="G$1" pin="PF4" pad="14"/>- <connect gate="G$1" pin="PF5" pad="15"/>- <connect gate="G$1" pin="PH0-OSC_IN" pad="16"/>- <connect gate="G$1" pin="PH1-OSC_OUT" pad="17"/>- <connect gate="G$1" pin="NRST" pad="18"/>- <connect gate="G$1" pin="PC0" pad="19"/>- <connect gate="G$1" pin="PC1" pad="20"/>- <connect gate="G$1" pin="PC2" pad="21"/>- <connect gate="G$1" pin="PC3" pad="22"/>- <connect gate="G$1" pin="PC4" pad="23"/>- <connect gate="G$1" pin="PC5" pad="24"/>- <connect gate="G$1" pin="PB0" pad="25"/>- <connect gate="G$1" pin="PB1" pad="26"/>- <connect gate="G$1" pin="PB2-BOOT1" pad="27"/>- <connect gate="G$1" pin="PE7" pad="28"/>- <connect gate="G$1" pin="PE8" pad="29"/>- <connect gate="G$1" pin="PE9" pad="30"/>- <connect gate="G$1" pin="PE10" pad="31"/>- <connect gate="G$1" pin="PE11" pad="32"/>- <connect gate="G$1" pin="PE12" pad="33"/>- <connect gate="G$1" pin="PE13" pad="34"/>- <connect gate="G$1" pin="PE14" pad="35"/>- <connect gate="G$1" pin="PE15" pad="36"/>- <connect gate="G$1" pin="PB10" pad="37"/>- <connect gate="G$1" pin="PB11" pad="38"/>- <connect gate="G$1" pin="VCAP_1" pad="39"/>- <connect gate="G$1" pin="VDD" pad="40"/>- <connect gate="G$1" pin="PB12" pad="41"/>- <connect gate="G$1" pin="PB13" pad="42"/>- <connect gate="G$1" pin="PB14" pad="43"/>- <connect gate="G$1" pin="PB15" pad="44"/>- <connect gate="G$1" pin="PD8" pad="45"/>- <connect gate="G$1" pin="PD9" pad="46"/>- <connect gate="G$1" pin="PD10" pad="47"/>- <connect gate="G$1" pin="PD11" pad="48"/>- <connect gate="G$1" pin="PD12" pad="49"/>- <connect gate="G$1" pin="PD13" pad="50"/>- <connect gate="G$1" pin="PE1" pad="100"/>- <connect gate="G$1" pin="PE0" pad="99"/>- <connect gate="G$1" pin="PB9" pad="98"/>- <connect gate="G$1" pin="PB8" pad="97"/>- <connect gate="G$1" pin="BOOT0" pad="96"/>- <connect gate="G$1" pin="PB5" pad="95"/>- <connect gate="G$1" pin="PB4_NJTRST" pad="94"/>- <connect gate="G$1" pin="PB3_JTDO/TRACESWO" pad="93"/>- <connect gate="G$1" pin="VDD@2" pad="92"/>- <connect gate="G$1" pin="VSS" pad="91"/>- <connect gate="G$1" pin="PI3" pad="90"/>- <connect gate="G$1" pin="PI2" pad="89"/>- <connect gate="G$1" pin="PI1" pad="88"/>- <connect gate="G$1" pin="PI0" pad="87"/>- <connect gate="G$1" pin="PH15" pad="86"/>- <connect gate="G$1" pin="PH14" pad="85"/>- <connect gate="G$1" pin="PH13" pad="84"/>- <connect gate="G$1" pin="PG15" pad="83"/>- <connect gate="G$1" pin="PG14" pad="82"/>- <connect gate="G$1" pin="PG13" pad="81"/>- <connect gate="G$1" pin="PG12" pad="80"/>- <connect gate="G$1" pin="PG11" pad="79"/>- <connect gate="G$1" pin="PD7" pad="78"/>- <connect gate="G$1" pin="PD6" pad="77"/>- <connect gate="G$1" pin="PD5" pad="76"/>- <connect gate="G$1" pin="PD4" pad="75"/>- <connect gate="G$1" pin="PD3" pad="74"/>- <connect gate="G$1" pin="PD2" pad="73"/>- <connect gate="G$1" pin="PD1" pad="72"/>- <connect gate="G$1" pin="PD0" pad="71"/>- <connect gate="G$1" pin="PC12" pad="70"/>- <connect gate="G$1" pin="PC11" pad="69"/>- <connect gate="G$1" pin="PC10" pad="68"/>- <connect gate="G$1" pin="PA15_JTDI" pad="67"/>- <connect gate="G$1" pin="PA14_JTCK-SWCLK" pad="66"/>- <connect gate="G$1" pin="VDD@3" pad="65"/>- <connect gate="G$1" pin="VSS@2" pad="64"/>- <connect gate="G$1" pin="VCAP_2" pad="63"/>- <connect gate="G$1" pin="PA13_JTMS-SWDIO" pad="62"/>- <connect gate="G$1" pin="PA12" pad="61"/>- <connect gate="G$1" pin="PA11" pad="60"/>- <connect gate="G$1" pin="PA10" pad="59"/>- <connect gate="G$1" pin="PA9" pad="58"/>- <connect gate="G$1" pin="PA8" pad="57"/>- <connect gate="G$1" pin="PC9" pad="56"/>- <connect gate="G$1" pin="PC8" pad="55"/>- <connect gate="G$1" pin="PC7" pad="54"/>- <connect gate="G$1" pin="PC6" pad="53"/>- <connect gate="G$1" pin="PD15" pad="52"/>- <connect gate="G$1" pin="PD14" pad="51"/>+ <connect gate="G$1" pin="PC14/OSC32_IN" pad="8"/>+ <connect gate="G$1" pin="PC15/OSC32_OUT" pad="9"/>+ <connect gate="G$1" pin="VSS" pad="10"/>+ <connect gate="G$1" pin="VDD" pad="11"/>+ <connect gate="G$1" pin="PH0/OSC_IN" pad="12"/>+ <connect gate="G$1" pin="PH1/OSC_OUT" pad="13"/>+ <connect gate="G$1" pin="NRST" pad="14"/>+ <connect gate="G$1" pin="PC0" pad="15"/>+ <connect gate="G$1" pin="PC1" pad="16"/>+ <connect gate="G$1" pin="PC2" pad="17"/>+ <connect gate="G$1" pin="PC3" pad="18"/>+ <connect gate="G$1" pin="VDD@2" pad="19"/>+ <connect gate="G$1" pin="VSSA" pad="20"/>+ <connect gate="G$1" pin="VREF+" pad="21"/>+ <connect gate="G$1" pin="VDDA" pad="22"/>+ <connect gate="G$1" pin="PA0/WKUP" pad="23"/>+ <connect gate="G$1" pin="PA1" pad="24"/>+ <connect gate="G$1" pin="PA2" pad="25"/>+ <connect gate="G$1" pin="PA3" pad="26"/>+ <connect gate="G$1" pin="VSS@2" pad="27"/>+ <connect gate="G$1" pin="VDD@3" pad="28"/>+ <connect gate="G$1" pin="PA4" pad="29"/>+ <connect gate="G$1" pin="PA5" pad="30"/>+ <connect gate="G$1" pin="PA6" pad="31"/>+ <connect gate="G$1" pin="PA7" pad="32"/>+ <connect gate="G$1" pin="PC4" pad="33"/>+ <connect gate="G$1" pin="PC5" pad="34"/>+ <connect gate="G$1" pin="PB0" pad="35"/>+ <connect gate="G$1" pin="PB1" pad="36"/>+ <connect gate="G$1" pin="PB2/BOOT1" pad="37"/>+ <connect gate="G$1" pin="PE7" pad="38"/>+ <connect gate="G$1" pin="PE8" pad="39"/>+ <connect gate="G$1" pin="PE9" pad="40"/>+ <connect gate="G$1" pin="PE10" pad="41"/>+ <connect gate="G$1" pin="PE11" pad="42"/>+ <connect gate="G$1" pin="PE12" pad="43"/>+ <connect gate="G$1" pin="PE13" pad="44"/>+ <connect gate="G$1" pin="PE14" pad="45"/>+ <connect gate="G$1" pin="PE15" pad="46"/>+ <connect gate="G$1" pin="PB10" pad="47"/>+ <connect gate="G$1" pin="PB11" pad="48"/>+ <connect gate="G$1" pin="VCAP_1" pad="49"/>+ <connect gate="G$1" pin="VDD@4" pad="50"/>+ <connect gate="G$1" pin="VDD@5" pad="100"/>+ <connect gate="G$1" pin="VSS@3" pad="99"/>+ <connect gate="G$1" pin="PE1" pad="98"/>+ <connect gate="G$1" pin="PE0" pad="97"/>+ <connect gate="G$1" pin="PB9" pad="96"/>+ <connect gate="G$1" pin="PB8" pad="95"/>+ <connect gate="G$1" pin="BOOT0" pad="94"/>+ <connect gate="G$1" pin="PB7" pad="93"/>+ <connect gate="G$1" pin="PB6" pad="92"/>+ <connect gate="G$1" pin="PB5" pad="91"/>+ <connect gate="G$1" pin="PB4" pad="90"/>+ <connect gate="G$1" pin="PB3" pad="89"/>+ <connect gate="G$1" pin="PD7" pad="88"/>+ <connect gate="G$1" pin="PD6" pad="87"/>+ <connect gate="G$1" pin="PD5" pad="86"/>+ <connect gate="G$1" pin="PD4" pad="85"/>+ <connect gate="G$1" pin="PD3" pad="84"/>+ <connect gate="G$1" pin="PD2" pad="83"/>+ <connect gate="G$1" pin="PD1" pad="82"/>+ <connect gate="G$1" pin="PD0" pad="81"/>+ <connect gate="G$1" pin="PC12" pad="80"/>+ <connect gate="G$1" pin="PC11" pad="79"/>+ <connect gate="G$1" pin="PC10" pad="78"/>+ <connect gate="G$1" pin="PA15" pad="77"/>+ <connect gate="G$1" pin="PA14" pad="76"/>+ <connect gate="G$1" pin="VDD@6" pad="75"/>+ <connect gate="G$1" pin="VSS@4" pad="74"/>+ <connect gate="G$1" pin="VCAP_2" pad="73"/>+ <connect gate="G$1" pin="PA13" pad="72"/>+ <connect gate="G$1" pin="PA12" pad="71"/>+ <connect gate="G$1" pin="PA11" pad="70"/>+ <connect gate="G$1" pin="PA10" pad="69"/>+ <connect gate="G$1" pin="PA9" pad="68"/>+ <connect gate="G$1" pin="PA8" pad="67"/>+ <connect gate="G$1" pin="PC9" pad="66"/>+ <connect gate="G$1" pin="PC8" pad="65"/>+ <connect gate="G$1" pin="PC7" pad="64"/>+ <connect gate="G$1" pin="PC6" pad="63"/>+ <connect gate="G$1" pin="PD15" pad="62"/>+ <connect gate="G$1" pin="PD14" pad="61"/>+ <connect gate="G$1" pin="PD13" pad="60"/>+ <connect gate="G$1" pin="PD12" pad="59"/>+ <connect gate="G$1" pin="PD11" pad="58"/>+ <connect gate="G$1" pin="PD10" pad="57"/>+ <connect gate="G$1" pin="PD9" pad="56"/>+ <connect gate="G$1" pin="PD8" pad="55"/>+ <connect gate="G$1" pin="PB15" pad="54"/>+ <connect gate="G$1" pin="PB14" pad="53"/>+ <connect gate="G$1" pin="PB13" pad="52"/>+ <connect gate="G$1" pin="PB12" pad="51"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="STM32F427VIT6" constant="no"/>+ <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8576729041816653824" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32f427vit6" constant="no"/>+ <attribute name="MOUSER_PN" value="511-STM32F427VIT6" constant="no"/>+ <attribute name="DIGIKEY_PN" value="497-14049-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C57097" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>