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STM32F417VGT6TR

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STMicroelectronics Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F417VGT6TR

STMicroelectronics · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

STM32F417VGT6TR from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant (FT) I/O; alternate functions include TRACECLK, FSMC_A23 and ETH_MII_TXD3.
2 PE3 bidirectional 5 V-tolerant (FT) I/O; alternate functions include TRACED0 and FSMC_A19.
3 PE4 bidirectional 5 V-tolerant (FT) I/O; alternate functions include TRACED1, FSMC_A20 and DCMI_D4.
4 PE5 bidirectional 5 V-tolerant (FT) I/O; alternate functions include TRACED2, FSMC_A21, TIM9_CH1 and DCMI_D6.
5 PE6 bidirectional 5 V-tolerant (FT) I/O; alternate functions include TRACED3, FSMC_A22, TIM9_CH2 and DCMI_D7.
6 VBAT power_in Backup supply pin for the RTC, the 20x32-bit backup registers and the optional 4 KB backup SRAM.
7 PC13 bidirectional 5 V-tolerant I/O supplied through the power switch, which sinks only 3 mA, so output use is limited to 2 MHz at 30 pF maximum load and it must not be used as a current source; alternates RTC_OUT, RTC_TAMP1 and RTC_TS.
8 PC14/OSC32_IN bidirectional Power-switch-supplied I/O with the same 3 mA, 2 MHz and 30 pF output limits as PC13, also used as the 32 kHz oscillator input OSC32_IN.
9 PC15/OSC32_OUT bidirectional Power-switch-supplied I/O with the same 3 mA, 2 MHz and 30 pF output limits as PC13, also used as the 32 kHz oscillator output OSC32_OUT.
10 VSS power_in Ground pin.
11 VDD power_in Supply pin for the I/Os and the digital core (application supply 1.8 V to 3.6 V).
12 PH0/OSC_IN bidirectional 5 V-tolerant I/O (FT except in oscillator mode) that serves as the high-speed external oscillator input OSC_IN.
13 PH1/OSC_OUT bidirectional 5 V-tolerant I/O (FT except in oscillator mode) that serves as the high-speed external oscillator output OSC_OUT.
14 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
15 PC0 bidirectional 5 V-tolerant I/O (except in analog mode); alternate OTG_HS_ULPI_STP and analog input ADC123_IN10.
16 PC1 bidirectional 5 V-tolerant I/O (except in analog mode); alternate ETH_MDC and analog input ADC123_IN11.
17 PC2 bidirectional 5 V-tolerant I/O (except in analog mode); alternates SPI2_MISO, I2S2ext_SD, OTG_HS_ULPI_DIR and ETH_MII_TXD2; analog input ADC123_IN12.
18 PC3 bidirectional 5 V-tolerant I/O (except in analog mode); alternates SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT and ETH_MII_TX_CLK; analog input ADC123_IN13.
19 VDD power_in Supply pin for the I/Os and the digital core (application supply 1.8 V to 3.6 V).
20 VSSA power_in Dedicated analog ground pin.
21 VREF+ power_in Positive reference voltage pin for the ADC, which can be decoupled separately or connected to VDDA as shown in the reference decoupling figures.
22 VDDA power_in Analog supply pin for the ADCs, DACs and related analog circuitry.
23 PA0/WKUP bidirectional 5 V-tolerant I/O with the WKUP wake-up function and analog input ADC123_IN0; alternates include USART2_CTS, UART4_TX and TIM2_CH1_ETR.
24 PA1 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC123_IN1; alternates include USART2_RTS, UART4_RX, TIM5_CH2 and ETH_RMII_REF_CLK.
25 PA2 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC123_IN2; alternates include USART2_TX, TIM5_CH3, TIM9_CH1 and ETH_MDIO.
26 PA3 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC123_IN3; alternates include USART2_RX, TIM5_CH4, TIM9_CH2 and OTG_HS_ULPI_D0.
27 VSS power_in Ground pin.
28 VDD power_in Supply pin for the I/Os and the digital core (application supply 1.8 V to 3.6 V).
29 PA4 bidirectional 3.3 V-tolerant TTa I/O directly connected to the ADC; alternates include SPI1_NSS, SPI3_NSS, USART2_CK and DCMI_HSYNC; analog outputs ADC12_IN4 and DAC_OUT1.
30 PA5 bidirectional 3.3 V-tolerant TTa I/O directly connected to the ADC; alternates include SPI1_SCK, OTG_HS_ULPI_CK and TIM2_CH1_ETR; analog pins ADC12_IN5 and DAC_OUT2.
31 PA6 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC12_IN6; alternates include SPI1_MISO, TIM8_BKIN, TIM13_CH1 and DCMI_PIXCLK.
32 PA7 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC12_IN7; alternates include SPI1_MOSI, TIM8_CH1N, TIM14_CH1 and ETH_MII_RX_DV.
33 PC4 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC12_IN14; alternates ETH_RMII_RX_D0 and ETH_MII_RX_D0.
34 PC5 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC12_IN15; alternates ETH_RMII_RX_D1 and ETH_MII_RX_D1.
35 PB0 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC12_IN8; alternates include TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1 and ETH_MII_RXD2.
36 PB1 bidirectional 5 V-tolerant I/O (except in analog mode); analog input ADC12_IN9; alternates include TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2 and ETH_MII_RXD3.
37 PB2/BOOT1 bidirectional 5 V-tolerant I/O whose pin name also carries the BOOT1 boot-mode function; alternate function EVENTOUT.
38 PE7 bidirectional 5 V-tolerant I/O; alternates include FSMC_D4 and TIM1_ETR.
39 PE8 bidirectional 5 V-tolerant I/O; alternates include FSMC_D5 and TIM1_CH1N.
40 PE9 bidirectional 5 V-tolerant I/O; alternates include FSMC_D6 and TIM1_CH1.
41 PE10 bidirectional 5 V-tolerant I/O; alternates include FSMC_D7 and TIM1_CH2N.
42 PE11 bidirectional 5 V-tolerant I/O; alternates include FSMC_D8 and TIM1_CH2.
43 PE12 bidirectional 5 V-tolerant I/O; alternates include FSMC_D9 and TIM1_CH3N.
44 PE13 bidirectional 5 V-tolerant I/O; alternates include FSMC_D10 and TIM1_CH3.
45 PE14 bidirectional 5 V-tolerant I/O; alternates include FSMC_D11 and TIM1_CH4.
46 PE15 bidirectional 5 V-tolerant I/O; alternates include FSMC_D12 and TIM1_BKIN.
47 PB10 bidirectional 5 V-tolerant I/O; alternates include SPI2_SCK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3 and TIM2_CH3.
48 PB11 bidirectional 5 V-tolerant I/O; alternates include I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN and TIM2_CH4.
49 VCAP_1 power_in Decoupling pin for the internal voltage regulator that requires an external capacitor (see VCAP_1/VCAP_2 external capacitor section).
50 VDD power_in Supply pin for the I/Os and the digital core (application supply 1.8 V to 3.6 V).
51 PB12 bidirectional 5 V-tolerant I/O; alternates include SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX and OTG_HS_ID.
52 PB13 bidirectional 5 V-tolerant I/O; alternates include SPI2_SCK, USART3_CTS, TIM1_CH1N, CAN2_TX and OTG_HS_ULPI_D6; additional function OTG_HS_VBUS.
53 PB14 bidirectional 5 V-tolerant I/O; alternates include SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM and USART3_RTS.
54 PB15 bidirectional 5 V-tolerant I/O; alternates include SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM12_CH2 and OTG_HS_DP; additional function RTC_REFIN.
55 PD8 bidirectional 5 V-tolerant I/O; alternates include FSMC_D13 and USART3_TX.
56 PD9 bidirectional 5 V-tolerant I/O; alternates include FSMC_D14 and USART3_RX.
57 PD10 bidirectional 5 V-tolerant I/O; alternates include FSMC_D15 and USART3_CK.
58 PD11 bidirectional 5 V-tolerant I/O; alternates include FSMC_CLE, FSMC_A16 and USART3_CTS.
59 PD12 bidirectional 5 V-tolerant I/O; alternates include FSMC_ALE, FSMC_A17, TIM4_CH1 and USART3_RTS.
60 PD13 bidirectional 5 V-tolerant I/O; alternates include FSMC_A18 and TIM4_CH2.
61 PD14 bidirectional 5 V-tolerant I/O; alternates include FSMC_D0 and TIM4_CH3.
62 PD15 bidirectional 5 V-tolerant I/O; alternates include FSMC_D1 and TIM4_CH4.
63 PC6 bidirectional 5 V-tolerant I/O; alternates include I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0 and TIM3_CH1.
64 PC7 bidirectional 5 V-tolerant I/O; alternates include I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1 and TIM3_CH2.
65 PC8 bidirectional 5 V-tolerant I/O; alternates include TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK and DCMI_D2.
66 PC9 bidirectional 5 V-tolerant I/O; alternates include MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, I2S_CKIN, DCMI_D3 and TIM3_CH4.
67 PA8 bidirectional 5 V-tolerant I/O; alternates include MCO1, USART1_CK, TIM1_CH1, I2C3_SCL and OTG_FS_SOF.
68 PA9 bidirectional 5 V-tolerant I/O; alternates include USART1_TX, TIM1_CH2, I2C3_SMBA and DCMI_D0; additional function OTG_FS_VBUS.
69 PA10 bidirectional 5 V-tolerant I/O; alternates include USART1_RX, TIM1_CH3, OTG_FS_ID and DCMI_D1.
70 PA11 bidirectional 5 V-tolerant I/O; alternates include USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM.
71 PA12 bidirectional 5 V-tolerant I/O; alternates include USART1_RTS, CAN1_TX, TIM1_ETR and OTG_FS_DP.
72 PA13 bidirectional 5 V-tolerant I/O; function JTMS-SWDIO (serial-wire debug data) after reset.
73 VCAP_2 power_in Decoupling pin for the internal voltage regulator that requires an external capacitor (see VCAP_1/VCAP_2 external capacitor section).
74 VSS power_in Ground pin.
75 VDD power_in Supply pin for the I/Os and the digital core (application supply 1.8 V to 3.6 V).
76 PA14 bidirectional 5 V-tolerant I/O; function JTCK-SWCLK (serial-wire debug clock) after reset.
77 PA15 bidirectional 5 V-tolerant I/O; function JTDI after reset; alternates include SPI3_NSS, I2S3_WS, TIM2_CH1_ETR and SPI1_NSS.
78 PC10 bidirectional 5 V-tolerant I/O; alternates include SPI3_SCK, I2S3_CK, UART4_TX, SDIO_D2, DCMI_D8 and USART3_TX.
79 PC11 bidirectional 5 V-tolerant I/O; alternates include UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX and I2S3ext_SD.
80 PC12 bidirectional 5 V-tolerant I/O; alternates include UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD and USART3_CK.
81 PD0 bidirectional 5 V-tolerant I/O; alternates include FSMC_D2 and CAN1_RX.
82 PD1 bidirectional 5 V-tolerant I/O; alternates include FSMC_D3 and CAN1_TX.
83 PD2 bidirectional 5 V-tolerant I/O; alternates include TIM3_ETR, UART5_RX, SDIO_CMD and DCMI_D11.
84 PD3 bidirectional 5 V-tolerant I/O; alternates include FSMC_CLK and USART2_CTS.
85 PD4 bidirectional 5 V-tolerant I/O; alternates include FSMC_NOE and USART2_RTS.
86 PD5 bidirectional 5 V-tolerant I/O; alternates include FSMC_NWE and USART2_TX.
87 PD6 bidirectional 5 V-tolerant I/O; alternates include FSMC_NWAIT and USART2_RX.
88 PD7 bidirectional 5 V-tolerant I/O; alternates include USART2_CK, FSMC_NE1 and FSMC_NCE2.
89 PB3 bidirectional 5 V-tolerant I/O; function JTDO/TRACESWO after reset; alternates include SPI3_SCK, I2S3_CK, TIM2_CH2 and SPI1_SCK.
90 PB4 bidirectional 5 V-tolerant I/O; function NJTRST after reset; alternates include SPI3_MISO, TIM3_CH1, SPI1_MISO and I2S3ext_SD.
91 PB5 bidirectional 5 V-tolerant I/O; alternates include I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10 and I2S3_SD.
92 PB6 bidirectional 5 V-tolerant I/O; alternates include I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5 and USART1_TX.
93 PB7 bidirectional 5 V-tolerant I/O; alternates include I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX and TIM4_CH2.
94 BOOT0 input Dedicated BOOT0 boot-mode selection input, also listed as the VPP pin for Flash programming.
95 PB8 bidirectional 5 V-tolerant I/O; alternates include TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL and CAN1_RX.
96 PB9 bidirectional 5 V-tolerant I/O; alternates include SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA and CAN1_TX.
97 PE0 bidirectional 5 V-tolerant I/O; alternates include TIM4_ETR, FSMC_NBL0 and DCMI_D2.
98 PE1 bidirectional 5 V-tolerant I/O; alternates include FSMC_NBL1 and DCMI_D3.
99 VSS power_in Ground pin.
100 VDD power_in Supply pin for the I/Os and the digital core (application supply 1.8 V to 3.6 V).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

CAD (KiCad official)

  • Symbol: STM32F417VGT6TR
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f417vgt6tr-etched.step / stm32f417vgt6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f417vgt6tr.step / stm32f417vgt6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (207 pp, sha256 da04336016c91137, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF