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STM32F415VGT6

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STMicroelectronics Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

STM32F415VGT6

STMicroelectronics · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

STM32F415VGT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO PE2, 5 V-tolerant I/O; alternate functions TRACECLK, FSMC_A23, ETH_MII_TXD3, EVENTOUT.
2 PE3 bidirectional GPIO PE3, 5 V-tolerant I/O; alternate functions TRACED0, FSMC_A19, EVENTOUT.
3 PE4 bidirectional GPIO PE4, 5 V-tolerant I/O; alternate functions TRACED1, FSMC_A20, DCMI_D4, EVENTOUT.
4 PE5 bidirectional GPIO PE5, 5 V-tolerant I/O; alternate functions TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6, EVENTOUT.
5 PE6 bidirectional GPIO PE6, 5 V-tolerant I/O; alternate functions TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7, EVENTOUT.
6 VBAT power_in Battery supply for RTC, backup SRAM, and 20×32-bit backup registers; range 1.65 V to 3.6 V; connect to VDD when not using a battery.
7 PC13 bidirectional GPIO PC13, 5 V-tolerant I/O supplied via power switch (max 2 MHz output, 30 pF load, no current source use); additional functions RTC_OUT, RTC_TAMP1, RTC_TS.
8 PC14 bidirectional GPIO PC14/OSC32_IN, 5 V-tolerant I/O (not FT in oscillator mode); can be used as 32 kHz LSE oscillator input (OSC32_IN).
9 PC15 bidirectional GPIO PC15/OSC32_OUT, 5 V-tolerant I/O (not FT in oscillator mode); can be used as 32 kHz LSE oscillator output (OSC32_OUT).
10 VSS power_in Ground reference for digital power supply domain.
11 VDD power_in Digital supply voltage 1.8 V to 3.6 V for I/O pins and internal digital logic.
12 PH0 bidirectional GPIO PH0/OSC_IN, 5 V-tolerant I/O (not FT in oscillator mode); can be used as 4-26 MHz HSE crystal oscillator input (OSC_IN).
13 PH1 bidirectional GPIO PH1/OSC_OUT, 5 V-tolerant I/O (not FT in oscillator mode); can be used as HSE crystal oscillator output (OSC_OUT).
14 NRST bidirectional Reset pin with embedded weak pull-up resistor; active-low system reset, can be driven externally or monitored for reset output.
15 PC0 bidirectional GPIO PC0, 5 V-tolerant I/O; alternate function OTG_HS_ULPI_STP; additional function ADC123_IN10.
16 PC1 bidirectional GPIO PC1, 5 V-tolerant I/O; alternate function ETH_MDC; additional function ADC123_IN11.
17 PC2 bidirectional GPIO PC2, 5 V-tolerant I/O; alternate functions SPI2_MISO/I2S2ext_SD, OTG_HS_ULPI_DIR, ETH_MII_TXD2; additional function ADC123_IN12.
18 PC3 bidirectional GPIO PC3, 5 V-tolerant I/O; alternate functions SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK; additional function ADC123_IN13.
19 VDD power_in Digital supply voltage 1.8 V to 3.6 V for I/O pins and internal digital logic.
20 VSSA power_in Ground reference for analog power supply domain (ADC, DAC, PLL); must be connected to VSS on the PCB.
21 VREF+ power_in Positive ADC and DAC reference voltage input; range VSSA ≤ VREF+ ≤ VDDA; decouple with 1 µF + 10 nF to VSSA.
22 VDDA power_in Analog supply voltage 1.8 V to 3.6 V for ADC, DAC, PLL, and internal references; must be ≥ VDD.
23 PA0 bidirectional GPIO PA0/WKUP, 5 V-tolerant I/O; standby wakeup pin; alternate functions TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, ETH_MII_CRS; additional functions ADC123_IN0, WKUP.
24 PA1 bidirectional GPIO PA1, 5 V-tolerant I/O; alternate functions TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK; additional function ADC123_IN1.
25 PA2 bidirectional GPIO PA2, 5 V-tolerant I/O; alternate functions TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, ETH_MDIO; additional function ADC123_IN2.
26 PA3 bidirectional GPIO PA3, 5 V-tolerant I/O; alternate functions TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, OTG_HS_ULPI_D0, ETH_MII_COL; additional function ADC123_IN3.
27 VSS power_in Ground reference for digital power supply domain.
28 VDD power_in Digital supply voltage 1.8 V to 3.6 V for I/O pins and internal digital logic.
29 PA4 bidirectional GPIO PA4, 3.3 V-tolerant I/O directly connected to ADC (TTa); alternate functions SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF; additional functions ADC12_IN4, DAC_OUT1.
30 PA5 bidirectional GPIO PA5, 3.3 V-tolerant I/O directly connected to ADC (TTa); alternate functions SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N; additional functions ADC12_IN5, DAC_OUT2.
31 PA6 bidirectional GPIO PA6, 5 V-tolerant I/O; alternate functions SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN; additional function ADC12_IN6.
32 PA7 bidirectional GPIO PA7, 5 V-tolerant I/O; alternate functions SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, TIM1_CH1N, ETH_RMII_CRS_DV; additional function ADC12_IN7.
33 PC4 bidirectional GPIO PC4, 5 V-tolerant I/O; alternate functions ETH_RMII_RX_D0, ETH_MII_RX_D0; additional function ADC12_IN14.
34 PC5 bidirectional GPIO PC5, 5 V-tolerant I/O; alternate functions ETH_RMII_RX_D1, ETH_MII_RX_D1; additional function ADC12_IN15.
35 PB0 bidirectional GPIO PB0, 5 V-tolerant I/O; alternate functions TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N; additional function ADC12_IN8.
36 PB1 bidirectional GPIO PB1, 5 V-tolerant I/O; alternate functions TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N; additional function ADC12_IN9.
37 PB2 bidirectional GPIO PB2/BOOT1, 5 V-tolerant I/O; sampled at reset as BOOT1 configuration input to select boot memory source.
38 PE7 bidirectional GPIO PE7, 5 V-tolerant I/O; alternate functions FSMC_D4, TIM1_ETR, EVENTOUT.
39 PE8 bidirectional GPIO PE8, 5 V-tolerant I/O; alternate functions FSMC_D5, TIM1_CH1N, EVENTOUT.
40 PE9 bidirectional GPIO PE9, 5 V-tolerant I/O; alternate functions FSMC_D6, TIM1_CH1, EVENTOUT.
41 PE10 bidirectional GPIO PE10, 5 V-tolerant I/O; alternate functions FSMC_D7, TIM1_CH2N, EVENTOUT.
42 PE11 bidirectional GPIO PE11, 5 V-tolerant I/O; alternate functions FSMC_D8, TIM1_CH2, EVENTOUT.
43 PE12 bidirectional GPIO PE12, 5 V-tolerant I/O; alternate functions FSMC_D9, TIM1_CH3N, EVENTOUT.
44 PE13 bidirectional GPIO PE13, 5 V-tolerant I/O; alternate functions FSMC_D10, TIM1_CH3, EVENTOUT.
45 PE14 bidirectional GPIO PE14, 5 V-tolerant I/O; alternate functions FSMC_D11, TIM1_CH4, EVENTOUT.
46 PE15 bidirectional GPIO PE15, 5 V-tolerant I/O; alternate functions FSMC_D12, TIM1_BKIN, EVENTOUT.
47 PB10 bidirectional GPIO PB10, 5 V-tolerant I/O; alternate functions SPI2_SCK/I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3.
48 PB11 bidirectional GPIO PB11, 5 V-tolerant I/O; alternate functions I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN, ETH_MII_TX_EN, TIM2_CH4.
49 VCAP_1 passive External decoupling capacitor node for internal 1.2 V voltage regulator output; requires 1 µF (ceramic) capacitor to VSS per Table 16.
50 VDD power_in Digital supply voltage 1.8 V to 3.6 V for I/O pins and internal digital logic.
51 PB12 bidirectional GPIO PB12, 5 V-tolerant I/O; alternate functions SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0, ETH_MII_TXD0, OTG_HS_ID.
52 PB13 bidirectional GPIO PB13, 5 V-tolerant I/O; alternate functions SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6, ETH_RMII_TXD1, ETH_MII_TXD1; additional function OTG_HS_VBUS.
53 PB14 bidirectional GPIO PB14, 5 V-tolerant I/O; alternate functions SPI2_MISO/I2S2ext_SD, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N.
54 PB15 bidirectional GPIO PB15, 5 V-tolerant I/O; alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP; additional function RTC_REFIN.
55 PD8 bidirectional GPIO PD8, 5 V-tolerant I/O; alternate functions FSMC_D13, USART3_TX, EVENTOUT.
56 PD9 bidirectional GPIO PD9, 5 V-tolerant I/O; alternate functions FSMC_D14, USART3_RX, EVENTOUT.
57 PD10 bidirectional GPIO PD10, 5 V-tolerant I/O; alternate functions FSMC_D15, USART3_CK, EVENTOUT.
58 PD11 bidirectional GPIO PD11, 5 V-tolerant I/O; alternate functions FSMC_CLE, FSMC_A16, USART3_CTS, EVENTOUT.
59 PD12 bidirectional GPIO PD12, 5 V-tolerant I/O; alternate functions FSMC_ALE, FSMC_A17, TIM4_CH1, USART3_RTS, EVENTOUT.
60 PD13 bidirectional GPIO PD13, 5 V-tolerant I/O; alternate functions FSMC_A18, TIM4_CH2, EVENTOUT.
61 PD14 bidirectional GPIO PD14, 5 V-tolerant I/O; alternate functions FSMC_D0, TIM4_CH3, EVENTOUT.
62 PD15 bidirectional GPIO PD15, 5 V-tolerant I/O; alternate functions FSMC_D1, TIM4_CH4, EVENTOUT.
63 PC6 bidirectional GPIO PC6, 5 V-tolerant I/O; alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1.
64 PC7 bidirectional GPIO PC7, 5 V-tolerant I/O; alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2.
65 PC8 bidirectional GPIO PC8, 5 V-tolerant I/O; alternate functions TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2.
66 PC9 bidirectional GPIO PC9, 5 V-tolerant I/O; alternate functions I2S_CKIN, MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4.
67 PA8 bidirectional GPIO PA8, 5 V-tolerant I/O; alternate functions MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF.
68 PA9 bidirectional GPIO PA9, 5 V-tolerant I/O; alternate functions USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0; additional function OTG_FS_VBUS.
69 PA10 bidirectional GPIO PA10, 5 V-tolerant I/O; alternate functions USART1_RX, TIM1_CH3, OTG_FS_ID, DCMI_D1.
70 PA11 bidirectional GPIO PA11, 5 V-tolerant I/O; alternate functions USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM.
71 PA12 bidirectional GPIO PA12, 5 V-tolerant I/O; alternate functions USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP.
72 PA13 bidirectional GPIO PA13 (default JTMS-SWDIO), 5 V-tolerant I/O; JTAG TMS / SWD data I/O signal; set as floating input during and after reset.
73 VCAP_2 passive External decoupling capacitor node for internal 1.2 V voltage regulator output; requires 1 µF (ceramic) capacitor to VSS per Table 16.
74 VSS power_in Ground reference for digital power supply domain.
75 VDD power_in Digital supply voltage 1.8 V to 3.6 V for I/O pins and internal digital logic.
76 PA14 bidirectional GPIO PA14 (default JTCK-SWCLK), 5 V-tolerant I/O; JTAG TCK / SWD clock input signal.
77 PA15 bidirectional GPIO PA15 (default JTDI), 5 V-tolerant I/O; alternate functions JTDI, SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, SPI1_NSS.
78 PC10 bidirectional GPIO PC10, 5 V-tolerant I/O; alternate functions SPI3_SCK/I2S3_CK, UART4_TX, SDIO_D2, DCMI_D8, USART3_TX.
79 PC11 bidirectional GPIO PC11, 5 V-tolerant I/O; alternate functions UART4_RX, SPI3_MISO/I2S3ext_SD, SDIO_D3, DCMI_D4, USART3_RX.
80 PC12 bidirectional GPIO PC12, 5 V-tolerant I/O; alternate functions UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI/I2S3_SD, USART3_CK.
81 PD0 bidirectional GPIO PD0, 5 V-tolerant I/O; alternate functions FSMC_D2, CAN1_RX, EVENTOUT.
82 PD1 bidirectional GPIO PD1, 5 V-tolerant I/O; alternate functions FSMC_D3, CAN1_TX, EVENTOUT.
83 PD2 bidirectional GPIO PD2, 5 V-tolerant I/O; alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT.
84 PD3 bidirectional GPIO PD3, 5 V-tolerant I/O; alternate functions FSMC_CLK, USART2_CTS, EVENTOUT.
85 PD4 bidirectional GPIO PD4, 5 V-tolerant I/O; alternate functions FSMC_NOE, USART2_RTS, EVENTOUT.
86 PD5 bidirectional GPIO PD5, 5 V-tolerant I/O; alternate functions FSMC_NWE, USART2_TX, EVENTOUT.
87 PD6 bidirectional GPIO PD6, 5 V-tolerant I/O; alternate functions FSMC_NWAIT, USART2_RX, EVENTOUT.
88 PD7 bidirectional GPIO PD7, 5 V-tolerant I/O; alternate functions USART2_CK, FSMC_NE1, FSMC_NCE2, EVENTOUT.
89 PB3 bidirectional GPIO PB3 (default JTDO/TRACESWO), 5 V-tolerant I/O; alternate functions JTDO, TRACESWO, SPI3_SCK/I2S3_CK, TIM2_CH2, SPI1_SCK.
90 PB4 bidirectional GPIO PB4 (default NJTRST), 5 V-tolerant I/O; alternate functions NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO, I2S3ext_SD.
91 PB5 bidirectional GPIO PB5, 5 V-tolerant I/O; alternate functions I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI/I2S3_SD, DCMI_D10.
92 PB6 bidirectional GPIO PB6, 5 V-tolerant I/O; alternate functions I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5, USART1_TX.
93 PB7 bidirectional GPIO PB7, 5 V-tolerant I/O; alternate functions I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX, TIM4_CH2.
94 BOOT0 input Dedicated BOOT0 input pin (type B); logic high at reset selects non-Flash boot source (system memory or SRAM) in combination with BOOT1 (PB2); has VPP function.
95 PB8 bidirectional GPIO PB8, 5 V-tolerant I/O; alternate functions TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX.
96 PB9 bidirectional GPIO PB9, 5 V-tolerant I/O; alternate functions SPI2_NSS/I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA, CAN1_TX.
97 PE0 bidirectional GPIO PE0, 5 V-tolerant I/O; alternate functions TIM4_ETR, FSMC_NBL0, DCMI_D2, EVENTOUT.
98 PE1 bidirectional GPIO PE1, 5 V-tolerant I/O; alternate functions FSMC_NBL1, DCMI_D3, EVENTOUT.
99 VSS power_in Ground reference for digital power supply domain (was PDR_ON in earlier silicon; changed to VSS on LQFP100 from Rev 2 of the datasheet).
100 VDD power_in Digital supply voltage 1.8 V to 3.6 V for I/O pins and internal digital logic.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

CAD (KiCad official)

  • Symbol: STM32F415VGT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f415vgt6-etched.step / stm32f415vgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f415vgt6.step / stm32f415vgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (186 pp, sha256 0a43b4c6d2c21667, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF