component
STM32F413CHU6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F413CHU6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32F413CHU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Power supply input for the VBAT backup domain that supplies the RTC, as listed in the table as the VBAT supply for RTC. |
| 2 | PC13-ANTI_TAMP | bidirectional | 5 V tolerant GPIO supplied through the power switch, which sinks at most 3 mA, so it must not be used as a current source and its output speed is limited to 2 MHz at 30 pF; additional function TAMP_1. |
| 3 | PC14-OSC32_IN | bidirectional | 5 V tolerant GPIO (FT except in analog or oscillator mode) supplied through the power switch with a 3 mA sink limit and a 2 MHz / 30 pF output limit in GPIO use; in oscillator mode it is the 32 kHz oscillator input OSC32_IN. |
| 4 | PC15-OSC32_OUT | bidirectional | 5 V tolerant GPIO (FT except in oscillator mode) supplied through the power switch with a 3 mA sink limit and a 2 MHz / 30 pF output limit in GPIO use; in oscillator mode it is the 32 kHz oscillator output OSC32_OUT. |
| 5 | PH0-OSC_IN | bidirectional | 5 V tolerant GPIO outside oscillator mode; in oscillator mode it is the OSC_IN input for the 4 to 26 MHz crystal oscillator. |
| 6 | PH1-OSC_OUT | bidirectional | 5 V tolerant GPIO outside oscillator mode; in oscillator mode it is the OSC_OUT output for the 4 to 26 MHz crystal oscillator. |
| 7 | NRST | bidirectional | Bidirectional reset pin with an embedded weak pull-up resistor. |
| 8 | VSSA | power_in | Analog ground pin for the analog peripherals. |
| 9 | VDDA | power_in | Analog supply pin for the analog peripherals; the supplied text gives no separate VDDA range, and the stated application supply is 1.7 to 3.6 V. |
| 10 | PA0 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX and additional functions ADC1_IN0 and WKUP1. |
| 11 | PA1 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3 and additional function ADC1_IN1. |
| 12 | PA2 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, FSMC_D4/FSMC_DA4 and additional function ADC1_IN2. |
| 13 | PA3 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, SAI1_SD_B, FSMC_D5/FSMC_DA5 and additional function ADC1_IN3. |
| 14 | PA4 | bidirectional | 3.3 V tolerant I/O (TTa) directly connected to DAC, floating input during and after reset, with alternate functions SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, DFSDM1_DATIN1, FSMC_D6/FSMC_DA6 and additional functions ADC1_IN4 and DAC_OUT1. |
| 15 | PA5 | bidirectional | 3.3 V tolerant I/O (TTa) directly connected to DAC, floating input during and after reset, with alternate functions TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, DFSDM1_CKIN1, FSMC_D7/FSMC_DA7 and additional functions ADC1_IN5 and DAC_OUT2. |
| 16 | PA6 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, DFSDM2_CKIN1, TIM13_CH1, QUADSPI_BK2_IO0, SDIO_CMD and additional function ADC1_IN6. |
| 17 | PA7 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, DFSDM2_DATIN1, TIM14_CH1, QUADSPI_BK2_IO1 and additional function ADC1_IN7. |
| 18 | PB0 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI5_SCK/I2S5_CK and additional function ADC1_IN8. |
| 19 | PB1 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI5_NSS/I2S5_WS, DFSDM1_DATIN0, QUADSPI_CLK and additional function ADC1_IN9. |
| 20 | PB2 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions LPTIM1_OUT, DFSDM1_CKIN0, QUADSPI_CLK and additional function BOOT1. |
| 21 | PB10 | bidirectional | 5 V tolerant GPIO with I2C FM+ option (FTf), floating input during and after reset, with alternate functions TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, USART3_TX, I2CFMP1_SCL, DFSDM2_CKOUT and SDIO_D7. |
| 22 | VCAP_1 | passive | Internal regulator decoupling pin that requires the external capacitor CEXT; its capacitor limits are given in section 6.3.2, which is outside the supplied text. |
| 23 | VSS | power_in | Ground pin for the digital core and I/Os (0 V reference). |
| 24 | VDD | power_in | Main supply pin for the application and I/Os, with an operating range of 1.7 to 3.6 V. |
| 25 | PB12 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, SPI3_SCK/I2S3_CK, USART3_CK, CAN2_RX, DFSDM1_DATIN1, UART5_RX and FSMC_D13/FSMC_DA13. |
| 26 | PB13 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_CH1N, I2CFMP1_SMBA, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, USART3_CTS, CAN2_TX, DFSDM1_CKIN1 and UART5_TX. |
| 27 | PB14 | bidirectional | 5 V tolerant GPIO with I2C FM+ option (FTf), floating input during and after reset, with alternate functions TIM1_CH2N, TIM8_CH2N, I2CFMP1_SDA, SPI2_MISO, I2S2ext_SD, USART3_RTS, DFSDM1_DATIN2, TIM12_CH1, FSMC_D0/FSMC_DA0 and SDIO_D6. |
| 28 | PB15 | bidirectional | 5 V tolerant GPIO with I2C FM+ option (FTf), floating input during and after reset, with alternate functions RTC_REFIN, TIM1_CH3N, TIM8_CH3N, I2CFMP1_SCL, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, TIM12_CH2 and SDIO_CK. |
| 29 | PA8 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions MCO_1, TIM1_CH1, I2C3_SCL, DFSDM1_CKOUT, USART1_CK, UART7_RX, USB_FS_SOF, CAN3_RX and SDIO_D1. |
| 30 | PA9 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_CH2, DFSDM2_CKIN3, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, USB_FS_VBUS and SDIO_D2. |
| 31 | PA10 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_CH3, DFSDM2_DATIN3, SPI2_MOSI/I2S2_SD, SPI5_MOSI/I2S5_SD, USART1_RX and USB_FS_ID. |
| 32 | PA11 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_CH4, DFSDM2_CKIN5, SPI2_NSS/I2S2_WS, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, USB_FS_DM and UART4_RX. |
| 33 | PA12 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions TIM1_ETR, DFSDM2_DATIN5, SPI2_MISO, SPI5_MISO, USART1_RTS, USART6_RX, CAN1_TX, USB_FS_DP and UART4_TX. |
| 34 | PA13 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate function JTMS-SWDIO for serial wire debug. |
| 35 | VSS | power_in | Ground pin for the digital core and I/Os (0 V reference). |
| 36 | VDD | power_in | Main supply pin for the application and I/Os, with an operating range of 1.7 to 3.6 V. |
| 37 | PA14 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate function JTCK-SWCLK for serial wire debug. |
| 38 | PA15 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART1_TX, UART7_TX, SAI1_MCLK_A and CAN3_TX. |
| 39 | PB3 | bidirectional | 5 V tolerant GPIO with I2C FM+ option (FTf), floating input during and after reset, with alternate functions JTDO-SWO, TIM2_CH2, I2CFMP1_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX, UART7_RX, I2C2_SDA, SAI1_SD_A and CAN3_RX. |
| 40 | PB4 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions JTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, UART7_TX, I2C3_SDA, SAI1_SCK_A, CAN3_TX and SDIO_D0. |
| 41 | PB5 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions LPTIM1_IN1, TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, SAI1_FS_A, UART5_RX and SDIO_D3. |
| 42 | PB6 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions LPTIM1_ETR, TIM4_CH1, I2C1_SCL, DFSDM2_CKIN7, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, UART5_TX and SDIO_D0. |
| 43 | PB7 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions LPTIM1_IN2, TIM4_CH2, I2C1_SDA, DFSDM2_DATIN7, USART1_RX and FSMC_NL. |
| 44 | BOOT0 | input | Dedicated BOOT0 pin used to select the boot mode; Table 10 also lists VPP as an additional function on this pin. |
| 45 | PB8 | bidirectional | 5 V tolerant GPIO, floating input during and after reset, with alternate functions LPTIM1_OUT, TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, DFSDM2_CKIN1, CAN1_RX, I2C3_SDA, UART5_RX and SDIO_D4. |
| 46 | PB9 | bidirectional | 5 V tolerant GPIO with I2C FM+ option (FTf), floating input during and after reset, with alternate functions TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, DFSDM2_DATIN1, CAN1_TX, I2C2_SDA, UART5_TX and SDIO_D5. |
| 47 | VSS | power_in | Ground pin for the digital core and I/Os (0 V reference). |
| 48 | VDD | power_in | Main supply pin for the application and I/Os, with an operating range of 1.7 to 3.6 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32F413CHU6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32f413chu6-etched.step/stm32f413chu6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f413chu6.step/stm32f413chu6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (208 pp, sha256
f6011311b70d14ef, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).