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STM32F412VGT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F412VGT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
STM32F412VGT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V-tolerant I/O (FT) with TRACECLK, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, QUADSPI_BK1_IO2, FSMC_A23 and EVENTOUT alternate functions. |
| 2 | PE3 | bidirectional | 5 V-tolerant I/O (FT) with TRACED0, FSMC_A19 and EVENTOUT alternate functions. |
| 3 | PE4 | bidirectional | 5 V-tolerant I/O (FT) with TRACED1, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, DFSDM1_DATIN3, FSMC_A20 and EVENTOUT alternate functions. |
| 4 | PE5 | bidirectional | 5 V-tolerant I/O (FT) with TRACED2, TIM9_CH1, SPI4_MISO, SPI5_MISO, DFSDM1_CKIN3, FSMC_A21 and EVENTOUT alternate functions. |
| 5 | PE6 | bidirectional | 5 V-tolerant I/O (FT) with TRACED3, TIM9_CH2, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, FSMC_A22 and EVENTOUT alternate functions. |
| 6 | VBAT | power_in | Backup battery supply pin for the RTC, backup registers and backup domain. |
| 7 | PC13 | bidirectional | 5 V-tolerant I/O powered through the power switch (EVENTOUT, TAMP_1); as output limited to 2 MHz with max 30 pF load and must not source current (e.g. drive an LED). |
| 8 | PC14-OSC32_IN | bidirectional | I/O or 32 kHz oscillator input (OSC32_IN), supplied through the power switch with output limited to 2 MHz and 30 pF; 5 V tolerant except in oscillator mode. |
| 9 | PC15-OSC32_OUT | bidirectional | I/O or 32 kHz oscillator output (OSC32_OUT), supplied through the power switch with output limited to 2 MHz and 30 pF; 5 V tolerant except in oscillator mode. |
| 10 | VSS | power_in | Ground supply pin. |
| 11 | VDD | power_in | Digital supply pin (application supply 1.7 V to 3.6 V). |
| 12 | PH0-OSC_IN | bidirectional | I/O or 4-26 MHz main oscillator input (OSC_IN); 5 V tolerant except in oscillator mode. |
| 13 | PH1-OSC_OUT | bidirectional | I/O or 4-26 MHz main oscillator output (OSC_OUT); 5 V tolerant except in oscillator mode. |
| 14 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 15 | PC0 | bidirectional | 5 V-tolerant I/O with EVENTOUT and analog functions ADC1_10 and WKUP2. |
| 16 | PC1 | bidirectional | 5 V-tolerant I/O with EVENTOUT and analog functions ADC1_11 and WKUP3. |
| 17 | PC2 | bidirectional | 5 V-tolerant I/O with SPI2_MISO, I2S2ext_SD, DFSDM1_CKOUT, FSMC_NWE, EVENTOUT and ADC1_12. |
| 18 | PC3 | bidirectional | 5 V-tolerant I/O with SPI2_MOSI/I2S2_SD, FSMC_A0, EVENTOUT and ADC1_13. |
| 19 | VDD | power_in | Digital supply pin (application supply 1.7 V to 3.6 V). |
| 20 | VSSA/VREF- | power_in | Analog ground, shared with the negative ADC reference voltage on this package. |
| 21 | VREF+ | power_in | Positive reference voltage input for the ADC. |
| 22 | VDDA | power_in | Analog supply pin for ADC and analog circuitry. |
| 23 | PA0 | bidirectional | 5 V-tolerant I/O with TIM2_CH1/ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, EVENTOUT, ADC1_0 and WKUP1. |
| 24 | PA1 | bidirectional | 5 V-tolerant I/O with TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, QUADSPI_BK1_IO3, EVENTOUT and ADC1_1. |
| 25 | PA2 | bidirectional | 5 V-tolerant I/O with TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, FSMC_D4/DA4, EVENTOUT and ADC1_2. |
| 26 | PA3 | bidirectional | 5 V-tolerant I/O with TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, FSMC_D5/DA5, EVENTOUT and ADC1_3. |
| 27 | VSS | power_in | Ground supply pin. |
| 28 | VDD | power_in | Digital supply pin (application supply 1.7 V to 3.6 V). |
| 29 | PA4 | bidirectional | 5 V-tolerant I/O with SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, DFSDM1_DATIN1, FSMC_D6/DA6, EVENTOUT and ADC1_4. |
| 30 | PA5 | bidirectional | 5 V-tolerant I/O with TIM2_CH1/ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, DFSDM1_CKIN1, FSMC_D7/DA7, EVENTOUT and ADC1_5. |
| 31 | PA6 | bidirectional | 5 V-tolerant I/O with TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, QUADSPI_BK2_IO0, SDIO_CMD, EVENTOUT and ADC1_6. |
| 32 | PA7 | bidirectional | 5 V-tolerant I/O with TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1, QUADSPI_BK2_IO1, EVENTOUT and ADC1_7. |
| 33 | PC4 | bidirectional | 5 V-tolerant I/O with I2S1_MCK, QUADSPI_BK2_IO2, FSMC_NE4, EVENTOUT and ADC1_14. |
| 34 | PC5 | bidirectional | 5 V-tolerant I/O with I2CFMP1_SMBA, USART3_RX, QUADSPI_BK2_IO3, FSMC_NOE, EVENTOUT and ADC1_15. |
| 35 | PB0 | bidirectional | 5 V-tolerant I/O with TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI5_SCK/I2S5_CK, EVENTOUT and ADC1_8. |
| 36 | PB1 | bidirectional | 5 V-tolerant I/O with TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI5_NSS/I2S5_WS, DFSDM1_DATIN0, QUADSPI_CLK, EVENTOUT and ADC1_9. |
| 37 | PB2 | bidirectional | 5 V-tolerant I/O with DFSDM1_CKIN0, QUADSPI_CLK, EVENTOUT; additional function BOOT1. |
| 38 | PE7 | bidirectional | 5 V-tolerant I/O with TIM1_ETR, DFSDM1_DATIN2, QUADSPI_BK2_IO0, FSMC_D4/DA4 and EVENTOUT. |
| 39 | PE8 | bidirectional | 5 V-tolerant I/O with TIM1_CH1N, DFSDM1_CKIN2, QUADSPI_BK2_IO1, FSMC_D5/DA5 and EVENTOUT. |
| 40 | PE9 | bidirectional | 5 V-tolerant I/O with TIM1_CH1, DFSDM1_CKOUT, QUADSPI_BK2_IO2, FSMC_D6/DA6 and EVENTOUT. |
| 41 | PE10 | bidirectional | 5 V-tolerant I/O with TIM1_CH2N, QUADSPI_BK2_IO3, FSMC_D7/DA7 and EVENTOUT. |
| 42 | PE11 | bidirectional | 5 V-tolerant I/O with TIM1_CH2, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, FSMC_D8/DA8 and EVENTOUT. |
| 43 | PE12 | bidirectional | 5 V-tolerant I/O with TIM1_CH3N, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, FSMC_D9/DA9 and EVENTOUT. |
| 44 | PE13 | bidirectional | 5 V-tolerant I/O with TIM1_CH3, SPI4_MISO, SPI5_MISO, FSMC_D10/DA10 and EVENTOUT. |
| 45 | PE14 | bidirectional | 5 V-tolerant I/O with TIM1_CH4, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, FSMC_D11/DA11 and EVENTOUT. |
| 46 | PE15 | bidirectional | 5 V-tolerant I/O with TIM1_BKIN, FSMC_D12/DA12 and EVENTOUT. |
| 47 | PB10 | bidirectional | 5 V-tolerant I/O with TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, USART3_TX, I2CFMP1_SCL, SDIO_D7 and EVENTOUT. |
| 48 | VCAP_1 | passive | Connection for the external capacitor of the internal 1.2 V voltage regulator. |
| 49 | VSS | power_in | Ground supply pin. |
| 50 | VDD | power_in | Digital supply pin (application supply 1.7 V to 3.6 V). |
| 51 | PB12 | bidirectional | 5 V-tolerant I/O with TIM1_BKIN, I2C2_SMBA, SPI2/SPI3/SPI4 NSS/SCK, USART3_CK, CAN2_RX, DFSDM1_DATIN1, FSMC_D13/DA13 and EVENTOUT. |
| 52 | PB13 | bidirectional | 5 V-tolerant I/O with TIM1_CH1N, I2CFMP1_SMBA, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, USART3_CTS, CAN2_TX, DFSDM1_CKIN1 and EVENTOUT. |
| 53 | PB14 | bidirectional | 5 V-tolerant I/O with TIM1_CH2N, TIM8_CH2N, I2CFMP1_SDA, SPI2_MISO, I2S2ext_SD, USART3_RTS, DFSDM1_DATIN2, TIM12_CH1, FSMC_D0/DA0, SDIO_D6 and EVENTOUT. |
| 54 | PB15 | bidirectional | 5 V-tolerant I/O with RTC_50Hz, TIM1_CH3N, TIM8_CH3N, I2CFMP1_SCL, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, TIM12_CH2, SDIO_CK and EVENTOUT. |
| 55 | PD8 | bidirectional | 5 V-tolerant I/O with USART3_TX, FSMC_D13/DA13 and EVENTOUT. |
| 56 | PD9 | bidirectional | 5 V-tolerant I/O with USART3_RX, FSMC_D14/DA14 and EVENTOUT. |
| 57 | PD10 | bidirectional | 5 V-tolerant I/O with USART3_CK, FSMC_D15/DA15 and EVENTOUT. |
| 58 | PD11 | bidirectional | 5 V-tolerant I/O with I2CFMP1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, FSMC_A16 and EVENTOUT. |
| 59 | PD12 | bidirectional | 5 V-tolerant I/O with TIM4_CH1, I2CFMP1_SCL, USART3_RTS, QUADSPI_BK1_IO1, FSMC_A17 and EVENTOUT. |
| 60 | PD13 | bidirectional | 5 V-tolerant I/O with TIM4_CH2, I2CFMP1_SDA, QUADSPI_BK1_IO3, FSMC_A18 and EVENTOUT. |
| 61 | PD14 | bidirectional | 5 V-tolerant I/O with TIM4_CH3, I2CFMP1_SCL, FSMC_D0/DA0 and EVENTOUT. |
| 62 | PD15 | bidirectional | 5 V-tolerant I/O with TIM4_CH4, I2CFMP1_SDA, FSMC_D1/DA1 and EVENTOUT. |
| 63 | PC6 | bidirectional | 5 V-tolerant I/O with TIM3_CH1, TIM8_CH1, I2CFMP1_SCL, I2S2_MCK, DFSDM1_CKIN3, USART6_TX, FSMC_D1/DA1, SDIO_D6 and EVENTOUT. |
| 64 | PC7 | bidirectional | 5 V-tolerant I/O with TIM3_CH2, TIM8_CH2, I2CFMP1_SDA, SPI2_SCK/I2S2_CK, I2S3_MCK, USART6_RX, DFSDM1_DATIN3, SDIO_D7 and EVENTOUT. |
| 65 | PC8 | bidirectional | 5 V-tolerant I/O with TIM3_CH3, TIM8_CH3, USART6_CK, QUADSPI_BK1_IO2, SDIO_D0 and EVENTOUT. |
| 66 | PC9 | bidirectional | 5 V-tolerant I/O with MCO_2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S2_CKIN, QUADSPI_BK1_IO0, SDIO_D1 and EVENTOUT. |
| 67 | PA8 | bidirectional | 5 V-tolerant I/O with MCO_1, TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF, SDIO_D1 and EVENTOUT. |
| 68 | PA9 | bidirectional | 5 V-tolerant I/O with TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS, SDIO_D2 and EVENTOUT. |
| 69 | PA10 | bidirectional | 5 V-tolerant I/O with TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX, USB_FS_ID and EVENTOUT. |
| 70 | PA11 | bidirectional | 5 V-tolerant I/O with TIM1_CH4, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, USB_FS_DM and EVENTOUT. |
| 71 | PA12 | bidirectional | 5 V-tolerant I/O with TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX, CAN1_TX, USB_FS_DP and EVENTOUT. |
| 72 | PA13 | bidirectional | 5 V-tolerant I/O with JTMS-SWDIO debug function and EVENTOUT. |
| 73 | VCAP_2 | passive | Connection for the external capacitor of the internal 1.2 V voltage regulator. |
| 74 | VSS | power_in | Ground supply pin. |
| 75 | VDD | power_in | Digital supply pin (application supply 1.7 V to 3.6 V). |
| 76 | PA14 | bidirectional | 5 V-tolerant I/O with JTCK-SWCLK debug function and EVENTOUT. |
| 77 | PA15 | bidirectional | 5 V-tolerant I/O with JTDI, TIM2_CH1/ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART1_TX and EVENTOUT. |
| 78 | PC10 | bidirectional | 5 V-tolerant I/O with SPI3_SCK/I2S3_CK, USART3_TX, QUADSPI_BK1_IO1, SDIO_D2 and EVENTOUT. |
| 79 | PC11 | bidirectional | 5 V-tolerant I/O with I2S3ext_SD, SPI3_MISO, USART3_RX, QUADSPI_BK2_NCS, FSMC_D2/DA2, SDIO_D3 and EVENTOUT. |
| 80 | PC12 | bidirectional | 5 V-tolerant I/O with SPI3_MOSI/I2S3_SD, USART3_CK, FSMC_D3/DA3, SDIO_CK and EVENTOUT. |
| 81 | PD0 | bidirectional | 5 V-tolerant I/O with CAN1_RX, FSMC_D2/DA2 and EVENTOUT. |
| 82 | PD1 | bidirectional | 5 V-tolerant I/O with CAN1_TX, FSMC_D3/DA3 and EVENTOUT. |
| 83 | PD2 | bidirectional | 5 V-tolerant I/O with TIM3_ETR, FSMC_NWE, SDIO_CMD and EVENTOUT. |
| 84 | PD3 | bidirectional | 5 V-tolerant I/O with TRACED1, SPI2_SCK/I2S2_CK, DFSDM1_DATIN0, USART2_CTS, QUADSPI_CLK, FSMC_CLK and EVENTOUT. |
| 85 | PD4 | bidirectional | 5 V-tolerant I/O with DFSDM1_CKIN0, USART2_RTS, FSMC_NOE and EVENTOUT. |
| 86 | PD5 | bidirectional | 5 V-tolerant I/O with USART2_TX, FSMC_NWE and EVENTOUT. |
| 87 | PD6 | bidirectional | 5 V-tolerant I/O with SPI3_MOSI/I2S3_SD, DFSDM1_DATIN1, USART2_RX, FSMC_NWAIT and EVENTOUT. |
| 88 | PD7 | bidirectional | 5 V-tolerant I/O with DFSDM1_CKIN1, USART2_CK, FSMC_NE1 and EVENTOUT. |
| 89 | PB3 | bidirectional | 5 V-tolerant I/O with JTDO-SWO, TIM2_CH2, I2CFMP1_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX, I2C2_SDA and EVENTOUT. |
| 90 | PB4 | bidirectional | 5 V-tolerant I/O with JTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, SDIO_D0 and EVENTOUT. |
| 91 | PB5 | bidirectional | 5 V-tolerant I/O with TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, SDIO_D3 and EVENTOUT. |
| 92 | PB6 | bidirectional | 5 V-tolerant I/O with TIM4_CH1, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, SDIO_D0 and EVENTOUT. |
| 93 | PB7 | bidirectional | 5 V-tolerant I/O with TIM4_CH2, I2C1_SDA, USART1_RX, FSMC_NL and EVENTOUT. |
| 94 | BOOT0 | input | Dedicated boot mode selection input pin (also VPP function). |
| 95 | PB8 | bidirectional | 5 V-tolerant I/O with TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, CAN1_RX, I2C3_SDA, SDIO_D4 and EVENTOUT. |
| 96 | PB9 | bidirectional | 5 V-tolerant I/O with TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, I2C2_SDA, SDIO_D5 and EVENTOUT. |
| 97 | PE0 | bidirectional | 5 V-tolerant I/O with TIM4_ETR, FSMC_NBL0 and EVENTOUT. |
| 98 | PE1 | bidirectional | 5 V-tolerant I/O with FSMC_NBL1 and EVENTOUT. |
| 99 | VSS | power_in | Ground supply pin. |
| 100 | VDD | power_in | Digital supply pin (application supply 1.7 V to 3.6 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
STM32F412VGT6 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32f412vgt6-etched.step/stm32f412vgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f412vgt6.step/stm32f412vgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (201 pp, sha256
f1e0b8449d87680f, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).