component
STM32F412RGT6TR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
5 files changed
+290−153
README.md+24−6@@ -12,15 +12,15 @@ STM32F412RGT6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin des | 2 | PC13 | bidirectional | GPIO Port C bit 13, 5 V tolerant I/O with output speed limited to 2 MHz and maximum 30 pF load due to power switch limitation. | | 3 | PC14-OSC32_IN | bidirectional | GPIO Port C bit 14 / 32 kHz oscillator input, 5 V tolerant I/O except in oscillator mode. | | 4 | PC15-OSC32_OUT | bidirectional | GPIO Port C bit 15 / 32 kHz oscillator output, 5 V tolerant I/O except in oscillator mode. |-| 5 | PH0-OSC_IN | bidirectional | GPIO Port H bit 0 / main crystal oscillator input for 4-26 MHz, 5 V tolerant I/O except in oscillator mode. |-| 6 | PH1-OSC_OUT | bidirectional | GPIO Port H bit 1 / main crystal oscillator output for 4-26 MHz, 5 V tolerant I/O except in oscillator mode. |-| 7 | NRST | bidirectional | Reset input with embedded weak pull-up resistor, active low, triggers system reset or wakes from low-power modes. |+| 5 | PH0 - OSC_IN | bidirectional | GPIO Port H bit 0 / main crystal oscillator input for 4-26 MHz, 5 V tolerant I/O except in oscillator mode. |+| 6 | PH1 - OSC_OUT | bidirectional | GPIO Port H bit 1 / main crystal oscillator output for 4-26 MHz, 5 V tolerant I/O except in oscillator mode. |+| 7 | NRST | input | Reset input with embedded weak pull-up resistor, active low, triggers system reset or wakes from low-power modes. | | 8 | PC0 | bidirectional | GPIO Port C bit 0, 5 V tolerant I/O with ADC1_10 analog input capability. | | 9 | PC1 | bidirectional | GPIO Port C bit 1, 5 V tolerant I/O with ADC1_11 analog input capability. | | 10 | PC2 | bidirectional | GPIO Port C bit 2, 5 V tolerant I/O supporting SPI2_MISO, I2S2, DFSDM1, and FSMC alternate functions with ADC1_12 capability. | | 11 | PC3 | bidirectional | GPIO Port C bit 3, 5 V tolerant I/O supporting SPI2_MOSI, I2S2_SD, and FSMC alternate functions with ADC1_13 capability. |-| 12 | VSSA/VREF- | power_in | Analog ground supply and negative reference voltage for ADC, must be connected to VSS through low-impedance path. |-| 13 | VDDA/VREF+ | power_in | Analog power supply and positive reference voltage for ADC, 1.7 V to 3.6 V, must be decoupled with capacitors per application design. |+| 12 | VSSA | power_in | Analog ground supply and negative reference voltage for ADC, must be connected to VSS through low-impedance path. |+| 13 | VDDA | power_in | Analog power supply and positive reference voltage for ADC, 1.7 V to 3.6 V, must be decoupled with capacitors per application design. | | 14 | PA0 | bidirectional | GPIO Port A bit 0, 5 V tolerant I/O supporting TIM2/TIM5/TIM8 and USART2 alternate functions with ADC1_0 analog input. | | 15 | PA1 | bidirectional | GPIO Port A bit 1, 5 V tolerant I/O supporting TIM2/TIM5, SPI4, and QUADSPI alternate functions with ADC1_1 analog input. | | 16 | PA2 | bidirectional | GPIO Port A bit 2, 5 V tolerant I/O supporting TIM2/TIM5/TIM9, I2S2, USART2, and FSMC alternate functions with ADC1_2 capability. |@@ -37,13 +37,31 @@ STM32F412RGT6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin des | 27 | PB1 | bidirectional | GPIO Port B bit 1, 5 V tolerant I/O supporting TIM1/TIM3/TIM8, SPI5, DFSDM1, and QUADSPI alternate functions with ADC1_9. | | 28 | PB2 | bidirectional | GPIO Port B bit 2, 5 V tolerant I/O supporting DFSDM1 and QUADSPI alternate functions; BOOT1 option bit. | | 29 | PB10 | bidirectional | GPIO Port B bit 10, 5 V tolerant I/O supporting TIM2, I2C2, SPI2, I2S3, USART3, I2CFMP1, and SDIO alternate functions. |-| 30 | VCAP_1 | passive | Internal voltage regulator output decoupling pin, requires 100 nF capacitor connected to VSS for voltage regulation stability. |+| 30 | VCAP_1 | power_in | Internal voltage regulator output decoupling pin, requires 100 nF capacitor connected to VSS for voltage regulation stability. | | 31 | VSS | power_in | Digital ground supply pin for core digital logic circuits. | | 32 | VDD | power_in | Main digital power supply, 1.7 V to 3.6 V operating range, requires decoupling capacitors close to pin. | | 33 | PB12 | bidirectional | GPIO Port B bit 12, 5 V tolerant I/O supporting TIM1, I2C2, SPI2/SPI4/SPI3, USART3, CAN2, DFSDM1, and FSMC alternate functions. | | 34 | PB13 | bidirectional | GPIO Port B bit 13, 5 V tolerant I/O supporting TIM1, I2CFMP1, SPI2/SPI4, USART3, CAN2, and DFSDM1 alternate functions. | | 35 | PB14 | bidirectional | GPIO Port B bit 14, 5 V tolerant I/O supporting TIM1/TIM8/TIM12, I2CFMP1, SPI2, USART3, DFSDM1, FSMC, and SDIO alternate functions. | | 36 | PB15 | bidirectional | GPIO Port B bit 15, 5 V tolerant I/O supporting RTC output, TIM1/TIM8/TIM12, I2CFMP1, SPI2, DFSDM1, and SDIO alternate functions. |+| 37 | PC6 | bidirectional | |+| 38 | PC7 | bidirectional | |+| 39 | PC8 | bidirectional | |+| 40 | PC9 | bidirectional | |+| 41 | PA8 | bidirectional | |+| 42 | PA9 | bidirectional | |+| 43 | PA10 | bidirectional | |+| 44 | PA11 | bidirectional | |+| 45 | PA12 | bidirectional | |+| 46 | PA13 | bidirectional | |+| 47 | VSS | power_in | Digital ground supply pin for core digital logic circuits. |+| 48 | VDD | power_in | Main digital power supply, 1.7 V to 3.6 V operating range, requires decoupling capacitors close to pin. |+| 49 | PA14 | bidirectional | |+| 50 | PA15 | bidirectional | |+| 51 | PC10 | bidirectional | |+| 52 | PC11 | bidirectional | |+| 53 | PC12 | bidirectional | |+| 54 | PD2 | bidirectional | | | 55 | PB3 | bidirectional | GPIO Port B bit 3, 5 V tolerant I/O supporting JTAG/SWD debug, TIM2, I2CFMP1, SPI1/SPI3, USART1, and I2C2 alternate functions. | | 56 | PB4 | bidirectional | GPIO Port B bit 4, 5 V tolerant I/O supporting JTAG reset, TIM3, SPI1/SPI3, I2S3, I2C3, and SDIO alternate functions. | | 57 | PB5 | bidirectional | GPIO Port B bit 5, 5 V tolerant I/O supporting TIM3, I2C1, SPI1/SPI3, CAN2, and SDIO alternate functions. |
package.json+2−2@@ -1,6 +1,6 @@ { "slug": "stm32f412rgt6tr",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.", "tags": [@@ -361,4 +361,4 @@ "footprint": "viewers/footprint.html" } }-}+}
page.json+4−4@@ -4,7 +4,7 @@ "slug": "stm32f412rgt6tr", "title": "STM32F412RGT6TR", "brief": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -388,7 +388,7 @@ "viewers/symbol.html", "viewers/footprint.html" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "org": "adom" }
stm32f412rgt6tr.kicad_sym+143−71@@ -1,196 +1,268 @@ (kicad_symbol_lib (version 20211014) (generator ds2sf_rect) (symbol "STM32F412RGT6TR" (in_bom yes) (on_board yes)- (property "Reference" "U" (at 0 33.02 0) (effects (font (size 1.27 1.27))))- (property "Value" "STM32F412RGT6TR" (at 0 -33.02 0) (effects (font (size 1.27 1.27))))+ (property "Reference" "U" (at 0 43.18 0) (effects (font (size 1.27 1.27))))+ (property "Value" "STM32F412RGT6TR" (at 0 -45.72 0) (effects (font (size 1.27 1.27)))) (property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide)) (symbol "STM32F412RGT6TR_0_1"- (rectangle (start -12.70 30.48) (end 12.70 -30.48)+ (rectangle (start -12.70 40.64) (end 12.70 -43.18) (stroke (width 0.254) (type default)) (fill (type background))) ) (symbol "STM32F412RGT6TR_1_1"- (pin power_in line (at -17.78 27.94 0) (length 5.08)+ (pin power_in line (at -17.78 38.10 0) (length 5.08) (name "VBAT" (effects (font (size 1.27 1.27)))) (number "1" (effects (font (size 1.27 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stm32f412rgt6tr.lbr+117−70@@ -50,7 +50,7 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data</description> <packages> <package name="LQFP-64_10x10mm_P0.5mm"> <description>LQFP-64, 10 x 10 mm, 0.5 mm pitch</description>@@ -144,63 +144,82 @@ </packages> <symbols> <symbol name="STM32F412RGT6TR">- <wire x1="-12.7" y1="30.48" x2="12.7" y2="30.48" width="0.254" layer="94"/>- <wire x1="12.7" y1="30.48" x2="12.7" y2="-30.48" width="0.254" layer="94"/>- <wire x1="12.7" y1="-30.48" x2="-12.7" y2="-30.48" width="0.254" layer="94"/>- <wire x1="-12.7" y1="-30.48" x2="-12.7" y2="30.48" width="0.254" layer="94"/>- <text x="0.0000" y="33.0200" size="1.27" layer="95" align="center">>NAME</text>- <text x="0.0000" y="-33.0200" size="1.27" layer="96" align="center">>VALUE</text>- <pin name="VBAT" x="-17.78" y="27.94" length="middle" direction="pwr"/>- <pin name="PC13" x="-17.78" y="25.4" length="middle" direction="io"/>- <pin name="PC14-OSC32_IN" x="-17.78" y="22.86" length="middle" direction="io"/>- <pin name="PC15-OSC32_OUT" x="-17.78" y="20.32" length="middle" direction="io"/>- <pin name="PH0-OSC_IN" x="-17.78" y="17.78" length="middle" direction="io"/>- <pin name="PH1-OSC_OUT" x="-17.78" y="15.24" length="middle" direction="io"/>- <pin name="NRST" x="-17.78" y="12.7" length="middle" direction="io"/>- <pin name="PC0" x="-17.78" y="10.16" length="middle" direction="io"/>- <pin name="PC1" x="-17.78" y="7.62" length="middle" direction="io"/>- <pin name="PC2" x="-17.78" y="5.08" length="middle" direction="io"/>- <pin name="PC3" x="-17.78" y="2.54" length="middle" direction="io"/>- <pin name="VSSA/VREF-" x="-17.78" y="0" length="middle" direction="pwr"/>- <pin name="VDDA/VREF+" x="-17.78" y="-2.54" length="middle" direction="pwr"/>- <pin name="PA0" x="-17.78" y="-5.08" length="middle" direction="io"/>- <pin name="PA1" x="-17.78" y="-7.62" length="middle" direction="io"/>- <pin name="PA2" x="-17.78" y="-10.16" length="middle" direction="io"/>- <pin name="PA3" x="-17.78" y="-12.7" length="middle" direction="io"/>- <pin name="VSS" x="-17.78" y="-15.24" length="middle" direction="pwr"/>- <pin name="VDD" x="-17.78" y="-17.78" length="middle" direction="pwr"/>- <pin name="PA4" x="-17.78" y="-20.32" length="middle" direction="io"/>- <pin name="PA5" x="-17.78" y="-22.86" length="middle" direction="io"/>- <pin name="PA6" x="-17.78" y="-25.4" length="middle" direction="io"/>- <pin name="PA7" x="-17.78" y="-27.94" length="middle" direction="io"/>- <pin name="VDD@2" x="17.78" y="27.94" length="middle" direction="pwr" rot="R180"/>- <pin name="VSS@2" x="17.78" y="25.4" length="middle" direction="pwr" rot="R180"/>- <pin name="PB9" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>- <pin name="PB8" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>- <pin name="BOOT0" x="17.78" y="17.78" length="middle" direction="in" rot="R180"/>- <pin name="PB7" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>- <pin name="PB6" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>- <pin name="PB5" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>- <pin name="PB4" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>- <pin name="PB3" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>- <pin name="PB15" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>- <pin name="PB14" x="17.78" y="0" length="middle" direction="io" rot="R180"/>- <pin name="PB13" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>- <pin name="PB12" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>- <pin name="VDD@3" x="17.78" y="-7.62" length="middle" direction="pwr" rot="R180"/>- <pin name="VSS@3" x="17.78" y="-10.16" length="middle" direction="pwr" rot="R180"/>- <pin name="VCAP_1" x="17.78" y="-12.7" length="middle" direction="pas" rot="R180"/>- <pin name="PB10" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>- <pin name="PB2" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>- <pin name="PB1" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>- <pin name="PB0" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>- <pin name="PC5" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>- <pin name="PC4" x="17.78" y="-27.94" length="middle" direction="io" rot="R180"/>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data</description>+ <wire x1="-12.7" y1="40.64" x2="12.7" y2="40.64" width="0.254" layer="94"/>+ <wire x1="12.7" y1="40.64" x2="12.7" y2="-43.18" width="0.254" layer="94"/>+ <wire x1="12.7" y1="-43.18" x2="-12.7" y2="-43.18" width="0.254" layer="94"/>+ <wire x1="-12.7" y1="-43.18" x2="-12.7" y2="40.64" width="0.254" layer="94"/>+ <text x="0.0000" y="43.1800" size="1.27" layer="95" align="center">>NAME</text>+ <text x="0.0000" y="-45.7200" size="1.27" layer="96" align="center">>VALUE</text>+ <pin name="VBAT" x="-17.78" y="38.1" length="middle" direction="pwr"/>+ <pin name="PC13" x="-17.78" y="35.56" length="middle" direction="io"/>+ <pin name="PC14-OSC32_IN" x="-17.78" y="33.02" length="middle" direction="io"/>+ <pin name="PC15-OSC32_OUT" x="-17.78" y="30.48" length="middle" direction="io"/>+ <pin name="PH0_-_OSC_IN" x="-17.78" y="27.94" length="middle" direction="io"/>+ <pin name="PH1_-_OSC_OUT" x="-17.78" y="25.4" length="middle" direction="io"/>+ <pin name="NRST" x="-17.78" y="22.86" length="middle" direction="in"/>+ <pin name="PC0" x="-17.78" y="20.32" length="middle" direction="io"/>+ <pin name="PC1" x="-17.78" y="17.78" length="middle" direction="io"/>+ <pin name="PC2" x="-17.78" y="15.24" length="middle" direction="io"/>+ <pin name="PC3" x="-17.78" y="12.7" length="middle" direction="io"/>+ <pin name="VSSA" x="-17.78" y="10.16" length="middle" direction="pwr"/>+ <pin name="VDDA" x="-17.78" y="7.62" length="middle" direction="pwr"/>+ <pin name="PA0" x="-17.78" y="5.08" length="middle" direction="io"/>+ <pin name="PA1" x="-17.78" y="2.54" length="middle" direction="io"/>+ <pin name="PA2" x="-17.78" y="0" length="middle" direction="io"/>+ <pin name="PA3" x="-17.78" y="-2.54" length="middle" direction="io"/>+ <pin name="VSS" x="-17.78" y="-5.08" length="middle" direction="pwr"/>+ <pin name="VDD" x="-17.78" y="-7.62" length="middle" direction="pwr"/>+ <pin name="PA4" x="-17.78" y="-10.16" length="middle" direction="io"/>+ <pin name="PA5" x="-17.78" y="-12.7" length="middle" direction="io"/>+ <pin name="PA6" x="-17.78" y="-15.24" length="middle" direction="io"/>+ <pin name="PA7" x="-17.78" y="-17.78" length="middle" direction="io"/>+ <pin name="PC4" x="-17.78" y="-20.32" length="middle" direction="io"/>+ <pin name="PC5" x="-17.78" y="-22.86" length="middle" direction="io"/>+ <pin name="PB0" x="-17.78" y="-25.4" length="middle" direction="io"/>+ <pin name="PB1" x="-17.78" y="-27.94" length="middle" direction="io"/>+ <pin name="PB2" x="-17.78" y="-30.48" length="middle" direction="io"/>+ <pin name="PB10" x="-17.78" y="-33.02" length="middle" direction="io"/>+ <pin name="VCAP_1" x="-17.78" y="-35.56" length="middle" direction="pwr"/>+ <pin name="VSS@2" x="-17.78" y="-38.1" length="middle" direction="pwr"/>+ <pin name="VDD@2" x="-17.78" y="-40.64" length="middle" direction="pwr"/>+ <pin name="VDD@3" x="17.78" y="38.1" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@3" x="17.78" y="35.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="PB9" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/>+ <pin name="PB8" x="17.78" y="30.48" length="middle" direction="io" rot="R180"/>+ <pin name="BOOT0" x="17.78" y="27.94" length="middle" direction="in" rot="R180"/>+ <pin name="PB7" x="17.78" y="25.4" length="middle" direction="io" rot="R180"/>+ <pin name="PB6" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>+ <pin name="PB5" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PB4" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PB3" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PD2" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PC12" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PC11" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PC10" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="PA15" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PA14" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@4" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@4" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/>+ <pin name="PA13" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PA12" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PA11" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PA10" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PA9" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PA8" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PC9" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>+ <pin name="PC8" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>+ <pin name="PC7" x="17.78" y="-27.94" length="middle" direction="io" rot="R180"/>+ <pin name="PC6" x="17.78" y="-30.48" length="middle" direction="io" rot="R180"/>+ <pin name="PB15" x="17.78" y="-33.02" length="middle" direction="io" rot="R180"/>+ <pin name="PB14" x="17.78" y="-35.56" length="middle" direction="io" rot="R180"/>+ <pin name="PB13" x="17.78" y="-38.1" length="middle" direction="io" rot="R180"/>+ <pin name="PB12" x="17.78" y="-40.64" length="middle" direction="io" rot="R180"/> </symbol> </symbols> <devicesets> <deviceset name="STM32F412RGT6TR" prefix="U">- <description></description>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data</description> <gates> <gate name="G$1" symbol="STM32F412RGT6TR" x="0" y="0"/> </gates>@@ -211,15 +230,15 @@ <connect gate="G$1" pin="PC13" pad="2"/> <connect gate="G$1" pin="PC14-OSC32_IN" pad="3"/> <connect gate="G$1" pin="PC15-OSC32_OUT" pad="4"/>- <connect gate="G$1" pin="PH0-OSC_IN" pad="5"/>- <connect gate="G$1" pin="PH1-OSC_OUT" pad="6"/>+ <connect gate="G$1" pin="PH0_-_OSC_IN" pad="5"/>+ <connect gate="G$1" pin="PH1_-_OSC_OUT" pad="6"/> <connect gate="G$1" pin="NRST" pad="7"/> <connect gate="G$1" pin="PC0" pad="8"/> <connect gate="G$1" pin="PC1" pad="9"/> <connect gate="G$1" pin="PC2" pad="10"/> <connect gate="G$1" pin="PC3" pad="11"/>- <connect gate="G$1" pin="VSSA/VREF-" pad="12"/>- <connect gate="G$1" pin="VDDA/VREF+" pad="13"/>+ <connect gate="G$1" pin="VSSA" pad="12"/>+ <connect gate="G$1" pin="VDDA" pad="13"/> <connect gate="G$1" pin="PA0" pad="14"/> <connect gate="G$1" pin="PA1" pad="15"/> <connect gate="G$1" pin="PA2" pad="16"/>@@ -230,8 +249,17 @@ <connect gate="G$1" pin="PA5" pad="21"/> <connect gate="G$1" pin="PA6" pad="22"/> <connect gate="G$1" pin="PA7" pad="23"/>- <connect gate="G$1" pin="VDD@2" pad="64"/>- <connect gate="G$1" pin="VSS@2" pad="63"/>+ <connect gate="G$1" pin="PC4" pad="24"/>+ <connect gate="G$1" pin="PC5" pad="25"/>+ <connect gate="G$1" pin="PB0" pad="26"/>+ <connect gate="G$1" pin="PB1" pad="27"/>+ <connect gate="G$1" pin="PB2" pad="28"/>+ <connect gate="G$1" pin="PB10" pad="29"/>+ <connect gate="G$1" pin="VCAP_1" pad="30"/>+ <connect gate="G$1" pin="VSS@2" pad="31"/>+ <connect gate="G$1" pin="VDD@2" pad="32"/>+ <connect gate="G$1" pin="VDD@3" pad="64"/>+ <connect gate="G$1" pin="VSS@3" pad="63"/> <connect gate="G$1" pin="PB9" pad="62"/> <connect gate="G$1" pin="PB8" pad="61"/> <connect gate="G$1" pin="BOOT0" pad="60"/>@@ -240,21 +268,40 @@ <connect gate="G$1" pin="PB5" pad="57"/> <connect gate="G$1" pin="PB4" pad="56"/> <connect gate="G$1" pin="PB3" pad="55"/>+ <connect gate="G$1" pin="PD2" pad="54"/>+ <connect gate="G$1" pin="PC12" pad="53"/>+ <connect gate="G$1" pin="PC11" pad="52"/>+ <connect gate="G$1" pin="PC10" pad="51"/>+ <connect gate="G$1" pin="PA15" pad="50"/>+ <connect gate="G$1" pin="PA14" pad="49"/>+ <connect gate="G$1" pin="VDD@4" pad="48"/>+ <connect gate="G$1" pin="VSS@4" pad="47"/>+ <connect gate="G$1" pin="PA13" pad="46"/>+ <connect gate="G$1" pin="PA12" pad="45"/>+ <connect gate="G$1" pin="PA11" pad="44"/>+ <connect gate="G$1" pin="PA10" pad="43"/>+ <connect gate="G$1" pin="PA9" pad="42"/>+ <connect gate="G$1" pin="PA8" pad="41"/>+ <connect gate="G$1" pin="PC9" pad="40"/>+ <connect gate="G$1" pin="PC8" pad="39"/>+ <connect gate="G$1" pin="PC7" pad="38"/>+ <connect gate="G$1" pin="PC6" pad="37"/> <connect gate="G$1" pin="PB15" pad="36"/> <connect gate="G$1" pin="PB14" pad="35"/> <connect gate="G$1" pin="PB13" pad="34"/> <connect gate="G$1" pin="PB12" pad="33"/>- <connect gate="G$1" pin="VDD@3" pad="32"/>- <connect gate="G$1" pin="VSS@3" pad="31"/>- <connect gate="G$1" pin="VCAP_1" pad="30"/>- <connect gate="G$1" pin="PB10" pad="29"/>- <connect gate="G$1" pin="PB2" pad="28"/>- <connect gate="G$1" pin="PB1" pad="27"/>- <connect gate="G$1" pin="PB0" pad="26"/>- <connect gate="G$1" pin="PC5" pad="25"/>- <connect gate="G$1" pin="PC4" pad="24"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="STM32F412RGT6TR" constant="no"/>+ <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588942390082351104" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32f412rgt6tr" constant="no"/>+ <attribute name="MOUSER_PN" value="511-STM32F412RGT6TR" constant="no"/>+ <attribute name="DIGIKEY_PN" value="497-18785-2-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C2053691" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>