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STM32F412CGU6TR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F412CGU6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32F412CGU6TR from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply input for the RTC (VBAT supply for RTC).
2 PC13 bidirectional 5 V tolerant I/O powered through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz at 30 pF and the pin must not be used as a current source such as an LED driver; additional functions TAMP_1 and EVENTOUT.
3 PC14-OSC32_IN bidirectional I/O powered through the power switch with the same 3 mA and 2 MHz output limits as PC13, multiplexed with the 32 kHz oscillator input OSC32_IN; 5 V tolerant except in analog or oscillator mode.
4 PC15-OSC32_OUT bidirectional I/O powered through the power switch with the same 3 mA and 2 MHz output limits as PC13, multiplexed with the 32 kHz oscillator output OSC32_OUT; 5 V tolerant except in oscillator mode.
5 PH0-OSC_IN bidirectional Multiplexed with the 4-to-26 MHz crystal oscillator input OSC_IN; 5 V tolerant except when in oscillator mode.
6 PH1-OSC_OUT bidirectional Multiplexed with the 4-to-26 MHz crystal oscillator output OSC_OUT; 5 V tolerant except when in oscillator mode.
7 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor.
8 VSSA/VREF- power_in Analog ground pin, also the ADC negative reference VREF-.
9 VDDA/VREF+ power_in Analog supply pin, also the ADC positive reference VREF+ (may be connected to VDDA per the ADC decoupling configurations).
10 PA0 bidirectional 5 V tolerant I/O with ADC1_0 and WKUP1 additional functions; alternate functions include TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR and USART2_CTS.
11 PA1 bidirectional 5 V tolerant I/O with ADC1_1 additional function; alternate functions include TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS and QUADSPI_BK1_IO3.
12 PA2 bidirectional 5 V tolerant I/O with ADC1_2 additional function; alternate functions include TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX and FSMC_D4/FSMC_DA4.
13 PA3 bidirectional 5 V tolerant I/O with ADC1_3 additional function; alternate functions include TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX and FSMC_D5/FSMC_DA5.
14 PA4 bidirectional 5 V tolerant I/O with ADC1_4 additional function; alternate functions include SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, DFSDM1_DATIN1 and FSMC_D6/FSMC_DA6.
15 PA5 bidirectional 5 V tolerant I/O with ADC1_5 additional function; alternate functions include TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, DFSDM1_CKIN1 and FSMC_D7/FSMC_DA7.
16 PA6 bidirectional 5 V tolerant I/O with ADC1_6 additional function; alternate functions include TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, QUADSPI_BK2_IO0 and SDIO_CMD.
17 PA7 bidirectional 5 V tolerant I/O with ADC1_7 additional function; alternate functions include TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1 and QUADSPI_BK2_IO1.
18 PB0 bidirectional 5 V tolerant I/O with ADC1_8 additional function; alternate functions include TIM1_CH2N, TIM3_CH3, TIM8_CH2N and SPI5_SCK/I2S5_CK.
19 PB1 bidirectional 5 V tolerant I/O with ADC1_9 additional function; alternate functions include TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI5_NSS/I2S5_WS, DFSDM1_DATIN0 and QUADSPI_CLK.
20 PB2 bidirectional 5 V tolerant I/O that also carries the BOOT1 additional function; alternate functions include DFSDM1_CKIN0 and QUADSPI_CLK.
21 PB10 bidirectional 5 V tolerant I/O; alternate functions include TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, USART3_TX, I2CFMP1_SCL and SDIO_D7.
22 VCAP_1 power_in Connection for the external capacitor of the internal voltage regulator (see VCAP_1/VCAP_2 external capacitors, Section 6.3.2).
23 VSS power_in Ground pin.
24 VDD power_in Digital supply pin; the application supply and I/Os range from 1.7 V to 3.6 V.
25 PB12 bidirectional 5 V tolerant I/O; alternate functions include TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, USART3_CK, CAN2_RX and FSMC_D13/FSMC_DA13.
26 PB13 bidirectional 5 V tolerant I/O; alternate functions include TIM1_CH1N, I2CFMP1_SMBA, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, USART3_CTS, CAN2_TX and DFSDM1_CKIN1.
27 PB14 bidirectional 5 V tolerant I/O; alternate functions include TIM1_CH2N, TIM8_CH2N, I2CFMP1_SDA, SPI2_MISO, I2S2ext_SD, USART3_RTS, DFSDM1_DATIN2, TIM12_CH1, FSMC_D0/FSMC_DA0 and SDIO_D6.
28 PB15 bidirectional 5 V tolerant I/O with RTC_50Hz additional function; alternate functions include TIM1_CH3N, TIM8_CH3N, I2CFMP1_SCL, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, TIM12_CH2 and SDIO_CK.
29 PA8 bidirectional 5 V tolerant I/O; alternate functions include MCO_1, TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF and SDIO_D1.
30 PA9 bidirectional 5 V tolerant I/O; alternate functions include TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS and SDIO_D2.
31 PA10 bidirectional 5 V tolerant I/O; alternate functions include TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX and USB_FS_ID.
32 PA11 bidirectional 5 V tolerant I/O; alternate functions include TIM1_CH4, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX and USB_FS_DM.
33 PA12 bidirectional 5 V tolerant I/O; alternate functions include TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX, CAN1_TX and USB_FS_DP.
34 PA13 bidirectional 5 V tolerant I/O; alternate function JTMS-SWDIO (serial wire debug data).
35 VSS power_in Ground pin.
36 VDD power_in Digital supply pin; the application supply and I/Os range from 1.7 V to 3.6 V.
37 PA14 bidirectional 5 V tolerant I/O; alternate function JTCK-SWCLK (serial wire debug clock).
38 PA15 bidirectional 5 V tolerant I/O; alternate functions include JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS and USART1_TX.
39 PB3 bidirectional 5 V tolerant I/O; alternate functions include JTDO-SWO, TIM2_CH2, I2CFMP1_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX and I2C2_SDA.
40 PB4 bidirectional 5 V tolerant I/O; alternate functions include JTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA and SDIO_D0.
41 PB5 bidirectional 5 V tolerant I/O; alternate functions include TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX and SDIO_D3.
42 PB6 bidirectional 5 V tolerant I/O; alternate functions include TIM4_CH1, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS and SDIO_D0.
43 PB7 bidirectional 5 V tolerant I/O; alternate functions include TIM4_CH2, I2C1_SDA, USART1_RX and FSMC_NL.
44 BOOT0 input Dedicated BOOT0 input pin, also carrying the VPP function.
45 PB8 bidirectional 5 V tolerant I/O; alternate functions include TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, CAN1_RX, I2C3_SDA and SDIO_D4.
46 PB9 bidirectional 5 V tolerant I/O; alternate functions include TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, I2C2_SDA and SDIO_D5.
47 VSS power_in Ground pin.
48 VDD power_in Digital supply pin; the application supply and I/Os range from 1.7 V to 3.6 V.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: STM32F412CGU6TR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f412cgu6tr-etched.step / stm32f412cgu6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f412cgu6tr.step / stm32f412cgu6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (201 pp, sha256 4337e70ae6879f52, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF