component
STM32F412CGU6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
main
STM32F412CGU6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32F412CGU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Battery backup supply voltage connection, 1.7 V to 3.6 V for RTC and backup domain. |
| 2 | PC13 | bidirectional | 5V-tolerant general-purpose I/O pin with RTC tamper detection and event output capability; limited to 3 mA output current due to power switch. |
| 3 | PC14-OSC32_IN | bidirectional | 5V-tolerant general-purpose I/O or 32 kHz oscillator input with event output capability. |
| 4 | PC15-OSC32_OUT | bidirectional | 5V-tolerant general-purpose I/O or 32 kHz oscillator output with event output capability. |
| 5 | PH0-OSC_IN | bidirectional | 5V-tolerant general-purpose I/O or main oscillator input (4-26 MHz) with event output capability. |
| 6 | PH1-OSC_OUT | bidirectional | 5V-tolerant general-purpose I/O or main oscillator output (4-26 MHz) with event output capability. |
| 7 | NRST | bidirectional | Active-low reset input pin with internal weak pull-up resistor and glitch filter for system reset control. |
| 8 | VSSA/VREF- | power_in | Analog ground and ADC negative reference voltage pin; must be connected to VSS. |
| 9 | VDDA/VREF+ | power_in | Analog power supply and ADC positive reference voltage pin, 1.7 V to 3.6 V; requires 100 nF decoupling capacitor. |
| 10 | PA0 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH0 input, timer inputs/outputs, USART handshaking, and wakeup capability from low-power modes. |
| 11 | PA1 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH1 input, timer functions, SPI output, QUADSPI bank 1 I/O 3, and USART handshaking. |
| 12 | PA2 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH2 input, timer/I2S functions, and USART transmission. |
| 13 | PA3 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH3 input, timer/I2S functions, and USART reception. |
| 14 | PA4 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH4 input, SPI NSS/I2S handshaking, and DFSDM data input. |
| 15 | PA5 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH5 input, SPI clock / I2S clock, timer ETR, and DFSDM clock input. |
| 16 | PA6 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH6 input, timer input/output, SPI MISO, and SDIO command pin. |
| 17 | PA7 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH7 input, timer output, SPI MOSI/I2S data, and QUADSPI bank 2 I/O. |
| 18 | PB0 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH8 input, timer outputs, and SPI clock input. |
| 19 | PB1 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH9 input, timer outputs, SPI NSS, DFSDM, and QUADSPI clock. |
| 20 | PB2 | bidirectional | 5V-tolerant general-purpose I/O with BOOT1 pin function for boot configuration, DFSDM clock input, and QUADSPI clock capability. |
| 21 | PB10 | bidirectional | 5V-tolerant general-purpose I/O supporting I2C clock, SPI clock / I2S MCK, USART transmission, and SDIO data line 7. |
| 22 | VCAP_1 | passive | Voltage regulator capacitor pin for internal voltage regulator output; connect 100 nF to 1 µF ceramic capacitor to VSS. |
| 23 | VSS | power_in | Ground connection for digital circuits. |
| 24 | VDD | power_in | Main power supply voltage, 1.7 V to 3.6 V for digital core and I/Os. |
| 25 | PB12 | bidirectional | 5V-tolerant general-purpose I/O supporting timer input, I2C handshaking, SPI/I2S functions, USART clock, and CAN input. |
| 26 | PB13 | bidirectional | 5V-tolerant general-purpose I/O supporting timer input, I2C/SPI/I2S clock, USART handshaking, and CAN transmission. |
| 27 | PB14 | bidirectional | 5V-tolerant general-purpose I/O supporting timer outputs, I2C/SPI/I2S functions, USART handshaking, and SDIO data line 6. |
| 28 | PB15 | bidirectional | 5V-tolerant general-purpose I/O supporting RTC 50 Hz output, timer outputs, I2C/SPI/I2S functions, and SDIO clock. |
| 29 | PA8 | bidirectional | 5V-tolerant general-purpose I/O supporting MCO_1 clock output, timer input, I2C clock, USART clock, USB SOF, and SDIO data line 1. |
| 30 | PA9 | bidirectional | 5V-tolerant general-purpose I/O supporting USB VBUS sensing, timer output, I2C address detection, USART transmission, and SDIO data line 2. |
| 31 | PA10 | bidirectional | 5V-tolerant general-purpose I/O supporting USB ID input, timer input, SPI data input, and USART reception. |
| 32 | PA11 | bidirectional | 5V-tolerant general-purpose I/O supporting USB D- data signal, timer output, SPI input, USART handshaking, and CAN reception. |
| 33 | PA12 | bidirectional | 5V-tolerant general-purpose I/O supporting USB D+ data signal, timer input, SPI input, USART handshaking, and CAN transmission. |
| 34 | PA13 | bidirectional | JTAG/Serial Wire Debug Data I/O pin (SWDIO/JTMS) for in-circuit programming and debugging. |
| 35 | VSS | power_in | Ground connection for digital circuits. |
| 36 | VDD | power_in | Main power supply voltage, 1.7 V to 3.6 V for digital core and I/Os. |
| 37 | PA14 | bidirectional | JTAG/Serial Wire Debug Clock pin (SWCLK/JTCK) for in-circuit programming and debugging at 10 MHz maximum frequency. |
| 38 | PA15 | bidirectional | 5V-tolerant general-purpose I/O or JTAG test data input (JTDI), supporting timer, SPI, and USART functions. |
| 39 | PB3 | bidirectional | 5V-tolerant general-purpose I/O or JTAG test data output (JTDO/SWO), supporting timer, I2C, SPI/I2S clock, and USART functions. |
| 40 | PB4 | bidirectional | 5V-tolerant general-purpose I/O or JTAG reset (JTRST), supporting timer, SPI MISO, I2S extension, and I2C data functions. |
| 41 | PB5 | bidirectional | 5V-tolerant general-purpose I/O supporting timer output, I2C address detection, SPI/I2S data, and CAN reception. |
| 42 | PB6 | bidirectional | 5V-tolerant general-purpose I/O supporting timer output, I2C clock, USART transmission, CAN transmission, and QUADSPI chip select. |
| 43 | PB7 | bidirectional | 5V-tolerant general-purpose I/O supporting timer output, I2C data, USART reception, and FSMC address latch enable. |
| 44 | BOOT0 | input | Boot mode selection pin for selecting boot source (0=Flash, 1=System bootloader); also VPP for flash programming operations. |
| 45 | PB8 | bidirectional | 5V-tolerant general-purpose I/O supporting timer outputs, I2C clock, SPI/I2S data, CAN reception, and SDIO data line 4. |
| 46 | PB9 | bidirectional | 5V-tolerant general-purpose I/O supporting timer outputs, I2C data, SPI NSS/I2S handshaking, CAN transmission, and SDIO data line 5. |
| 47 | VSS | power_in | Ground connection for digital circuits. |
| 48 | VDD | power_in | Main power supply voltage, 1.7 V to 3.6 V for digital core and I/Os. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
STM32F412CGU6 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
stm32f412cgu6-etched.step/stm32f412cgu6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f412cgu6.step/stm32f412cgu6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (201 pp, sha256
d640babe702a369d, retrieved 2026-10-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STM32F412CGU6
**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)
STM32F412CGU6 from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Battery backup supply voltage connection, 1.7 V to 3.6 V for RTC and backup domain. |
| 2 | PC13 | bidirectional | 5V-tolerant general-purpose I/O pin with RTC tamper detection and event output capability; limited to 3 mA output current due to power switch. |
| 3 | PC14-OSC32_IN | bidirectional | 5V-tolerant general-purpose I/O or 32 kHz oscillator input with event output capability. |
| 4 | PC15-OSC32_OUT | bidirectional | 5V-tolerant general-purpose I/O or 32 kHz oscillator output with event output capability. |
| 5 | PH0-OSC_IN | bidirectional | 5V-tolerant general-purpose I/O or main oscillator input (4-26 MHz) with event output capability. |
| 6 | PH1-OSC_OUT | bidirectional | 5V-tolerant general-purpose I/O or main oscillator output (4-26 MHz) with event output capability. |
| 7 | NRST | bidirectional | Active-low reset input pin with internal weak pull-up resistor and glitch filter for system reset control. |
| 8 | VSSA/VREF- | power_in | Analog ground and ADC negative reference voltage pin; must be connected to VSS. |
| 9 | VDDA/VREF+ | power_in | Analog power supply and ADC positive reference voltage pin, 1.7 V to 3.6 V; requires 100 nF decoupling capacitor. |
| 10 | PA0 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH0 input, timer inputs/outputs, USART handshaking, and wakeup capability from low-power modes. |
| 11 | PA1 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH1 input, timer functions, SPI output, QUADSPI bank 1 I/O 3, and USART handshaking. |
| 12 | PA2 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH2 input, timer/I2S functions, and USART transmission. |
| 13 | PA3 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH3 input, timer/I2S functions, and USART reception. |
| 14 | PA4 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH4 input, SPI NSS/I2S handshaking, and DFSDM data input. |
| 15 | PA5 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH5 input, SPI clock / I2S clock, timer ETR, and DFSDM clock input. |
| 16 | PA6 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH6 input, timer input/output, SPI MISO, and SDIO command pin. |
| 17 | PA7 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH7 input, timer output, SPI MOSI/I2S data, and QUADSPI bank 2 I/O. |
| 18 | PB0 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH8 input, timer outputs, and SPI clock input. |
| 19 | PB1 | bidirectional | 5V-tolerant general-purpose I/O with ADC1_CH9 input, timer outputs, SPI NSS, DFSDM, and QUADSPI clock. |
| 20 | PB2 | bidirectional | 5V-tolerant general-purpose I/O with BOOT1 pin function for boot configuration, DFSDM clock input, and QUADSPI clock capability. |
| 21 | PB10 | bidirectional | 5V-tolerant general-purpose I/O supporting I2C clock, SPI clock / I2S MCK, USART transmission, and SDIO data line 7. |
| 22 | VCAP_1 | passive | Voltage regulator capacitor pin for internal voltage regulator output; connect 100 nF to 1 µF ceramic capacitor to VSS. |
| 23 | VSS | power_in | Ground connection for digital circuits. |
| 24 | VDD | power_in | Main power supply voltage, 1.7 V to 3.6 V for digital core and I/Os. |
| 25 | PB12 | bidirectional | 5V-tolerant general-purpose I/O supporting timer input, I2C handshaking, SPI/I2S functions, USART clock, and CAN input. |
| 26 | PB13 | bidirectional | 5V-tolerant general-purpose I/O supporting timer input, I2C/SPI/I2S clock, USART handshaking, and CAN transmission. |
| 27 | PB14 | bidirectional | 5V-tolerant general-purpose I/O supporting timer outputs, I2C/SPI/I2S functions, USART handshaking, and SDIO data line 6. |
| 28 | PB15 | bidirectional | 5V-tolerant general-purpose I/O supporting RTC 50 Hz output, timer outputs, I2C/SPI/I2S functions, and SDIO clock. |
| 29 | PA8 | bidirectional | 5V-tolerant general-purpose I/O supporting MCO_1 clock output, timer input, I2C clock, USART clock, USB SOF, and SDIO data line 1. |
| 30 | PA9 | bidirectional | 5V-tolerant general-purpose I/O supporting USB VBUS sensing, timer output, I2C address detection, USART transmission, and SDIO data line 2. |
| 31 | PA10 | bidirectional | 5V-tolerant general-purpose I/O supporting USB ID input, timer input, SPI data input, and USART reception. |
| 32 | PA11 | bidirectional | 5V-tolerant general-purpose I/O supporting USB D- data signal, timer output, SPI input, USART handshaking, and CAN reception. |
| 33 | PA12 | bidirectional | 5V-tolerant general-purpose I/O supporting USB D+ data signal, timer input, SPI input, USART handshaking, and CAN transmission. |
| 34 | PA13 | bidirectional | JTAG/Serial Wire Debug Data I/O pin (SWDIO/JTMS) for in-circuit programming and debugging. |
| 35 | VSS | power_in | Ground connection for digital circuits. |
| 36 | VDD | power_in | Main power supply voltage, 1.7 V to 3.6 V for digital core and I/Os. |
| 37 | PA14 | bidirectional | JTAG/Serial Wire Debug Clock pin (SWCLK/JTCK) for in-circuit programming and debugging at 10 MHz maximum frequency. |
| 38 | PA15 | bidirectional | 5V-tolerant general-purpose I/O or JTAG test data input (JTDI), supporting timer, SPI, and USART functions. |
| 39 | PB3 | bidirectional | 5V-tolerant general-purpose I/O or JTAG test data output (JTDO/SWO), supporting timer, I2C, SPI/I2S clock, and USART functions. |
| 40 | PB4 | bidirectional | 5V-tolerant general-purpose I/O or JTAG reset (JTRST), supporting timer, SPI MISO, I2S extension, and I2C data functions. |
| 41 | PB5 | bidirectional | 5V-tolerant general-purpose I/O supporting timer output, I2C address detection, SPI/I2S data, and CAN reception. |
| 42 | PB6 | bidirectional | 5V-tolerant general-purpose I/O supporting timer output, I2C clock, USART transmission, CAN transmission, and QUADSPI chip select. |
| 43 | PB7 | bidirectional | 5V-tolerant general-purpose I/O supporting timer output, I2C data, USART reception, and FSMC address latch enable. |
| 44 | BOOT0 | input | Boot mode selection pin for selecting boot source (0=Flash, 1=System bootloader); also VPP for flash programming operations. |
| 45 | PB8 | bidirectional | 5V-tolerant general-purpose I/O supporting timer outputs, I2C clock, SPI/I2S data, CAN reception, and SDIO data line 4. |
| 46 | PB9 | bidirectional | 5V-tolerant general-purpose I/O supporting timer outputs, I2C data, SPI NSS/I2S handshaking, CAN transmission, and SDIO data line 5. |
| 47 | VSS | power_in | Ground connection for digital circuits. |
| 48 | VDD | power_in | Main power supply voltage, 1.7 V to 3.6 V for digital core and I/Os. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFQFPN-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `STM32F412CGU6`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `stm32f412cgu6-etched.step` / `stm32f412cgu6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f412cgu6.step` / `stm32f412cgu6.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922750445998080) (201 pp, sha256 `d640babe702a369d`, retrieved 2026-10-06, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stm32f412cgu6-datasheet.pdf)