component
STM32F411CEY6TR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), WLCSP-49(3x3.2). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSTM32F411CEY6TR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · WLCSP-49(3x3.2)
STM32F411CEY6TR from STMicroelectronics, in a WLCSP-49(3x3.2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PA14 | bidirectional | 5 V-tolerant GPIO. Alternate function default JTCK-SWCLK: SWD/JTAG clock input. Also EVENTOUT. |
| A2 | PA15 | bidirectional | 5 V-tolerant GPIO. Alternate function default JTDI. Muxed with TIM2_CH1/TIM2_ETR, SPI1/3_NSS/I2S1/3_WS, USART1_TX, EVENTOUT. |
| A3 | PB3 | bidirectional | 5 V-tolerant GPIO. Alternate function default JTDO-SWO (SWO trace). Muxed with TIM2_CH2, SPI1/3_SCK/I2S1/3_CK, USART1_RX, I2C2_SDA, EVENTOUT. |
| A4 | PB4 | bidirectional | 5 V-tolerant GPIO. Alternate function default JTRST. Muxed with TIM3_CH1, SPI1/3_MISO, I2S3ext_SD, I2C3_SDA, SDIO_D0, EVENTOUT. |
| A5 | BOOT0 | input | Dedicated boot-mode select input (structure 'B'). Sampled at reset to choose boot memory. Additional function VPP. |
| A6 | VSS | power_in | Digital ground reference (0 V). Connect to system ground plane. |
| A7 | VDD | power_in | Digital supply rail, 1.7-3.6 V. Decouple with 100 nF close to each VDD pin plus one 4.7 uF bulk capacitor. |
| B1 | VSS | power_in | Digital ground reference (0 V). Connect to system ground plane. |
| B2 | VDD | power_in | Digital supply rail, 1.7-3.6 V. |
| B3 | PA13 | bidirectional | 5 V-tolerant GPIO. Alternate function default JTMS-SWDIO: SWD/JTAG data. Also EVENTOUT. |
| B4 | PB5 | bidirectional | 3.3 V (TC) GPIO. Muxed with TIM3_CH2, I2C1_SMBA, SPI1/3_MOSI/I2S1/3_SD, SDIO_D3, EVENTOUT. |
| B5 | PB8 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, I2C3_SDA, SDIO_D4, EVENTOUT. |
| B6 | PDR_ON | input | Power-down reset control (5 V-tolerant). Tie to VDD to enable the internal PDR; tie to VSS to disable it and use the external reset supervisor scheme. |
| B7 | VBAT | power_in | Backup domain supply, 1.65-3.6 V. Powers RTC, LSE oscillator and backup registers when VDD is off. Tie to VDD if backup domain is not battery-backed. |
| C1 | PA11 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM1_CH4, SPI4_MISO, USART1_CTS, USART6_TX, USB_FS_DM, EVENTOUT. |
| C2 | PA10 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX, USB_FS_ID, EVENTOUT. |
| C3 | PA12 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX, USB_FS_DP, EVENTOUT. |
| C4 | PB6 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM4_CH1, I2C1_SCL, USART1_TX, EVENTOUT. |
| C5 | PB9 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C2_SDA, SDIO_D5, EVENTOUT. |
| C6 | PC15-OSC32_OUT | bidirectional | LSE (32.768 kHz) crystal output when RTC uses the low-speed external oscillator; otherwise a limited-drive GPIO. FT structure, driven from backup domain switch (max 3 mA, max load 30 pF, 2 MHz). |
| C7 | PC14-OSC32_IN | bidirectional | LSE (32.768 kHz) crystal input when RTC uses the low-speed external oscillator; otherwise a limited-drive GPIO. FT structure but not 5 V tolerant in analog/oscillator mode. |
| D1 | PA8 | bidirectional | 5 V-tolerant GPIO. Muxed with MCO_1, TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF, SDIO_D1, EVENTOUT. |
| D2 | PA9 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS, SDIO_D2, EVENTOUT. Additional function OTG_FS_VBUS. |
| D3 | VSS | power_in | Digital ground reference (0 V). |
| D4 | PB7 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM4_CH2, I2C1_SDA, USART1_RX, SDIO_D0, EVENTOUT. |
| D5 | PC13-ANTI_TAMP | bidirectional | Backup-domain limited-drive GPIO. Additional functions RTC_AMP1 (tamper), RTC_OUT, RTC_TS. Supplied through backup switch: max 3 mA, 2 MHz, 30 pF load; do not drive LEDs. |
| D6 | PH1-OSC_OUT | bidirectional | HSE (4-26 MHz) crystal output when the high-speed external oscillator is used; otherwise a GPIO. FT structure but not 5 V tolerant in analog/oscillator mode. |
| D7 | PH0-OSC_IN | bidirectional | HSE (4-26 MHz) crystal input or external clock input when HSE is used; otherwise a GPIO. FT structure but not 5 V tolerant in analog/oscillator mode. |
| E1 | PB15 | bidirectional | 5 V-tolerant GPIO. Additional function RTC_REFIN. Alternate functions RTC_50Hz, TIM1_CH3N, SPI2_MOSI/I2S2_SD, SDIO_CK, EVENTOUT. |
| E2 | PB12 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, SPI3_SCK/I2S3_CK, EVENTOUT. |
| E3 | PB10 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, SDIO_D7, EVENTOUT. |
| E4 | PA3 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, EVENTOUT. Additional function ADC1_3. |
| E5 | PA2 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, EVENTOUT. Additional function ADC1_2. |
| E6 | VSSA/VREF- | power_in | Analog ground and ADC negative reference. Tie to VSS at a single star point. On WLCSP49 VREF- and VSSA share a single ball. |
| E7 | NRST | bidirectional | Bidirectional device reset input/output with embedded weak pull-up (~40 kOhm). Driven low by internal supervisor; also EVENTOUT. Add ~100 nF external filter capacitor. |
| F1 | PB14 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM1_CH2N, SPI2_MISO, I2S2ext_SD, SDIO_D6, EVENTOUT. |
| F2 | VDD | power_in | Digital supply rail, 1.7-3.6 V. |
| F3 | PA7 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SD, EVENTOUT. Additional function ADC1_7. |
| F4 | PA6 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM1_BKIN, TIM3_CH1, SPI1_MISO, I2S2_MCK, SDIO_CMD, EVENTOUT. Additional function ADC1_6. |
| F5 | PA5 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM2_CH1/TIM2_ETR, SPI1_SCK/I2S1_CK, EVENTOUT. Additional function ADC1_5. |
| F6 | PA0-WKUP | bidirectional | 3.3 V (TC) GPIO, also standby wakeup (WKUP1). Alternate functions TIM2_CH1/TIM2_ET, TIM5_CH1, USART2_CTS, EVENTOUT. Additional functions ADC1_0, WKUP1. |
| F7 | VDDA/VREF+ | power_in | Analog supply and positive ADC/temperature/reference-voltage reference, 1.8-3.6 V. On WLCSP49 VREF+ and VDDA share a single ball; decouple with 100 nF + 1 uF to VSSA. |
| G1 | PB13 | bidirectional | 5 V-tolerant GPIO. Muxed with TIM1_CH1N, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, EVENTOUT. |
| G2 | VCAP_1 | passive | Internal 1.2 V core regulator external stabilization capacitor pin. Connect a 2.2 uF low-ESR ceramic capacitor to VSS (see VCAP_1/VCAP_2 operating conditions). |
| G3 | PB2 | bidirectional | 5 V-tolerant GPIO. Additional function BOOT1: sampled with BOOT0 at reset to select the boot memory. Also EVENTOUT. |
| G4 | PB1 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM1_CH3N, TIM3_CH4, SPI5_NSS/I2S5_WS, EVENTOUT. Additional function ADC1_9. |
| G5 | PB0 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM1_CH2N, TIM3_CH3, SPI5_SCK/I2S5_CK, EVENTOUT. Additional function ADC1_8. |
| G6 | PA4 | bidirectional | 5 V-tolerant GPIO. Alternate functions SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT. Additional function ADC1_4. |
| G7 | PA1 | bidirectional | 5 V-tolerant GPIO. Alternate functions TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, EVENTOUT. Additional function ADC1_1. |
Key specifications
| Parameter | Value |
|---|---|
| Core | Arm Cortex-M4 |
| Max clock | 100 MHz |
| Flash | 512 kB |
| RAM | 128 kB |
| I/O pins | 36 |
| ADC units | 1 |
| Supply | 1.7 to 3.6 V |
| Temperature | -40 to 85 C |
| ST status | Active |
| Manufacturer | STMicroelectronics |
| Package | WLCSP-49(3x3.2) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Ordering variants
Same part, different packaging or reel option.
STM32F411CEY6TRYSTM32F411CEY6TRUSTM32F411CEY6TRRSTM32F411CEY6TRVSTM32F411CEY6TRH
CAD (KiCad official)
- Symbol:
STM32F411CEY6TR - Footprint:
Package_CSP:ST_WLCSP-49_Die431 - 3D model: WLCSP-49(3x3.2) (KiCad packages3D, STEP)
- 3D model files:
stm32f411cey6tr-etched.step/stm32f411cey6tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f411cey6tr.step/stm32f411cey6tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (55 pp, sha256
4ac2e31b207404a8, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).