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STM32F410C8U6TR

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFQFPN-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

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STM32F410C8U6TR

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFQFPN-48(7x7)

STM32F410C8U6TR from STMicroelectronics, in a UFQFPN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Power supply for the RTC, the external 32 kHz oscillator and the backup registers through the power switch when VDD is not present, 1.65 to 3.6 V.
2 PC13 bidirectional Supplied through the power switch, which sinks at most 3 mA, so it must not exceed 2 MHz at 30 pF max load or be used as a current source; alternates RTC_TAMP1, RTC_OUT, RTC_TS and EVENTOUT.
3 PC14-OSC32_IN bidirectional Power-switch supplied GPIO with the same 2 MHz / 30 pF and no current-source limits as PC13, 5 V tolerant except in oscillator mode, also used as OSC32_IN for the 32 kHz oscillator.
4 PC15-OSC32_OUT bidirectional Power-switch supplied GPIO with the same 2 MHz / 30 pF and no current-source limits as PC13, 5 V tolerant except in oscillator mode, also used as OSC32_OUT for the 32 kHz oscillator.
5 PH0-OSC_IN bidirectional 5 V tolerant I/O except in oscillator mode, used as the OSC_IN input of the external 4-26 MHz oscillator, with EVENTOUT as an alternate function.
6 PH1-OSC_OUT bidirectional 5 V tolerant I/O except in oscillator mode, used as the OSC_OUT output of the external 4-26 MHz oscillator, with EVENTOUT as an alternate function.
7 NRST bidirectional Reset pin with an embedded weak pull-up resistor.
8 VSSA/VREF- power_in Analog ground for the ADC, reset blocks, RC oscillators and PLL, to be connected to VSS with decoupling.
9 VDDA/VREF+ power_in Analog supply 1.7 to 3.6 V for the ADC, reset blocks, RC oscillators and PLL, to be connected to VDD with decoupling.
10 PA0 bidirectional 5 V tolerant I/O with alternate functions TIM5_CH1, USART2_CTS and EVENTOUT, and additional functions ADC1_0 and WKUP1.
11 PA1 bidirectional 5 V tolerant I/O with alternate functions TIM5_CH2, USART2_RTS and EVENTOUT, and additional function ADC1_1.
12 PA2 bidirectional 5 V tolerant I/O with alternate functions TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX and EVENTOUT, and additional function ADC1_2.
13 PA3 bidirectional 5 V tolerant I/O with alternate functions TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX and EVENTOUT, and additional function ADC1_3.
14 PA4 bidirectional 5 V tolerant I/O with alternate functions SPI1_NSS/I2S1_WS, USART2_CK and EVENTOUT, and additional function ADC1_4.
15 PA5 bidirectional Standard 3.3 V I/O (TC, not 5 V tolerant) with alternate functions SPI1_SCK/I2S1_CK and EVENTOUT, and additional functions ADC1_5 and DAC_OUT1.
16 PA6 bidirectional 5 V tolerant I/O with alternate functions TIM1_BKIN, SPI1_MISO, I2S2_MCK and EVENTOUT, and additional function ADC1_6.
17 PA7 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH1N, SPI1_MOSI/I2S1_SD and EVENTOUT, and additional function ADC1_7.
18 PB0 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH2N, SPI5_SCK/I2S5_CK and EVENTOUT, and additional function ADC1_8.
19 PB1 bidirectional Standard 3.3 V I/O (TC, not 5 V tolerant) with alternate functions TIM1_CH3N, SPI5_NSS/I2S5_WS and EVENTOUT, and additional function ADC1_9.
20 PB2 bidirectional 5 V tolerant I/O with alternate function LPTIM1_OUT and EVENTOUT, and BOOT1 as an additional function.
21 PB10 bidirectional 5 V tolerant I/O with alternate functions I2C2_SCL, SPI2_SCK/I2S2_CK, I2S1_MCK, I2C4_SCL and EVENTOUT.
22 VCAP_1 passive Connection to the internal voltage regulator that requires an external capacitor as specified in the VCAP_1 operating conditions (Table 17).
23 VSS power_in Ground.
24 VDD power_in Digital supply for the I/Os, 1.7 to 3.6 V.
25 PB12 bidirectional 5 V tolerant I/O with alternate functions TIM1_BKIN, TIM5_CH1, I2C2_SMBA, SPI2_NSS/I2S2_WS and EVENTOUT.
26 PB13 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH1N, I2C4_SMBA, SPI2_SCK/I2S2_CK and EVENTOUT.
27 PB14 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH2N, I2C4_SDA, SPI2_MISO and EVENTOUT.
28 PB15 bidirectional 5 V tolerant I/O with alternate functions RTC_50Hz, TIM1_CH3N, I2C4_SCL, SPI2_MOSI/I2S2_SD and EVENTOUT.
29 PA8 bidirectional 5 V tolerant I/O with alternate functions MCO_1, TIM1_CH1, I2C4_SCL, USART1_CK and EVENTOUT.
30 PA9 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH2, USART1_TX and EVENTOUT.
31 PA10 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX and EVENTOUT.
32 PA11 bidirectional 5 V tolerant I/O with alternate functions TIM1_CH4, USART1_CTS, USART6_TX and EVENTOUT.
33 PA12 bidirectional 5 V tolerant I/O with alternate functions TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX and EVENTOUT.
34 PA13 bidirectional 5 V tolerant I/O with alternate functions JTMS-SWDIO and EVENTOUT.
35 VSS power_in Ground.
36 VDD power_in Digital supply for the I/Os, 1.7 to 3.6 V.
37 PA14 bidirectional 5 V tolerant I/O with alternate functions JTCK-SWCLK and EVENTOUT.
38 PA15 bidirectional 5 V tolerant I/O with alternate functions JTDI, SPI1_NSS/I2S1_WS, USART1_TX and EVENTOUT.
39 PB3 bidirectional 5 V tolerant I/O with alternate functions JTDO-SWO, I2C4_SDA, SPI1_SCK/I2S1_CK, USART1_RX, I2C2_SDA and EVENTOUT.
40 PB4 bidirectional 5 V tolerant I/O with alternate functions JTRST, SPI1_MISO and EVENTOUT.
41 PB5 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI/I2S1_SD and EVENTOUT.
42 PB6 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_ETR, I2C1_SCL, USART1_TX and EVENTOUT.
43 PB7 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_IN2, I2C1_SDA, USART1_RX and EVENTOUT.
44 BOOT0 input Dedicated BOOT0 pin that is sampled at startup, together with BOOT1, to select boot from user Flash, system memory or embedded SRAM.
45 PB8 bidirectional 5 V tolerant I/O with alternate functions LPTIM1_OUT, I2C1_SCL, SPI5_MOSI/I2S5_SD and EVENTOUT.
46 PB9 bidirectional 5 V tolerant I/O with alternate functions TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C2_SDA and EVENTOUT.
47 VSS power_in Ground.
48 VDD power_in Digital supply for the I/Os, 1.7 to 3.6 V.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFQFPN-48(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: STM32F410C8U6TR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: UFQFPN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: stm32f410c8u6tr-etched.step / stm32f410c8u6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f410c8u6tr.step / stm32f410c8u6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (143 pp, sha256 8d6d318eb4b129f7, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF