component

STM32F407ZGT6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentmcustm32f407zgt6
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

STM32F407ZGT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

STM32F407ZGT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional General-purpose I/O port E bit 2 (5 V tolerant). Alt: TRACECLK / FSMC_A23 / ETH_MII_TXD3 / EVENTOUT.
2 PE3 bidirectional General-purpose I/O port E bit 3 (5 V tolerant). Alt: TRACED0 / FSMC_A19 / EVENTOUT.
3 PE4 bidirectional General-purpose I/O port E bit 4 (5 V tolerant). Alt: TRACED1 / FSMC_A20 / DCMI_D4 / EVENTOUT.
4 PE5 bidirectional General-purpose I/O port E bit 5 (5 V tolerant). Alt: TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT.
5 PE6 bidirectional General-purpose I/O port E bit 6 (5 V tolerant). Alt: TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT.
6 VBAT power_in Backup battery supply for RTC, external clock 32 kHz oscillator, and backup registers when VDD is off. Typical 1.65-3.6 V.
7 PC13 bidirectional General-purpose I/O port C bit 13, supplied through the power switch (limited to 3 mA sink, 2 MHz max, 30 pF max load). Alt: EVENTOUT / RTC_OUT / RTC_TAMP1 / RTC_TS.
8 PC14/OSC32_IN bidirectional GPIO PC14 or 32.768 kHz LSE oscillator input. Powered through the backup power switch (limited current).
9 PC15/OSC32_OUT bidirectional GPIO PC15 or 32.768 kHz LSE oscillator output. Powered through the backup power switch.
10 PF0 bidirectional General-purpose I/O port F bit 0 (5 V tolerant). Alt: FSMC_A0 / I2C2_SDA / EVENTOUT.
11 PF1 bidirectional General-purpose I/O port F bit 1 (5 V tolerant). Alt: FSMC_A1 / I2C2_SCL / EVENTOUT.
12 PF2 bidirectional General-purpose I/O port F bit 2 (5 V tolerant). Alt: FSMC_A2 / I2C2_SMBA / EVENTOUT.
13 PF3 bidirectional General-purpose I/O port F bit 3, 5V tolerant except in analog mode. Alt: FSMC_A3 / EVENTOUT. Add: ADC3_IN9.
14 PF4 bidirectional General-purpose I/O port F bit 4. Alt: FSMC_A4 / EVENTOUT. Add: ADC3_IN14.
15 PF5 bidirectional General-purpose I/O port F bit 5. Alt: FSMC_A5 / EVENTOUT. Add: ADC3_IN15.
16 VSS power_in Ground reference for digital core and I/Os.
17 VDD power_in Digital supply, 1.8-3.6 V. Decouple locally with 100 nF.
18 PF6 bidirectional General-purpose I/O port F bit 6. Alt: TIM10_CH1 / FSMC_NIORD / EVENTOUT. Add: ADC3_IN4.
19 PF7 bidirectional General-purpose I/O port F bit 7. Alt: TIM11_CH1 / FSMC_NREG / EVENTOUT. Add: ADC3_IN5.
20 PF8 bidirectional General-purpose I/O port F bit 8. Alt: TIM13_CH1 / FSMC_NIOWR / EVENTOUT. Add: ADC3_IN6.
21 PF9 bidirectional General-purpose I/O port F bit 9. Alt: TIM14_CH1 / FSMC_CD / EVENTOUT. Add: ADC3_IN7.
22 PF10 bidirectional General-purpose I/O port F bit 10. Alt: FSMC_INTR / EVENTOUT. Add: ADC3_IN8.
23 PH0/OSC_IN bidirectional GPIO PH0 or main HSE oscillator input (4-26 MHz crystal). Alt: EVENTOUT.
24 PH1/OSC_OUT bidirectional GPIO PH1 or main HSE oscillator output. Alt: EVENTOUT.
25 NRST bidirectional Bidirectional device reset input/open-drain output, active low. Internal pull-up (~40 kΩ). Recommend 100 nF cap to ground.
26 PC0 bidirectional General-purpose I/O port C bit 0. Alt: OTG_HS_ULPI_STP / EVENTOUT. Add: ADC123_IN10.
27 PC1 bidirectional General-purpose I/O port C bit 1. Alt: ETH_MDC / EVENTOUT. Add: ADC123_IN11.
28 PC2 bidirectional General-purpose I/O port C bit 2. Alt: SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 / I2S2ext_SD / EVENTOUT. Add: ADC123_IN12.
29 PC3 bidirectional General-purpose I/O port C bit 3. Alt: SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK / EVENTOUT. Add: ADC123_IN13.
30 VDD power_in Digital supply, 1.8-3.6 V. Decouple with 100 nF.
31 VSSA power_in Analog ground reference for the ADC/DAC and analog blocks. Tie to VSS via a single low-impedance point.
32 VREF+ power_in Positive reference for the ADC and DAC. Must be ≥ 1.8 V and ≤ VDDA. Decouple with 100 nF + 1 µF.
33 VDDA power_in Analog supply (1.8-3.6 V) for ADC/DAC/reset/PLL. Decouple with 100 nF + 1 µF near the pin.
34 PA0/WKUP bidirectional GPIO PA0 with wakeup capability from standby. Alt: USART2_CTS / UART4_TX / ETH_MII_CRS / TIM2_CH1_ETR / TIM5_CH1 / TIM8_ETR / EVENTOUT. Add: ADC123_IN0 / WKUP.
35 PA1 bidirectional GPIO PA1. Alt: USART2_RTS / UART4_RX / ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2 / EVENTOUT. Add: ADC123_IN1.
36 PA2 bidirectional GPIO PA2. Alt: USART2_TX / TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO / EVENTOUT. Add: ADC123_IN2.
37 PA3 bidirectional GPIO PA3. Alt: USART2_RX / TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL / EVENTOUT. Add: ADC123_IN3.
38 VSS power_in Digital ground reference.
39 VDD power_in Digital supply, 1.8-3.6 V.
40 PA4 bidirectional GPIO PA4 (TTa: 3.6 V tolerant analog/digital). Alt: SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF / I2S3_WS / EVENTOUT. Add: ADC12_IN4 / DAC_OUT1.
41 PA5 bidirectional GPIO PA5 (TTa). Alt: SPI1_SCK / OTG_HS_ULPI_CK / TIM2_CH1_ETR / TIM8_CH1N / EVENTOUT. Add: ADC12_IN5 / DAC_OUT2.
42 PA6 bidirectional GPIO PA6. Alt: SPI1_MISO / TIM8_BKIN / TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN / EVENTOUT. Add: ADC12_IN6.
43 PA7 bidirectional GPIO PA7. Alt: SPI1_MOSI / TIM8_CH1N / TIM14_CH1 / TIM3_CH2 / ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV / EVENTOUT. Add: ADC12_IN7.
44 PC4 bidirectional GPIO PC4. Alt: ETH_RMII_RX_D0 / ETH_MII_RX_D0 / EVENTOUT. Add: ADC12_IN14.
45 PC5 bidirectional GPIO PC5. Alt: ETH_RMII_RX_D1 / ETH_MII_RX_D1 / EVENTOUT. Add: ADC12_IN15.
46 PB0 bidirectional GPIO PB0. Alt: TIM3_CH3 / TIM8_CH2N / OTG_HS_ULPI_D1 / ETH_MII_RXD2 / TIM1_CH2N / EVENTOUT. Add: ADC12_IN8.
47 PB1 bidirectional GPIO PB1. Alt: TIM3_CH4 / TIM8_CH3N / OTG_HS_ULPI_D2 / ETH_MII_RXD3 / TIM1_CH3N / EVENTOUT. Add: ADC12_IN9.
48 PB2/BOOT1 bidirectional GPIO PB2 also serves as BOOT1 configuration input latched at reset. Alt: EVENTOUT.
49 PF11 bidirectional GPIO PF11. Alt: DCMI_D12 / EVENTOUT.
50 PF12 bidirectional GPIO PF12. Alt: FSMC_A6 / EVENTOUT.
51 VSS power_in Digital ground reference.
52 VDD power_in Digital supply, 1.8-3.6 V.
53 PF13 bidirectional GPIO PF13. Alt: FSMC_A7 / EVENTOUT.
54 PF14 bidirectional GPIO PF14. Alt: FSMC_A8 / EVENTOUT.
55 PF15 bidirectional GPIO PF15. Alt: FSMC_A9 / EVENTOUT.
56 PG0 bidirectional GPIO PG0. Alt: FSMC_A10 / EVENTOUT.
57 PG1 bidirectional GPIO PG1. Alt: FSMC_A11 / EVENTOUT.
58 PE7 bidirectional GPIO PE7. Alt: FSMC_D4 / TIM1_ETR / EVENTOUT.
59 PE8 bidirectional GPIO PE8. Alt: FSMC_D5 / TIM1_CH1N / EVENTOUT.
60 PE9 bidirectional GPIO PE9. Alt: FSMC_D6 / TIM1_CH1 / EVENTOUT.
61 VSS power_in Digital ground reference.
62 VDD power_in Digital supply, 1.8-3.6 V.
63 PE10 bidirectional GPIO PE10. Alt: FSMC_D7 / TIM1_CH2N / EVENTOUT.
64 PE11 bidirectional GPIO PE11. Alt: FSMC_D8 / TIM1_CH2 / EVENTOUT.
65 PE12 bidirectional GPIO PE12. Alt: FSMC_D9 / TIM1_CH3N / EVENTOUT.
66 PE13 bidirectional GPIO PE13. Alt: FSMC_D10 / TIM1_CH3 / EVENTOUT.
67 PE14 bidirectional GPIO PE14. Alt: FSMC_D11 / TIM1_CH4 / EVENTOUT.
68 PE15 bidirectional GPIO PE15. Alt: FSMC_D12 / TIM1_BKIN / EVENTOUT.
69 PB10 bidirectional GPIO PB10. Alt: SPI2_SCK / I2S2_CK / I2C2_SCL / USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3 / EVENTOUT.
70 PB11 bidirectional GPIO PB11. Alt: I2C2_SDA / USART3_RX / OTG_HS_ULPI_D4 / ETH_RMII_TX_EN / ETH_MII_TX_EN / TIM2_CH4 / EVENTOUT.
71 VCAP_1 power_out Regulated 1.2 V core supply output; requires an external 2.2 µF low-ESR ceramic capacitor to ground. Do not load externally.
72 VDD power_in Digital supply, 1.8-3.6 V.
73 PB12 bidirectional GPIO PB12. Alt: SPI2_NSS / I2S2_WS / I2C2_SMBA / USART3_CK / TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5 / ETH_RMII_TXD0 / ETH_MII_TXD0 / OTG_HS_ID / EVENTOUT.
74 PB13 bidirectional GPIO PB13. Alt: SPI2_SCK / I2S2_CK / USART3_CTS / TIM1_CH1N / CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1 / EVENTOUT. Add: OTG_HS_VBUS.
75 PB14 bidirectional GPIO PB14. Alt: SPI2_MISO / TIM1_CH2N / TIM12_CH1 / OTG_HS_DM / USART3_RTS / TIM8_CH2N / I2S2ext_SD / EVENTOUT.
76 PB15 bidirectional GPIO PB15. Alt: SPI2_MOSI / I2S2_SD / TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP / EVENTOUT. Add: RTC_REFIN.
77 PD8 bidirectional GPIO PD8. Alt: FSMC_D13 / USART3_TX / EVENTOUT.
78 PD9 bidirectional GPIO PD9. Alt: FSMC_D14 / USART3_RX / EVENTOUT.
79 PD10 bidirectional GPIO PD10. Alt: FSMC_D15 / USART3_CK / EVENTOUT.
80 PD11 bidirectional GPIO PD11. Alt: FSMC_CLE / FSMC_A16 / USART3_CTS / EVENTOUT.
81 PD12 bidirectional GPIO PD12. Alt: FSMC_ALE / FSMC_A17 / TIM4_CH1 / USART3_RTS / EVENTOUT.
82 PD13 bidirectional GPIO PD13. Alt: FSMC_A18 / TIM4_CH2 / EVENTOUT.
83 VSS power_in Digital ground reference.
84 VDD power_in Digital supply, 1.8-3.6 V.
85 PD14 bidirectional GPIO PD14. Alt: FSMC_D0 / TIM4_CH3 / EVENTOUT.
86 PD15 bidirectional GPIO PD15. Alt: FSMC_D1 / TIM4_CH4 / EVENTOUT.
87 PG2 bidirectional GPIO PG2. Alt: FSMC_A12 / EVENTOUT.
88 PG3 bidirectional GPIO PG3. Alt: FSMC_A13 / EVENTOUT.
89 PG4 bidirectional GPIO PG4. Alt: FSMC_A14 / EVENTOUT.
90 PG5 bidirectional GPIO PG5. Alt: FSMC_A15 / EVENTOUT.
91 PG6 bidirectional GPIO PG6. Alt: FSMC_INT2 / EVENTOUT.
92 PG7 bidirectional GPIO PG7. Alt: FSMC_INT3 / USART6_CK / EVENTOUT.
93 PG8 bidirectional GPIO PG8. Alt: USART6_RTS / ETH_PPS_OUT / EVENTOUT.
94 VSS power_in Digital ground reference.
95 VDD power_in Digital supply, 1.8-3.6 V.
96 PC6 bidirectional GPIO PC6. Alt: I2S2_MCK / TIM8_CH1 / SDIO_D6 / USART6_TX / DCMI_D0 / TIM3_CH1 / EVENTOUT.
97 PC7 bidirectional GPIO PC7. Alt: I2S3_MCK / TIM8_CH2 / SDIO_D7 / USART6_RX / DCMI_D1 / TIM3_CH2 / EVENTOUT.
98 PC8 bidirectional GPIO PC8. Alt: TIM8_CH3 / SDIO_D0 / TIM3_CH3 / USART6_CK / DCMI_D2 / EVENTOUT.
99 PC9 bidirectional GPIO PC9. Alt: I2S_CKIN / MCO2 / TIM8_CH4 / SDIO_D1 / I2C3_SDA / DCMI_D3 / TIM3_CH4 / EVENTOUT.
100 PA8 bidirectional GPIO PA8. Alt: MCO1 / USART1_CK / TIM1_CH1 / I2C3_SCL / OTG_FS_SOF / EVENTOUT.
101 PA9 bidirectional GPIO PA9. Alt: USART1_TX / TIM1_CH2 / I2C3_SMBA / DCMI_D0 / EVENTOUT. Add: OTG_FS_VBUS.
102 PA10 bidirectional GPIO PA10. Alt: USART1_RX / TIM1_CH3 / OTG_FS_ID / DCMI_D1 / EVENTOUT.
103 PA11 bidirectional GPIO PA11. Alt: USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM / EVENTOUT.
104 PA12 bidirectional GPIO PA12. Alt: USART1_RTS / CAN1_TX / TIM1_ETR / OTG_FS_DP / EVENTOUT.
105 PA13 bidirectional GPIO PA13, JTMS/SWDIO after reset. Alt: JTMS-SWDIO / EVENTOUT.
106 VCAP_2 power_out Regulated 1.2 V core supply output; requires an external 2.2 µF low-ESR ceramic capacitor to ground (paired with VCAP_1).
107 VSS power_in Digital ground reference.
108 VDD power_in Digital supply, 1.8-3.6 V.
109 PA14 bidirectional GPIO PA14, JTCK/SWCLK after reset. Alt: JTCK-SWCLK / EVENTOUT.
110 PA15 bidirectional GPIO PA15, JTDI after reset. Alt: JTDI / SPI3_NSS / I2S3_WS / TIM2_CH1_ETR / SPI1_NSS / EVENTOUT.
111 PC10 bidirectional GPIO PC10. Alt: SPI3_SCK / I2S3_CK / UART4_TX / SDIO_D2 / DCMI_D8 / USART3_TX / EVENTOUT.
112 PC11 bidirectional GPIO PC11. Alt: UART4_RX / SPI3_MISO / SDIO_D3 / DCMI_D4 / USART3_RX / I2S3ext_SD / EVENTOUT.
113 PC12 bidirectional GPIO PC12. Alt: UART5_TX / SDIO_CK / DCMI_D9 / SPI3_MOSI / I2S3_SD / USART3_CK / EVENTOUT.
114 PD0 bidirectional GPIO PD0. Alt: FSMC_D2 / CAN1_RX / EVENTOUT.
115 PD1 bidirectional GPIO PD1. Alt: FSMC_D3 / CAN1_TX / EVENTOUT.
116 PD2 bidirectional GPIO PD2. Alt: TIM3_ETR / UART5_RX / SDIO_CMD / DCMI_D11 / EVENTOUT.
117 PD3 bidirectional GPIO PD3. Alt: FSMC_CLK / USART2_CTS / EVENTOUT.
118 PD4 bidirectional GPIO PD4. Alt: FSMC_NOE / USART2_RTS / EVENTOUT.
119 PD5 bidirectional GPIO PD5. Alt: FSMC_NWE / USART2_TX / EVENTOUT.
120 VSS power_in Digital ground reference.
121 VDD power_in Digital supply, 1.8-3.6 V.
122 PD6 bidirectional GPIO PD6. Alt: FSMC_NWAIT / USART2_RX / EVENTOUT.
123 PD7 bidirectional GPIO PD7. Alt: USART2_CK / FSMC_NE1 / FSMC_NCE2 / EVENTOUT.
124 PG9 bidirectional GPIO PG9. Alt: USART6_RX / FSMC_NE2 / FSMC_NCE3 / EVENTOUT.
125 PG10 bidirectional GPIO PG10. Alt: FSMC_NCE4_1 / FSMC_NE3 / EVENTOUT.
126 PG11 bidirectional GPIO PG11. Alt: FSMC_NCE4_2 / ETH_MII_TX_EN / ETH_RMII_TX_EN / EVENTOUT.
127 PG12 bidirectional GPIO PG12. Alt: FSMC_NE4 / USART6_RTS / EVENTOUT.
128 PG13 bidirectional GPIO PG13. Alt: FSMC_A24 / USART6_CTS / ETH_MII_TXD0 / ETH_RMII_TXD0 / EVENTOUT.
129 PG14 bidirectional GPIO PG14. Alt: FSMC_A25 / USART6_TX / ETH_MII_TXD1 / ETH_RMII_TXD1 / EVENTOUT.
130 VSS power_in Digital ground reference.
131 VDD power_in Digital supply, 1.8-3.6 V.
132 PG15 bidirectional GPIO PG15. Alt: USART6_CTS / DCMI_D13 / EVENTOUT.
133 PB3 bidirectional GPIO PB3, JTDO/TRACESWO after reset. Alt: JTDO / TRACESWO / SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK / EVENTOUT.
134 PB4 bidirectional GPIO PB4, NJTRST after reset. Alt: NJTRST / SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD / EVENTOUT.
135 PB5 bidirectional GPIO PB5. Alt: I2C1_SMBA / CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT / TIM3_CH2 / SPI1_MOSI / SPI3_MOSI / DCMI_D10 / I2S3_SD / EVENTOUT.
136 PB6 bidirectional GPIO PB6. Alt: I2C1_SCL / TIM4_CH1 / CAN2_TX / DCMI_D5 / USART1_TX / EVENTOUT.
137 PB7 bidirectional GPIO PB7. Alt: I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX / TIM4_CH2 / EVENTOUT.
138 BOOT0 input Boot memory selection input latched at reset (with PB2/BOOT1). Also serves as VPP for factory Flash programming. Must be tied to a defined level (typically GND for boot from Main Flash).
139 PB8 bidirectional GPIO PB8. Alt: TIM4_CH3 / SDIO_D4 / TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL / CAN1_RX / EVENTOUT.
140 PB9 bidirectional GPIO PB9. Alt: SPI2_NSS / I2S2_WS / TIM4_CH4 / TIM11_CH1 / SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX / EVENTOUT.
141 PE0 bidirectional GPIO PE0. Alt: TIM4_ETR / FSMC_NBL0 / DCMI_D2 / EVENTOUT.
142 PE1 bidirectional GPIO PE1. Alt: FSMC_NBL1 / DCMI_D3 / EVENTOUT.
143 PDR_ON input Power Down Reset ON: selects internal Power-Down Reset behavior. Table 7 in this datasheet revision lists LQFP144 pin 143 as PDR_ON; later STM32F407 datasheet revisions list this pin as VSS on LQFP144. Verify against the ordering-code-specific device marking/datasheet before layout.
144 VDD power_in Digital supply, 1.8-3.6 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category MCU
Pins 144

Ordering variants

Same part, different packaging or reel option.

  • STM32F407ZGT6
  • STM32F407ZGT6ZET6
  • STM32F407ZGT6RGT6
  • STM32F407ZGT6VGT6
  • STM32F407ZGT6VET6
  • STM32F407ZGT6IGT6
  • STM32F407ZGT6IET6
  • STM32F407ZGT6IGH6
  • STM32F407ZGT6IEH6
  • STM32F407ZGT6VGY6

CAD (KiCad official)

  • Symbol: STM32F407ZGT6
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: stm32f407zgt6-etched.step / stm32f407zgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f407zgt6.step / stm32f407zgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 f83f1f3dca0b4e10, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF