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STM32F407VET6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F407VET6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
STM32F407VET6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5V-tolerant fast I/O, floating input after reset; AF: TRACECLK/FSMC_A23/ETH_MII_TXD3/EVENTOUT. |
| 2 | PE3 | bidirectional | 5V-tolerant fast I/O, floating input after reset; AF: TRACED0/FSMC_A19/EVENTOUT. |
| 3 | PE4 | bidirectional | 5V-tolerant fast I/O, floating input after reset; AF: TRACED1/FSMC_A20/DCMI_D4/EVENTOUT. |
| 4 | PE5 | bidirectional | 5V-tolerant fast I/O, floating input after reset; AF: TRACED2/FSMC_A21/TIM9_CH1/DCMI_D6/EVENTOUT. |
| 5 | PE6 | bidirectional | 5V-tolerant fast I/O, floating input after reset; AF: TRACED3/FSMC_A22/TIM9_CH2/DCMI_D7/EVENTOUT. |
| 6 | VBAT | power_in | Battery voltage supply for RTC, 20x32-bit backup registers and (when present) backup SRAM when VDD is not present. |
| 7 | PC13 | bidirectional | 5V-tolerant I/O supplied through the power switch (limited to 3 mA sink, output speed <=2 MHz, max load 30 pF, not usable as current source); AF: EVENTOUT; additional functions RTC_OUT, RTC_TAMP1, RTC_TS. |
| 8 | PC14 | bidirectional | 5V-tolerant I/O supplied through the power switch (same 3 mA/2 MHz/30 pF limits as PC13); AF: EVENTOUT; additional function OSC32_IN (32.768 kHz oscillator input) when used as LSE. |
| 9 | PC15 | bidirectional | 5V-tolerant I/O supplied through the power switch (same 3 mA/2 MHz/30 pF limits as PC13); AF: EVENTOUT; additional function OSC32_OUT (32.768 kHz oscillator output) when used as LSE. |
| 10 | VSS | power_in | Digital ground supply pin. |
| 11 | VDD | power_in | Digital power supply pin, 1.8 V to 3.6 V. |
| 12 | PH0 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: EVENTOUT; additional function OSC_IN (4-26 MHz external crystal/resonator input). |
| 13 | PH1 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: EVENTOUT; additional function OSC_OUT (4-26 MHz external crystal/resonator output). |
| 14 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor; active-low system reset input/output. |
| 15 | PC0 | bidirectional | 5V-tolerant I/O (analog mode 3.3V tolerant), floating input after reset; additional function ADC123_IN10; AF: OTG_HS_ULPI_STP/EVENTOUT. |
| 16 | PC1 | bidirectional | 5V-tolerant I/O (analog mode 3.3V tolerant), floating input after reset; additional function ADC123_IN11; AF: ETH_MDC/EVENTOUT. |
| 17 | PC2 | bidirectional | 5V-tolerant I/O (analog mode 3.3V tolerant), floating input after reset; additional function ADC123_IN12; AF: SPI2_MISO/OTG_HS_ULPI_DIR/ETH_MII_TXD2/I2S2ext_SD/EVENTOUT. |
| 18 | PC3 | bidirectional | 5V-tolerant I/O (analog mode 3.3V tolerant), floating input after reset; additional function ADC123_IN13; AF: SPI2_MOSI/I2S2_SD/OTG_HS_ULPI_NXT/ETH_MII_TX_CLK/EVENTOUT. |
| 19 | VDD | power_in | Digital power supply pin, 1.8 V to 3.6 V. |
| 20 | VSSA | power_in | Analog ground supply pin for ADC, DAC, reset block, RC oscillators and PLL. |
| 21 | VREF+ | power_in | Positive analog reference voltage for ADC/DAC, must be between minimum VREF+ and VDDA. |
| 22 | VDDA | power_in | Analog power supply pin for ADC, DAC, reset block, RC oscillators and PLL (1.8 V to 3.6 V). |
| 23 | PA0 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC123_IN0/WKUP (wakeup from standby); AF: USART2_CTS/UART4_TX/ETH_MII_CRS/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/EVENTOUT. |
| 24 | PA1 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC123_IN1; AF: USART2_RTS/UART4_RX/ETH_RMII_REF_CLK/ETH_MII_RX_CLK/TIM5_CH2/TIM2_CH2/EVENTOUT. |
| 25 | PA2 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC123_IN2; AF: USART2_TX/TIM5_CH3/TIM9_CH1/TIM2_CH3/ETH_MDIO/EVENTOUT. |
| 26 | PA3 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC123_IN3; AF: USART2_RX/TIM5_CH4/TIM9_CH2/TIM2_CH4/OTG_HS_ULPI_D0/ETH_MII_COL/EVENTOUT. |
| 27 | VSS | power_in | Digital ground supply pin. |
| 28 | VDD | power_in | Digital power supply pin, 1.8 V to 3.6 V. |
| 29 | PA4 | bidirectional | 3.3V-tolerant I/O directly connected to ADC (TTa), floating input after reset; additional function ADC12_IN4/DAC_OUT1; AF: SPI1_NSS/SPI3_NSS/USART2_CK/DCMI_HSYNC/OTG_HS_SOF/I2S3_WS/EVENTOUT. |
| 30 | PA5 | bidirectional | 3.3V-tolerant I/O directly connected to ADC (TTa), floating input after reset; additional function ADC12_IN5/DAC_OUT2; AF: SPI1_SCK/OTG_HS_ULPI_CK/TIM2_CH1_ETR/TIM8_CH1N/EVENTOUT. |
| 31 | PA6 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC12_IN6; AF: SPI1_MISO/TIM8_BKIN/TIM13_CH1/DCMI_PIXCLK/TIM3_CH1/TIM1_BKIN/EVENTOUT. |
| 32 | PA7 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC12_IN7; AF: SPI1_MOSI/TIM8_CH1N/TIM14_CH1/TIM3_CH2/ETH_MII_RX_DV/TIM1_CH1N/ETH_RMII_CRS_DV/EVENTOUT. |
| 33 | PC4 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC12_IN14; AF: ETH_RMII_RX_D0/ETH_MII_RX_D0/EVENTOUT. |
| 34 | PC5 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC12_IN15; AF: ETH_RMII_RX_D1/ETH_MII_RX_D1/EVENTOUT. |
| 35 | PB0 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC12_IN8; AF: TIM3_CH3/TIM8_CH2N/OTG_HS_ULPI_D1/ETH_MII_RXD2/TIM1_CH2N/EVENTOUT. |
| 36 | PB1 | bidirectional | 5V-tolerant I/O, floating input after reset; additional function ADC12_IN9; AF: TIM3_CH4/TIM8_CH3N/OTG_HS_ULPI_D2/ETH_MII_RXD3/TIM1_CH3N/EVENTOUT. |
| 37 | PB2 | bidirectional | 5V-tolerant I/O also used as BOOT1 pin sampled at reset to select boot mode; AF: EVENTOUT. |
| 38 | PE7 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D4/TIM1_ETR/EVENTOUT. |
| 39 | PE8 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D5/TIM1_CH1N/EVENTOUT. |
| 40 | PE9 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D6/TIM1_CH1/EVENTOUT. |
| 41 | PE10 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D7/TIM1_CH2N/EVENTOUT. |
| 42 | PE11 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D8/TIM1_CH2/EVENTOUT. |
| 43 | PE12 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D9/TIM1_CH3N/EVENTOUT. |
| 44 | PE13 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D10/TIM1_CH3/EVENTOUT. |
| 45 | PE14 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D11/TIM1_CH4/EVENTOUT. |
| 46 | PE15 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D12/TIM1_BKIN/EVENTOUT. |
| 47 | PB10 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: SPI2_SCK/I2S2_CK/I2C2_SCL/USART3_TX/OTG_HS_ULPI_D3/ETH_MII_RX_ER/TIM2_CH3/EVENTOUT. |
| 48 | PB11 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: I2C2_SDA/USART3_RX/OTG_HS_ULPI_D4/ETH_RMII_TX_EN/ETH_MII_TX_EN/TIM2_CH4/EVENTOUT. |
| 49 | VCAP_1 | power_out | Voltage regulator output for internal 1.2V core supply; requires external decoupling capacitor per VCAP operating conditions. |
| 50 | VDD | power_in | Digital power supply pin, 1.8 V to 3.6 V. |
| 51 | PB12 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN/CAN2_RX/OTG_HS_ULPI_D5/ETH_RMII_TXD0/ETH_MII_TXD0/OTG_HS_ID/EVENTOUT. |
| 52 | PB13 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N/CAN2_TX/OTG_HS_ULPI_D6/ETH_RMII_TXD1/ETH_MII_TXD1/EVENTOUT; additional function OTG_HS_VBUS. |
| 53 | PB14 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: SPI2_MISO/TIM1_CH2N/TIM12_CH1/OTG_HS_DM/USART3_RTS/TIM8_CH2N/I2S2ext_SD/EVENTOUT. |
| 54 | PB15 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: SPI2_MOSI/I2S2_SD/TIM1_CH3N/TIM8_CH3N/TIM12_CH2/OTG_HS_DP/EVENTOUT; additional function RTC_REFIN. |
| 55 | PD8 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D13/USART3_TX/EVENTOUT. |
| 56 | PD9 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D14/USART3_RX/EVENTOUT. |
| 57 | PD10 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D15/USART3_CK/EVENTOUT. |
| 58 | PD11 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_CLE/FSMC_A16/USART3_CTS/EVENTOUT. |
| 59 | PD12 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_ALE/FSMC_A17/TIM4_CH1/USART3_RTS/EVENTOUT. |
| 60 | PD13 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_A18/TIM4_CH2/EVENTOUT. |
| 61 | PD14 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D0/TIM4_CH3/EVENTOUT. |
| 62 | PD15 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D1/TIM4_CH4/EVENTOUT. |
| 63 | PC6 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: I2S2_MCK/TIM8_CH1/SDIO_D6/USART6_TX/DCMI_D0/TIM3_CH1/EVENTOUT. |
| 64 | PC7 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: I2S3_MCK/TIM8_CH2/SDIO_D7/USART6_RX/DCMI_D1/TIM3_CH2/EVENTOUT. |
| 65 | PC8 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: TIM8_CH3/SDIO_D0/TIM3_CH3/USART6_CK/DCMI_D2/EVENTOUT. |
| 66 | PC9 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: I2S_CKIN/MCO2/TIM8_CH4/SDIO_D1/I2C3_SDA/DCMI_D3/TIM3_CH4/EVENTOUT. |
| 67 | PA8 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: MCO1/USART1_CK/TIM1_CH1/I2C3_SCL/OTG_FS_SOF/EVENTOUT. |
| 68 | PA9 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: USART1_TX/TIM1_CH2/I2C3_SMBA/DCMI_D0/EVENTOUT; additional function OTG_FS_VBUS. |
| 69 | PA10 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: USART1_RX/TIM1_CH3/OTG_FS_ID/DCMI_D1/EVENTOUT. |
| 70 | PA11 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: USART1_CTS/CAN1_RX/TIM1_CH4/OTG_FS_DM/EVENTOUT. |
| 71 | PA12 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: USART1_RTS/CAN1_TX/TIM1_ETR/OTG_FS_DP/EVENTOUT. |
| 72 | PA13 | bidirectional | 5V-tolerant I/O, JTMS-SWDIO after reset (JTAG/SW debug); AF: JTMS-SWDIO/EVENTOUT. |
| 73 | VCAP_2 | power_out | Voltage regulator output for internal 1.2V core supply; requires external decoupling capacitor per VCAP operating conditions. |
| 74 | VSS | power_in | Digital ground supply pin. |
| 75 | VDD | power_in | Digital power supply pin, 1.8 V to 3.6 V. |
| 76 | PA14 | bidirectional | 5V-tolerant I/O, JTCK-SWCLK after reset (JTAG/SW debug clock); AF: JTCK-SWCLK/EVENTOUT. |
| 77 | PA15 | bidirectional | 5V-tolerant I/O, JTDI after reset; AF: JTDI/SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS/EVENTOUT. |
| 78 | PC10 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: SPI3_SCK/I2S3_CK/UART4_TX/SDIO_D2/DCMI_D8/USART3_TX/EVENTOUT. |
| 79 | PC11 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: UART4_RX/SPI3_MISO/SDIO_D3/DCMI_D4/USART3_RX/I2S3ext_SD/EVENTOUT. |
| 80 | PC12 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: UART5_TX/SDIO_CK/DCMI_D9/SPI3_MOSI/I2S3_SD/USART3_CK/EVENTOUT. |
| 81 | PD0 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D2/CAN1_RX/EVENTOUT. |
| 82 | PD1 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_D3/CAN1_TX/EVENTOUT. |
| 83 | PD2 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: TIM3_ETR/UART5_RX/SDIO_CMD/DCMI_D11/EVENTOUT. |
| 84 | PD3 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_CLK/USART2_CTS/EVENTOUT. |
| 85 | PD4 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_NOE/USART2_RTS/EVENTOUT. |
| 86 | PD5 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_NWE/USART2_TX/EVENTOUT. |
| 87 | PD6 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_NWAIT/USART2_RX/EVENTOUT. |
| 88 | PD7 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: USART2_CK/FSMC_NE1/FSMC_NCE2/EVENTOUT. |
| 89 | PB3 | bidirectional | 5V-tolerant I/O, JTDO/TRACESWO after reset; AF: JTDO/TRACESWO/SPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/EVENTOUT. |
| 90 | PB4 | bidirectional | 5V-tolerant I/O, NJTRST after reset; AF: NJTRST/SPI3_MISO/TIM3_CH1/SPI1_MISO/I2S3ext_SD/EVENTOUT. |
| 91 | PB5 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: I2C1_SMBA/CAN2_RX/OTG_HS_ULPI_D7/ETH_PPS_OUT/TIM3_CH2/SPI1_MOSI/SPI3_MOSI/DCMI_D10/I2S3_SD/EVENTOUT. |
| 92 | PB6 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: I2C1_SCL/TIM4_CH1/CAN2_TX/DCMI_D5/USART1_TX/EVENTOUT. |
| 93 | PB7 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: I2C1_SDA/FSMC_NL/DCMI_VSYNC/USART1_RX/TIM4_CH2/EVENTOUT. |
| 94 | BOOT0 | input | Dedicated boot mode select pin sampled at reset to choose boot from Flash, system memory or SRAM; additional function VPP. |
| 95 | PB8 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: TIM4_CH3/SDIO_D4/TIM10_CH1/DCMI_D6/ETH_MII_TXD3/I2C1_SCL/CAN1_RX/EVENTOUT. |
| 96 | PB9 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: SPI2_NSS/I2S2_WS/TIM4_CH4/TIM11_CH1/SDIO_D5/DCMI_D7/I2C1_SDA/CAN1_TX/EVENTOUT. |
| 97 | PE0 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: TIM4_ETR/FSMC_NBL0/DCMI_D2/EVENTOUT. |
| 98 | PE1 | bidirectional | 5V-tolerant I/O, floating input after reset; AF: FSMC_NBL1/DCMI_D3/EVENTOUT. |
| 99 | VSS | power_in | Digital ground supply pin. |
| 100 | VDD | power_in | Digital power supply pin, 1.8 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
STM32F407VET6 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32f407vet6-etched.step/stm32f407vet6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f407vet6.step/stm32f407vet6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (185 pp, sha256
f83f1f3dca0b4e10, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).