# STM32F407IGH6TR

**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · UFBGA-201(10x10)

STM32F407IGH6TR from STMicroelectronics, in a UFBGA-201(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | PE3 | bidirectional | Port E bit 3 I/O, 5 V tolerant (FT); alternate functions TRACED0, FSMC_A19 and EVENTOUT. |
| A2 | PE2 | bidirectional | Port E bit 2 I/O, 5 V tolerant (FT); alternate functions TRACECLK, FSMC_A23, ETH_MII_TXD3 and EVENTOUT. |
| A3 | PE1 | bidirectional | Port E bit 1 I/O, 5 V tolerant (FT); alternate functions FSMC_NBL1, DCMI_D3 and EVENTOUT. |
| A4 | PE0 | bidirectional | Port E bit 0 I/O, 5 V tolerant (FT); alternate functions TIM4_ETR, FSMC_NBL0, DCMI_D2 and EVENTOUT. |
| A5 | PB8 | bidirectional | Port B bit 8 I/O, 5 V tolerant (FT); alternate functions TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDIO_D4, DCMI_D6 and EVENTOUT. |
| A6 | PB5 | bidirectional | Port B bit 5 I/O, 5 V tolerant (FT); alternate functions I2C1_SMBA, CAN2_RX, SPI1_MOSI, SPI3_MOSI, DCMI_D10 and EVENTOUT. |
| A7 | PG14 | bidirectional | Port G bit 14 I/O, 5 V tolerant (FT); alternate functions FSMC_A25, USART6_TX, ETH_MII_TXD1, ETH_RMII_TXD1 and EVENTOUT. |
| A8 | PG13 | bidirectional | Port G bit 13 I/O, 5 V tolerant (FT); alternate functions FSMC_A24, USART6_CTS, ETH_MII_TXD0, ETH_RMII_TXD0 and EVENTOUT. |
| A9 | PB4 | bidirectional | Port B bit 4 I/O, 5 V tolerant (FT); default function NJTRST, alternate functions SPI3_MISO, TIM3_CH1, SPI1_MISO, I2S3ext_SD and EVENTOUT. |
| A10 | PB3 | bidirectional | Port B bit 3 I/O, 5 V tolerant (FT); default function JTDO/TRACESWO, alternate functions SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK and EVENTOUT. |
| A11 | PD7 | bidirectional | Port D bit 7 I/O, 5 V tolerant (FT); alternate functions USART2_CK, FSMC_NE1/FSMC_NCE2 and EVENTOUT. |
| A12 | PC12 | bidirectional | Port C bit 12 I/O, 5 V tolerant (FT); alternate functions UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI/I2S3_SD, USART3_CK and EVENTOUT. |
| A13 | PA15 | bidirectional | Port A bit 15 I/O, 5 V tolerant (FT); default function JTDI, alternate functions SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, SPI1_NSS and EVENTOUT. |
| A14 | PA14 | bidirectional | Port A bit 14 I/O, 5 V tolerant (FT); default function JTCK-SWCLK (SWD clock) and EVENTOUT alternate function. |
| A15 | PA13 | bidirectional | Port A bit 13 I/O, 5 V tolerant (FT); default function JTMS-SWDIO (SWD data) and EVENTOUT alternate function. |
| B1 | PE4 | bidirectional | Port E bit 4 I/O, 5 V tolerant (FT); alternate functions TRACED1, FSMC_A20, DCMI_D4 and EVENTOUT. |
| B2 | PE5 | bidirectional | Port E bit 5 I/O, 5 V tolerant (FT); alternate functions TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6 and EVENTOUT. |
| B3 | PE6 | bidirectional | Port E bit 6 I/O, 5 V tolerant (FT); alternate functions TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7 and EVENTOUT. |
| B4 | PB9 | bidirectional | Port B bit 9 I/O, 5 V tolerant (FT); alternate functions SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, I2C1_SDA, SDIO_D5, DCMI_D7, CAN1_TX and EVENTOUT. |
| B5 | PB7 | bidirectional | Port B bit 7 I/O, 5 V tolerant (FT); alternate functions I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX, TIM4_CH2 and EVENTOUT. |
| B6 | PB6 | bidirectional | Port B bit 6 I/O, 5 V tolerant (FT); alternate functions I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5, USART1_TX and EVENTOUT. |
| B7 | PG15 | bidirectional | Port G bit 15 I/O, 5 V tolerant (FT); alternate functions USART6_CTS, DCMI_D13 and EVENTOUT. |
| B8 | PG12 | bidirectional | Port G bit 12 I/O, 5 V tolerant (FT); alternate functions FSMC_NE4, USART6_RTS and EVENTOUT. |
| B9 | PG11 | bidirectional | Port G bit 11 I/O, 5 V tolerant (FT); alternate functions FSMC_NCE4_2, ETH_MII_TX_EN, ETH_RMII_TX_EN and EVENTOUT. |
| B10 | PG10 | bidirectional | Port G bit 10 I/O, 5 V tolerant (FT); alternate functions FSMC_NCE4_1, FSMC_NE3 and EVENTOUT. |
| B11 | PD6 | bidirectional | Port D bit 6 I/O, 5 V tolerant (FT); alternate functions FSMC_NWAIT, USART2_RX and EVENTOUT. |
| B12 | PD0 | bidirectional | Port D bit 0 I/O, 5 V tolerant (FT); alternate functions FSMC_D2, CAN1_RX and EVENTOUT. |
| B13 | PC11 | bidirectional | Port C bit 11 I/O, 5 V tolerant (FT); alternate functions UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX, I2S3ext_SD and EVENTOUT. |
| B14 | PC10 | bidirectional | Port C bit 10 I/O, 5 V tolerant (FT); alternate functions SPI3_SCK/I2S3_CK, UART4_TX, USART3_TX, SDIO_D2, DCMI_D8 and EVENTOUT. |
| B15 | PA12 | bidirectional | Port A bit 12 I/O, 5 V tolerant (FT); alternate functions USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP and EVENTOUT. |
| C1 | VBAT | power_in | Backup power supply for the RTC, the 20x32-bit backup registers and the optional 4 KB backup SRAM. |
| C2 | PI7 | bidirectional | Port I bit 7 I/O, 5 V tolerant (FT); alternate functions TIM8_CH3, DCMI_D7 and EVENTOUT. |
| C3 | PI6 | bidirectional | Port I bit 6 I/O, 5 V tolerant (FT); alternate functions TIM8_CH2, DCMI_D6 and EVENTOUT. |
| C4 | PI5 | bidirectional | Port I bit 5 I/O, 5 V tolerant (FT); alternate functions TIM8_CH1, DCMI_VSYNC and EVENTOUT. |
| C5 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| C6 | PDR_ON | input | Power-down reset control input (FT, 5 V tolerant) used in the internal reset OFF configurations. |
| C7 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| C8 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| C9 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| C10 | PG9 | bidirectional | Port G bit 9 I/O, 5 V tolerant (FT); alternate functions USART6_RX, FSMC_NE2/FSMC_NCE3 and EVENTOUT. |
| C11 | PD5 | bidirectional | Port D bit 5 I/O, 5 V tolerant (FT); alternate functions FSMC_NWE, USART2_TX and EVENTOUT. |
| C12 | PD1 | bidirectional | Port D bit 1 I/O, 5 V tolerant (FT); alternate functions FSMC_D3, CAN1_TX and EVENTOUT. |
| C13 | PI3 | bidirectional | Port I bit 3 I/O, 5 V tolerant (FT); alternate functions TIM8_ETR, SPI2_MOSI, I2S2_SD, DCMI_D10 and EVENTOUT. |
| C14 | PI2 | bidirectional | Port I bit 2 I/O, 5 V tolerant (FT); alternate functions TIM8_CH4, SPI2_MISO, I2S2ext_SD, DCMI_D9 and EVENTOUT. |
| C15 | PA11 | bidirectional | Port A bit 11 I/O, 5 V tolerant (FT); alternate functions USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM and EVENTOUT. |
| D1 | PC13 | bidirectional | Port C bit 13 I/O supplied through the power switch (3 mA sink limit), so output use is limited to 2 MHz at 30 pF and it must not source current; alternate functions RTC_OUT, RTC_TAMP1, RTC_TS and EVENTOUT. |
| D2 | PI8 | bidirectional | Port I bit 8 I/O supplied through the power switch (3 mA sink limit), so output use is limited to 2 MHz at 30 pF; alternate functions RTC_TAMP1, RTC_TAMP2, RTC_TS and EVENTOUT. |
| D3 | PI9 | bidirectional | Port I bit 9 I/O, 5 V tolerant (FT); alternate functions CAN1_RX and EVENTOUT. |
| D4 | PI4 | bidirectional | Port I bit 4 I/O, 5 V tolerant (FT); alternate functions TIM8_BKIN, DCMI_D5 and EVENTOUT. |
| D5 | VSS | power_in | Ground (VSS) supply pin. |
| D6 | BOOT0 | input | Dedicated BOOT0 pin that selects the boot mode and also serves as VPP for Flash programming. |
| D7 | VSS | power_in | Ground (VSS) supply pin. |
| D8 | VSS | power_in | Ground (VSS) supply pin. |
| D9 | VSS | power_in | Ground (VSS) supply pin. |
| D10 | PD4 | bidirectional | Port D bit 4 I/O, 5 V tolerant (FT); alternate functions FSMC_NOE, USART2_RTS and EVENTOUT. |
| D11 | PD3 | bidirectional | Port D bit 3 I/O, 5 V tolerant (FT); alternate functions FSMC_CLK, USART2_CTS and EVENTOUT. |
| D12 | PD2 | bidirectional | Port D bit 2 I/O, 5 V tolerant (FT); alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11 and EVENTOUT. |
| D13 | PH15 | bidirectional | Port H bit 15 I/O, 5 V tolerant (FT); alternate functions TIM8_CH3N, DCMI_D11 and EVENTOUT. |
| D14 | PI1 | bidirectional | Port I bit 1 I/O, 5 V tolerant (FT); alternate functions SPI2_SCK, I2S2_CK, DCMI_D8 and EVENTOUT. |
| D15 | PA10 | bidirectional | Port A bit 10 I/O, 5 V tolerant (FT); alternate functions USART1_RX, TIM1_CH3, OTG_FS_ID, DCMI_D1 and EVENTOUT. |
| E1 | PC14/OSC32_IN | bidirectional | Port C bit 14 I/O supplied through the power switch (3 mA sink limit); it is the OSC32_IN 32 kHz oscillator input when the LSE oscillator is used. |
| E2 | PF0 | bidirectional | Port F bit 0 I/O, 5 V tolerant (FT); alternate functions FSMC_A0, I2C2_SDA and EVENTOUT. |
| E3 | PI10 | bidirectional | Port I bit 10 I/O, 5 V tolerant (FT); alternate functions ETH_MII_RX_ER and EVENTOUT. |
| E4 | PI11 | bidirectional | Port I bit 11 I/O, 5 V tolerant (FT); alternate functions OTG_HS_ULPI_DIR and EVENTOUT. |
| E12 | PH13 | bidirectional | Port H bit 13 I/O, 5 V tolerant (FT); alternate functions TIM8_CH1N, CAN1_TX and EVENTOUT. |
| E13 | PH14 | bidirectional | Port H bit 14 I/O, 5 V tolerant (FT); alternate functions TIM8_CH2N, DCMI_D4 and EVENTOUT. |
| E14 | PI0 | bidirectional | Port I bit 0 I/O, 5 V tolerant (FT); alternate functions TIM5_CH4, SPI2_NSS, I2S2_WS, DCMI_D13 and EVENTOUT. |
| E15 | PA9 | bidirectional | Port A bit 9 I/O, 5 V tolerant (FT); alternate functions USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0 and EVENTOUT, with OTG_FS_VBUS as additional function. |
| F1 | PC15/OSC32_OUT | bidirectional | Port C bit 15 I/O supplied through the power switch (3 mA sink limit); it is the OSC32_OUT 32 kHz oscillator output when the LSE oscillator is used. |
| F2 | VSS | power_in | Ground (VSS) supply pin. |
| F3 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| F4 | PH2 | bidirectional | Port H bit 2 I/O, 5 V tolerant (FT); alternate functions ETH_MII_CRS and EVENTOUT. |
| F6 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| F7 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| F8 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| F9 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| F10 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| F12 | VSS | power_in | Ground (VSS) supply pin. |
| F13 | VCAP_2 | power_in | Voltage regulator decoupling pin VCAP_2, connected to the external capacitor required by the regulator. |
| F14 | PC9 | bidirectional | Port C bit 9 I/O, 5 V tolerant (FT); alternate functions MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, SDIO_D1, DCMI_D3 and EVENTOUT. |
| F15 | PA8 | bidirectional | Port A bit 8 I/O, 5 V tolerant (FT); alternate functions MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF and EVENTOUT. |
| G1 | PH0/OSC_IN | bidirectional | Port H bit 0 I/O (FT, not 5 V tolerant in oscillator mode); it is the OSC_IN HSE oscillator input when the external oscillator is used. |
| G2 | VSS | power_in | Ground (VSS) supply pin. |
| G3 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| G4 | PH3 | bidirectional | Port H bit 3 I/O, 5 V tolerant (FT); alternate functions ETH_MII_COL and EVENTOUT. |
| G6 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| G7 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| G8 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| G9 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| G10 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| G12 | VSS | power_in | Ground (VSS) supply pin. |
| G13 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| G14 | PC8 | bidirectional | Port C bit 8 I/O, 5 V tolerant (FT); alternate functions TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2 and EVENTOUT. |
| G15 | PC7 | bidirectional | Port C bit 7 I/O, 5 V tolerant (FT); alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2 and EVENTOUT. |
| H1 | PH1/OSC_OUT | bidirectional | Port H bit 1 I/O (FT, not 5 V tolerant in oscillator mode); it is the OSC_OUT HSE oscillator output when the external oscillator is used. |
| H2 | PF2 | bidirectional | Port F bit 2 I/O, 5 V tolerant (FT); alternate functions FSMC_A2, I2C2_SMBA and EVENTOUT. |
| H3 | PF1 | bidirectional | Port F bit 1 I/O, 5 V tolerant (FT); alternate functions FSMC_A1, I2C2_SCL and EVENTOUT. |
| H4 | PH4 | bidirectional | Port H bit 4 I/O, 5 V tolerant (FT); alternate functions I2C2_SCL, OTG_HS_ULPI_NXT and EVENTOUT. |
| H6 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| H7 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| H8 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| H9 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| H10 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| H12 | VSS | power_in | Ground (VSS) supply pin. |
| H13 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| H14 | PG8 | bidirectional | Port G bit 8 I/O, 5 V tolerant (FT); alternate functions USART6_RTS, ETH_PPS_OUT and EVENTOUT. |
| H15 | PC6 | bidirectional | Port C bit 6 I/O, 5 V tolerant (FT); alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1 and EVENTOUT. |
| J1 | NRST | bidirectional | Bidirectional active-low reset pin with an embedded weak pull-up resistor. |
| J2 | PF3 | bidirectional | Port F bit 3 I/O, 5 V tolerant (FT, except in analog mode); alternate functions FSMC_A3 and EVENTOUT, with ADC3_IN9 as additional function. |
| J3 | PF4 | bidirectional | Port F bit 4 I/O, 5 V tolerant (FT, except in analog mode); alternate functions FSMC_A4 and EVENTOUT, with ADC3_IN14 as additional function. |
| J4 | PH5 | bidirectional | Port H bit 5 I/O, 5 V tolerant (FT); alternate functions I2C2_SDA and EVENTOUT. |
| J6 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| J7 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| J8 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| J9 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| J10 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| J12 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| J13 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| J14 | PG7 | bidirectional | Port G bit 7 I/O, 5 V tolerant (FT); alternate functions FSMC_INT3, USART6_CK and EVENTOUT. |
| J15 | PG6 | bidirectional | Port G bit 6 I/O, 5 V tolerant (FT); alternate functions FSMC_INT2 and EVENTOUT. |
| K1 | PF7 | bidirectional | Port F bit 7 I/O (FT, except in analog mode); alternate functions TIM11_CH1, FSMC_NREG and EVENTOUT, with ADC3_IN5 as additional function. |
| K2 | PF6 | bidirectional | Port F bit 6 I/O (FT, except in analog mode); alternate functions TIM10_CH1, FSMC_NIORD and EVENTOUT, with ADC3_IN4 as additional function. |
| K3 | PF5 | bidirectional | Port F bit 5 I/O (FT, except in analog mode); alternate function FSMC_A5 and EVENTOUT, with ADC3_IN15 as additional function. |
| K4 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| K6 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| K7 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| K8 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| K9 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| K10 | VSS | power_in | Ball connected to VSS for heat dissipation and package mechanical stability (UFBGA176 note 1). |
| K12 | PH12 | bidirectional | Port H bit 12 I/O, 5 V tolerant (FT); alternate functions TIM5_CH3, DCMI_D3 and EVENTOUT. |
| K13 | PG5 | bidirectional | Port G bit 5 I/O, 5 V tolerant (FT); alternate functions FSMC_A15 and EVENTOUT. |
| K14 | PG4 | bidirectional | Port G bit 4 I/O, 5 V tolerant (FT); alternate functions FSMC_A14 and EVENTOUT. |
| K15 | PG3 | bidirectional | Port G bit 3 I/O, 5 V tolerant (FT); alternate functions FSMC_A13 and EVENTOUT. |
| L1 | PF10 | bidirectional | Port F bit 10 I/O (FT, except in analog mode); alternate function FSMC_INTR and EVENTOUT, with ADC3_IN8 as additional function. |
| L2 | PF9 | bidirectional | Port F bit 9 I/O (FT, except in analog mode); alternate functions TIM14_CH1, FSMC_CD and EVENTOUT, with ADC3_IN7 as additional function. |
| L3 | PF8 | bidirectional | Port F bit 8 I/O (FT, except in analog mode); alternate functions TIM13_CH1, FSMC_NIOWR and EVENTOUT, with ADC3_IN6 as additional function. |
| L4 | BYPASS_REG | input | Voltage regulator bypass control input (FT); when tied to VDD the internal regulator is off and PA0 becomes the internal reset in UFBGA176 devices. |
| L12 | PH11 | bidirectional | Port H bit 11 I/O, 5 V tolerant (FT); alternate functions TIM5_CH2, DCMI_D2 and EVENTOUT. |
| L13 | PH10 | bidirectional | Port H bit 10 I/O, 5 V tolerant (FT); alternate functions TIM5_CH1, DCMI_D1 and EVENTOUT. |
| L14 | PD15 | bidirectional | Port D bit 15 I/O, 5 V tolerant (FT); alternate functions FSMC_D1, TIM4_CH4 and EVENTOUT. |
| L15 | PG2 | bidirectional | Port G bit 2 I/O, 5 V tolerant (FT); alternate functions FSMC_A12 and EVENTOUT. |
| M1 | VSSA | power_in | Analog ground pin for the ADC, DAC and reference. |
| M2 | PC0 | bidirectional | Port C bit 0 I/O (FT, except in analog mode); alternate function OTG_HS_ULPI_STP and EVENTOUT, with ADC123_IN10 as additional function. |
| M3 | PC1 | bidirectional | Port C bit 1 I/O (FT, except in analog mode); alternate functions ETH_MDC and EVENTOUT, with ADC123_IN11 as additional function. |
| M4 | PC2 | bidirectional | Port C bit 2 I/O (FT, except in analog mode); alternate functions SPI2_MISO, I2S2ext_SD, OTG_HS_ULPI_DIR, ETH_MII_TXD2 and EVENTOUT, with ADC123_IN12 as additional function. |
| M5 | PC3 | bidirectional | Port C bit 3 I/O (FT, except in analog mode); alternate functions SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK and EVENTOUT, with ADC123_IN13 as additional function. |
| M6 | PB2/BOOT1 | bidirectional | Port B bit 2 I/O, 5 V tolerant (FT); it also carries the BOOT1 function and the EVENTOUT alternate function. |
| M7 | PG1 | bidirectional | Port G bit 1 I/O, 5 V tolerant (FT); alternate functions FSMC_A11 and EVENTOUT. |
| M8 | VSS | power_in | Ground (VSS) supply pin. |
| M9 | VSS | power_in | Ground (VSS) supply pin. |
| M10 | VCAP_1 | power_in | Voltage regulator decoupling pin VCAP_1, connected to the external capacitor required by the regulator. |
| M11 | PH6 | bidirectional | Port H bit 6 I/O, 5 V tolerant (FT); alternate functions I2C2_SMBA, TIM12_CH1, ETH_MII_RXD2 and EVENTOUT. |
| M12 | PH8 | bidirectional | Port H bit 8 I/O, 5 V tolerant (FT); alternate functions I2C3_SDA, DCMI_HSYNC and EVENTOUT. |
| M13 | PH9 | bidirectional | Port H bit 9 I/O, 5 V tolerant (FT); alternate functions I2C3_SMBA, TIM12_CH2, DCMI_D0 and EVENTOUT. |
| M14 | PD14 | bidirectional | Port D bit 14 I/O, 5 V tolerant (FT); alternate functions FSMC_D0, TIM4_CH3 and EVENTOUT. |
| M15 | PD13 | bidirectional | Port D bit 13 I/O, 5 V tolerant (FT); alternate functions FSMC_A18, TIM4_CH2 and EVENTOUT. |
| N1 | VREF- | power_in | Negative reference voltage input for the ADC. |
| N2 | PA1 | bidirectional | Port A bit 1 I/O, 5 V tolerant (FT); alternate functions USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2 and EVENTOUT, with ADC123_IN1 as additional function. |
| N3 | PA0/WKUP | bidirectional | Port A bit 0 I/O, 5 V tolerant (FT) with WKUP wakeup function; alternate functions USART2_CTS, UART4_TX, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and EVENTOUT, and with BYPASS_REG at VDD it is the internal active-low reset. |
| N4 | PA4 | bidirectional | Port A bit 4 I/O, 3.3 V tolerant TTa structure connected directly to the ADC; alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF, I2S3_WS and EVENTOUT, with ADC12_IN4 and DAC_OUT1 as additional functions. |
| N5 | PC4 | bidirectional | Port C bit 4 I/O, 5 V tolerant (FT); alternate functions ETH_RMII_RXD0, ETH_MII_RXD0 and EVENTOUT, with ADC12_IN14 as additional function. |
| N6 | PF13 | bidirectional | Port F bit 13 I/O, 5 V tolerant (FT); alternate functions FSMC_A7 and EVENTOUT. |
| N7 | PG0 | bidirectional | Port G bit 0 I/O, 5 V tolerant (FT); alternate functions FSMC_A10 and EVENTOUT. |
| N8 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| N9 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| N10 | VDD | power_in | Application supply for the core and I/Os, 1.8 V to 3.6 V. |
| N11 | PE13 | bidirectional | Port E bit 13 I/O, 5 V tolerant (FT); alternate functions TIM1_CH3, FSMC_D10 and EVENTOUT. |
| N12 | PH7 | bidirectional | Port H bit 7 I/O, 5 V tolerant (FT); alternate functions I2C3_SCL, ETH_MII_RXD3 and EVENTOUT. |
| N13 | PD12 | bidirectional | Port D bit 12 I/O, 5 V tolerant (FT); alternate functions FSMC_A17/FSMC_ALE, TIM4_CH1, USART3_RTS and EVENTOUT. |
| N14 | PD11 | bidirectional | Port D bit 11 I/O, 5 V tolerant (FT); alternate functions FSMC_A16/FSMC_CLE, USART3_CTS and EVENTOUT. |
| N15 | PD10 | bidirectional | Port D bit 10 I/O, 5 V tolerant (FT); alternate functions FSMC_D15, USART3_CK and EVENTOUT. |
| P1 | VREF+ | power_in | Positive reference voltage input for the ADC and DAC. |
| P2 | PA2 | bidirectional | Port A bit 2 I/O, 5 V tolerant (FT); alternate functions USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO and EVENTOUT, with ADC123_IN2 as additional function. |
| P3 | PA6 | bidirectional | Port A bit 6 I/O, 5 V tolerant (FT); alternate functions SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN and EVENTOUT, with ADC12_IN6 as additional function. |
| P4 | PA5 | bidirectional | Port A bit 5 I/O, 3.3 V tolerant TTa structure connected directly to the ADC; alternate functions SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N and EVENTOUT, with ADC12_IN5 and DAC_OUT2 as additional functions. |
| P5 | PC5 | bidirectional | Port C bit 5 I/O, 5 V tolerant (FT); alternate functions ETH_MII_RXD1, ETH_RMII_RXD1 and EVENTOUT, with ADC12_IN15 as additional function. |
| P6 | PF12 | bidirectional | Port F bit 12 I/O, 5 V tolerant (FT); alternate functions FSMC_A6 and EVENTOUT. |
| P7 | PF15 | bidirectional | Port F bit 15 I/O, 5 V tolerant (FT); alternate functions FSMC_A9 and EVENTOUT. |
| P8 | PE8 | bidirectional | Port E bit 8 I/O, 5 V tolerant (FT); alternate functions FSMC_D5, TIM1_CH1N and EVENTOUT. |
| P9 | PE9 | bidirectional | Port E bit 9 I/O, 5 V tolerant (FT); alternate functions FSMC_D6, TIM1_CH1 and EVENTOUT. |
| P10 | PE11 | bidirectional | Port E bit 11 I/O, 5 V tolerant (FT); alternate functions FSMC_D8, TIM1_CH2 and EVENTOUT. |
| P11 | PE14 | bidirectional | Port E bit 14 I/O, 5 V tolerant (FT); alternate functions FSMC_D11, TIM1_CH4 and EVENTOUT. |
| P12 | PB12 | bidirectional | Port B bit 12 I/O, 5 V tolerant (FT); alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, OTG_HS_ID and EVENTOUT. |
| P13 | PB13 | bidirectional | Port B bit 13 I/O, 5 V tolerant (FT); alternate functions SPI2_SCK, I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6 and EVENTOUT, with OTG_HS_VBUS as additional function. |
| P14 | PD9 | bidirectional | Port D bit 9 I/O, 5 V tolerant (FT); alternate functions FSMC_D14, USART3_RX and EVENTOUT. |
| P15 | PD8 | bidirectional | Port D bit 8 I/O, 5 V tolerant (FT); alternate functions FSMC_D13, USART3_TX and EVENTOUT. |
| R1 | VDDA | power_in | Analog supply voltage for the ADC, DAC and reference. |
| R2 | PA3 | bidirectional | Port A bit 3 I/O, 5 V tolerant (FT); alternate functions USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL and EVENTOUT, with ADC123_IN3 as additional function. |
| R3 | PA7 | bidirectional | Port A bit 7 I/O, 5 V tolerant (FT); alternate functions SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, ETH_RMII_CRS_DV, TIM1_CH1N and EVENTOUT, with ADC12_IN7 as additional function. |
| R4 | PB1 | bidirectional | Port B bit 1 I/O, 5 V tolerant (FT); alternate functions TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N and EVENTOUT, with ADC12_IN9 as additional function. |
| R5 | PB0 | bidirectional | Port B bit 0 I/O, 5 V tolerant (FT); alternate functions TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N and EVENTOUT, with ADC12_IN8 as additional function. |
| R6 | PF11 | bidirectional | Port F bit 11 I/O, 5 V tolerant (FT); alternate functions DCMI_D12 and EVENTOUT. |
| R7 | PF14 | bidirectional | Port F bit 14 I/O, 5 V tolerant (FT); alternate functions FSMC_A8 and EVENTOUT. |
| R8 | PE7 | bidirectional | Port E bit 7 I/O, 5 V tolerant (FT); alternate functions FSMC_D4, TIM1_ETR and EVENTOUT. |
| R9 | PE10 | bidirectional | Port E bit 10 I/O, 5 V tolerant (FT); alternate functions FSMC_D7, TIM1_CH2N and EVENTOUT. |
| R10 | PE12 | bidirectional | Port E bit 12 I/O, 5 V tolerant (FT); alternate functions FSMC_D9, TIM1_CH3N and EVENTOUT. |
| R11 | PE15 | bidirectional | Port E bit 15 I/O, 5 V tolerant (FT); alternate functions FSMC_D12, TIM1_BKIN and EVENTOUT. |
| R12 | PB10 | bidirectional | Port B bit 10 I/O, 5 V tolerant (FT); alternate functions SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3 and EVENTOUT. |
| R13 | PB11 | bidirectional | Port B bit 11 I/O, 5 V tolerant (FT); alternate functions I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN, TIM2_CH4 and EVENTOUT. |
| R14 | PB14 | bidirectional | Port B bit 14 I/O, 5 V tolerant (FT); alternate functions SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N, I2S2ext_SD and EVENTOUT. |
| R15 | PB15 | bidirectional | Port B bit 15 I/O, 5 V tolerant (FT); alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP and EVENTOUT, with RTC_REFIN as additional function. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | UFBGA-201(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 201 |

## CAD (KiCad official)

- Symbol: `STM32F407IGH6TR`
- Footprint: `Package_BGA:UFBGA-201_10x10mm_Layout15x15_P0.65mm`
- 3D model: UFBGA-201(10x10) (KiCad packages3D, STEP)
- 3D model files: `stm32f407igh6tr-etched.step` / `stm32f407igh6tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f407igh6tr.step` / `stm32f407igh6tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm32f407igh6tr.pdf) (203 pp, sha256 `1356a8eec66c7d48`, retrieved 2026-10-09, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stm32f407igh6tr-datasheet.pdf)