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STM32F407IEH6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFBGA-201. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f407ieh6factory-2.0.0extractor-text
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STM32F407IEH6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFBGA-201

STM32F407IEH6 from STMicroelectronics, in a UFBGA-201. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 PE3 bidirectional 5 V tolerant I/O (FT). AF: TRACED0, FSMC_A19, EVENTOUT.
A2 PE2 bidirectional 5 V tolerant I/O (FT). AF: TRACECLK, FSMC_A23, ETH_MII_TXD3, EVENTOUT.
A3 PE1 bidirectional 5 V tolerant I/O (FT). AF: FSMC_NBL1, DCMI_D3, EVENTOUT.
A4 PE0 bidirectional 5 V tolerant I/O (FT). AF: TIM4_ETR, FSMC_NBL0, DCMI_D2, EVENTOUT.
A5 PB8 bidirectional 5 V tolerant I/O (FT). AF: TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL, CAN1_RX, EVENTOUT.
A6 PB5 bidirectional 5 V tolerant I/O (FT). AF: I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10, I2S3_SD, EVENTOUT.
A7 PG14 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A25, USART6_TX, ETH_MII_TXD1, ETH_RMII_TXD1, EVENTOUT.
A8 PG13 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A24, USART6_CTS, ETH_MII_TXD0, ETH_RMII_TXD0, EVENTOUT.
A9 PB4 bidirectional 5 V tolerant I/O (FT). AF: NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO, I2S3ext_SD, EVENTOUT.
A10 PB3 bidirectional 5 V tolerant I/O (FT). AF: JTDO, TRACESWO, SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK, EVENTOUT.
A11 PD7 bidirectional 5 V tolerant I/O (FT). AF: USART2_CK, FSMC_NE1/FSMC_NCE2, EVENTOUT.
A12 PC12 bidirectional 5 V tolerant I/O (FT). AF: UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD, USART3_CK, EVENTOUT.
A13 PA15 bidirectional 5 V tolerant I/O (FT). AF: JTDI, TIM2_CH1_ETR, SPI3_NSS, I2S3_WS, SPI1_NSS, EVENTOUT.
A14 PA14 bidirectional 5 V tolerant I/O (FT). AF: JTCK-SWCLK, EVENTOUT.
A15 PA13 bidirectional 5 V tolerant I/O (FT). AF: JTMS-SWDIO, EVENTOUT.
B1 PE4 bidirectional 5 V tolerant I/O (FT). AF: TRACED1, FSMC_A20, DCMI_D4, EVENTOUT.
B2 PE5 bidirectional 5 V tolerant I/O (FT). AF: TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6, EVENTOUT.
B3 PE6 bidirectional 5 V tolerant I/O (FT). AF: TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7, EVENTOUT.
B4 PB9 bidirectional 5 V tolerant I/O (FT). AF: SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA, CAN1_TX, EVENTOUT.
B5 PB7 bidirectional 5 V tolerant I/O (FT). AF: I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX, TIM4_CH2, EVENTOUT.
B6 PB6 bidirectional 5 V tolerant I/O (FT). AF: I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5, USART1_TX, EVENTOUT.
B7 PG15 bidirectional 5 V tolerant I/O (FT). AF: USART6_CTS, DCMI_D13, EVENTOUT.
B8 PG12 bidirectional 5 V tolerant I/O (FT). AF: FSMC_NE4, USART6_RTS, EVENTOUT.
B9 PG11 bidirectional 5 V tolerant I/O (FT). AF: FSMC_NCE4_2, ETH_MII_TX_EN, ETH_RMII_TX_EN, EVENTOUT.
B10 PG10 bidirectional 5 V tolerant I/O (FT). AF: FSMC_NCE4_1, FSMC_NE3, EVENTOUT.
B11 PD6 bidirectional 5 V tolerant I/O (FT). AF: FSMC_NWAIT, USART2_RX, EVENTOUT.
B12 PD0 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D2, CAN1_RX, EVENTOUT.
B13 PC11 bidirectional 5 V tolerant I/O (FT). AF: UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX, I2S3ext_SD, EVENTOUT.
B14 PC10 bidirectional 5 V tolerant I/O (FT). AF: SPI3_SCK, I2S3_CK, UART4_TX, SDIO_D2, DCMI_D8, USART3_TX, EVENTOUT.
B15 PA12 bidirectional 5 V tolerant I/O (FT). AF: USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP, EVENTOUT.
C1 VBAT power_in Backup-domain supply for the RTC, backup registers and optional backup SRAM (VBAT supply).
C2 PI7 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH3, DCMI_D7, EVENTOUT.
C3 PI6 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH2, DCMI_D6, EVENTOUT.
C4 PI5 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH1, DCMI_VSYNC, EVENTOUT.
C5 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
C6 PDR_ON input 5 V tolerant input (FT) used for PDR_ON and NRST control when the internal reset is OFF.
C7 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
C8 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
C9 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
C10 PG9 bidirectional 5 V tolerant I/O (FT). AF: USART6_RX, FSMC_NE2/FSMC_NCE3, EVENTOUT.
C11 PD5 bidirectional 5 V tolerant I/O (FT). AF: FSMC_NWE, USART2_TX, EVENTOUT.
C12 PD1 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D3, CAN1_TX, EVENTOUT.
C13 PI3 bidirectional 5 V tolerant I/O (FT). AF: TIM8_ETR, SPI2_MOSI, I2S2_SD, DCMI_D10, EVENTOUT.
C14 PI2 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH4, SPI2_MISO, DCMI_D9, I2S2ext_SD, EVENTOUT.
C15 PA11 bidirectional 5 V tolerant I/O (FT). AF: USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM, EVENTOUT.
D1 PC13 bidirectional I/O (FT) supplied through the power switch, sinking at most 3 mA; output speed limited to 2 MHz with 30 pF and not usable as a current source. Additional: RTC_OUT, RTC_TAMP1, RTC_TS.
D2 PI8 bidirectional I/O (FT) supplied through the power switch, sinking at most 3 mA; output speed limited to 2 MHz with 30 pF and not usable as a current source. Additional: RTC_TAMP1, RTC_TAMP2, RTC_TS.
D3 PI9 bidirectional 5 V tolerant I/O (FT). AF: CAN1_RX, EVENTOUT.
D4 PI4 bidirectional 5 V tolerant I/O (FT). AF: TIM8_BKIN, DCMI_D5, EVENTOUT.
D5 VSS power_in Ground reference pin (VSS).
D6 BOOT0 input Dedicated BOOT0 pin (type B) selecting the boot mode; also carries the VPP function for Flash programming with VPP.
D7 VSS power_in Ground reference pin (VSS).
D8 VSS power_in Ground reference pin (VSS).
D9 VSS power_in Ground reference pin (VSS).
D10 PD4 bidirectional 5 V tolerant I/O (FT). AF: FSMC_NOE, USART2_RTS, EVENTOUT.
D11 PD3 bidirectional 5 V tolerant I/O (FT). AF: FSMC_CLK, USART2_CTS, EVENTOUT.
D12 PD2 bidirectional 5 V tolerant I/O (FT). AF: TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT.
D13 PH15 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH3N, DCMI_D11, EVENTOUT.
D14 PI1 bidirectional 5 V tolerant I/O (FT). AF: SPI2_SCK, I2S2_CK, DCMI_D8, EVENTOUT.
D15 PA10 bidirectional 5 V tolerant I/O (FT). AF: USART1_RX, TIM1_CH3, OTG_FS_ID, DCMI_D1, EVENTOUT.
E1 PC14/OSC32_IN bidirectional I/O (FT) supplied through the power switch, sinking at most 3 mA; output speed limited to 2 MHz with 30 pF. Additional: OSC32_IN.
E2 PF0 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A0, I2C2_SDA, EVENTOUT.
E3 PI10 bidirectional 5 V tolerant I/O (FT). AF: ETH_MII_RX_ER, EVENTOUT.
E4 PI11 bidirectional 5 V tolerant I/O (FT). AF: OTG_HS_ULPI_DIR, EVENTOUT.
E12 PH13 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH1N, CAN1_TX, EVENTOUT.
E13 PH14 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH2N, DCMI_D4, EVENTOUT.
E14 PI0 bidirectional 5 V tolerant I/O (FT). AF: TIM5_CH4, SPI2_NSS, I2S2_WS, DCMI_D13, EVENTOUT.
E15 PA9 bidirectional 5 V tolerant I/O (FT). AF: USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0, EVENTOUT. Additional: OTG_FS_VBUS.
F1 PC15/OSC32_OUT bidirectional I/O (FT) supplied through the power switch, sinking at most 3 mA; output speed limited to 2 MHz with 30 pF. Additional: OSC32_OUT.
F2 VSS power_in Ground reference pin (VSS).
F3 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
F4 PH2 bidirectional 5 V tolerant I/O (FT). AF: ETH_MII_CRS, EVENTOUT.
F6 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
F7 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
F8 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
F9 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
F10 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
F12 VSS power_in Ground reference pin (VSS).
F13 VCAP_2 power_in Connection for the external capacitor of the internal voltage regulator (VCAP_2).
F14 PC9 bidirectional 5 V tolerant I/O (FT). AF: MCO2, I2S_CKIN, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4, EVENTOUT.
F15 PA8 bidirectional 5 V tolerant I/O (FT). AF: MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF, EVENTOUT.
G1 PH0/OSC_IN bidirectional I/O (FT, not 5 V tolerant in oscillator mode). Additional: OSC_IN; AF: EVENTOUT.
G2 VSS power_in Ground reference pin (VSS).
G3 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
G4 PH3 bidirectional 5 V tolerant I/O (FT). AF: ETH_MII_COL, EVENTOUT.
G6 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
G7 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
G8 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
G9 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
G10 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
G12 VSS power_in Ground reference pin (VSS).
G13 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
G14 PC8 bidirectional 5 V tolerant I/O (FT). AF: TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2, EVENTOUT.
G15 PC7 bidirectional 5 V tolerant I/O (FT). AF: I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2, EVENTOUT.
H1 PH1/OSC_OUT bidirectional I/O (FT, not 5 V tolerant in oscillator mode). Additional: OSC_OUT; AF: EVENTOUT.
H2 PF2 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A2, I2C2_SMBA, EVENTOUT.
H3 PF1 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A1, I2C2_SCL, EVENTOUT.
H4 PH4 bidirectional 5 V tolerant I/O (FT). AF: I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT.
H6 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
H7 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
H8 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
H9 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
H10 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
H12 VSS power_in Ground reference pin (VSS).
H13 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
H14 PG8 bidirectional 5 V tolerant I/O (FT). AF: USART6_RTS, ETH_PPS_OUT, EVENTOUT.
H15 PC6 bidirectional 5 V tolerant I/O (FT). AF: I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1, EVENTOUT.
J1 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor (RST I/O structure).
J2 PF3 bidirectional 5 V tolerant I/O (FT except analog mode). AF: FSMC_A3, EVENTOUT. Additional: ADC3_IN9.
J3 PF4 bidirectional 5 V tolerant I/O (FT except analog mode). AF: FSMC_A4, EVENTOUT. Additional: ADC3_IN14.
J4 PH5 bidirectional 5 V tolerant I/O (FT). AF: I2C2_SDA, EVENTOUT.
J6 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
J7 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
J8 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
J9 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
J10 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
J12 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
J13 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
J14 PG7 bidirectional 5 V tolerant I/O (FT). AF: FSMC_INT3, USART6_CK, EVENTOUT.
J15 PG6 bidirectional 5 V tolerant I/O (FT). AF: FSMC_INT2, EVENTOUT.
K1 PF7 bidirectional 5 V tolerant I/O (FT except analog mode). AF: TIM11_CH1, FSMC_NREG, EVENTOUT. Additional: ADC3_IN5.
K2 PF6 bidirectional 5 V tolerant I/O (FT except analog mode). AF: TIM10_CH1, FSMC_NIORD, EVENTOUT. Additional: ADC3_IN4.
K3 PF5 bidirectional 5 V tolerant I/O (FT except analog mode). AF: FSMC_A5, EVENTOUT. Additional: ADC3_IN15.
K4 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
K6 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
K7 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
K8 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
K9 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
K10 VSS power_in Ball connected to VSS for heat dissipation and package mechanical stability (not a signal ball).
K12 PH12 bidirectional 5 V tolerant I/O (FT). AF: TIM5_CH3, DCMI_D3, EVENTOUT.
K13 PG5 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A15, EVENTOUT.
K14 PG4 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A14, EVENTOUT.
K15 PG3 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A13, EVENTOUT.
L1 PF10 bidirectional 5 V tolerant I/O (FT except analog mode). AF: FSMC_INTR, EVENTOUT. Additional: ADC3_IN8.
L2 PF9 bidirectional 5 V tolerant I/O (FT except analog mode). AF: TIM14_CH1, FSMC_CD, EVENTOUT. Additional: ADC3_IN7.
L3 PF8 bidirectional 5 V tolerant I/O (FT except analog mode). AF: TIM13_CH1, FSMC_NIOWR, EVENTOUT. Additional: ADC3_IN6.
L4 BYPASS_REG input 5 V tolerant input (FT) controlling the regulator state; set to VDD for regulator OFF / internal reset ON mode.
L12 PH11 bidirectional 5 V tolerant I/O (FT). AF: TIM5_CH2, DCMI_D2, EVENTOUT.
L13 PH10 bidirectional 5 V tolerant I/O (FT). AF: TIM5_CH1, DCMI_D1, EVENTOUT.
L14 PD15 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D1, TIM4_CH4, EVENTOUT.
L15 PG2 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A12, EVENTOUT.
M1 VSSA power_in Analog ground pin for the analog peripherals (VSSA).
M2 PC0 bidirectional 5 V tolerant I/O (FT except analog mode). AF: OTG_HS_ULPI_STP, EVENTOUT. Additional: ADC123_IN10.
M3 PC1 bidirectional 5 V tolerant I/O (FT except analog mode). AF: ETH_MDC, EVENTOUT. Additional: ADC123_IN11.
M4 PC2 bidirectional 5 V tolerant I/O (FT except analog mode). AF: SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, I2S2ext_SD, EVENTOUT. Additional: ADC123_IN12.
M5 PC3 bidirectional 5 V tolerant I/O (FT except analog mode). AF: SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, EVENTOUT. Additional: ADC123_IN13.
M6 PB2/BOOT1 bidirectional 5 V tolerant I/O (FT); pin name also carries the BOOT1 function. AF: EVENTOUT.
M7 PG1 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A11, EVENTOUT.
M8 VSS power_in Ground reference pin (VSS).
M9 VSS power_in Ground reference pin (VSS).
M10 VCAP_1 power_in Connection for the external capacitor of the internal voltage regulator (VCAP_1).
M11 PH6 bidirectional 5 V tolerant I/O (FT). AF: I2C2_SMBA, TIM12_CH1, ETH_MII_RXD2, EVENTOUT.
M12 PH8 bidirectional 5 V tolerant I/O (FT). AF: I2C3_SDA, DCMI_HSYNC, EVENTOUT.
M13 PH9 bidirectional 5 V tolerant I/O (FT). AF: I2C3_SMBA, TIM12_CH2, DCMI_D0, EVENTOUT.
M14 PD14 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D0, TIM4_CH3, EVENTOUT.
M15 PD13 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A18, TIM4_CH2, EVENTOUT.
N1 VREF- power_in Negative reference voltage pin (VREF-) for the ADC, listed in the ADC characteristics.
N2 PA1 bidirectional 5 V tolerant I/O (FT except analog mode). AF: USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2, EVENTOUT. Additional: ADC123_IN1.
N3 PA0/WKUP bidirectional 5 V tolerant I/O (FT except analog mode). AF: USART2_CTS, UART4_TX, ETH_MII_CRS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, EVENTOUT. Additional: ADC123_IN0/WKUP; on UFBGA176 with BYPASS_REG at VDD it is used as internal reset (active low).
N4 PA4 bidirectional 3.3 V tolerant I/O (TTa) connected directly to the ADC. AF: SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF, I2S3_WS, EVENTOUT. Additional: ADC12_IN4/DAC_OUT1.
N5 PC4 bidirectional 5 V tolerant I/O (FT except analog mode). AF: ETH_RMII_RX_D0, ETH_MII_RX_D0, EVENTOUT. Additional: ADC12_IN14.
N6 PF13 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A7, EVENTOUT.
N7 PG0 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A10, EVENTOUT.
N8 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
N9 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
N10 VDD power_in Digital supply pin; 1.8 V to 3.6 V application supply for the I/Os and core.
N11 PE13 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D10, TIM1_CH3, EVENTOUT.
N12 PH7 bidirectional 5 V tolerant I/O (FT). AF: I2C3_SCL, ETH_MII_RXD3, EVENTOUT.
N13 PD12 bidirectional 5 V tolerant I/O (FT). AF: FSMC_ALE, FSMC_A17, TIM4_CH1, USART3_RTS, EVENTOUT.
N14 PD11 bidirectional 5 V tolerant I/O (FT). AF: FSMC_CLE, FSMC_A16, USART3_CTS, EVENTOUT.
N15 PD10 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D15, USART3_CK, EVENTOUT.
P1 VREF+ power_in Positive reference voltage pin (VREF+) for the ADC and DAC.
P2 PA2 bidirectional 5 V tolerant I/O (FT except analog mode). AF: USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO, EVENTOUT. Additional: ADC123_IN2.
P3 PA6 bidirectional 5 V tolerant I/O (FT except analog mode). AF: SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN, EVENTOUT. Additional: ADC12_IN6.
P4 PA5 bidirectional 3.3 V tolerant I/O (TTa) connected directly to the ADC. AF: SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N, EVENTOUT. Additional: ADC12_IN5/DAC_OUT2.
P5 PC5 bidirectional 5 V tolerant I/O (FT except analog mode). AF: ETH_RMII_RX_D1, ETH_MII_RX_D1, EVENTOUT. Additional: ADC12_IN15.
P6 PF12 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A6, EVENTOUT.
P7 PF15 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A9, EVENTOUT.
P8 PE8 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D5, TIM1_CH1N, EVENTOUT.
P9 PE9 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D6, TIM1_CH1, EVENTOUT.
P10 PE11 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D8, TIM1_CH2, EVENTOUT.
P11 PE14 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D11, TIM1_CH4, EVENTOUT.
P12 PB12 bidirectional 5 V tolerant I/O (FT). AF: SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0, ETH_MII_TXD0, OTG_HS_ID, EVENTOUT.
P13 PB13 bidirectional 5 V tolerant I/O (FT). AF: SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1, ETH_RMII_TXD1, EVENTOUT. Additional: OTG_HS_VBUS.
P14 PD9 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D14, USART3_RX, EVENTOUT.
P15 PD8 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D13, USART3_TX, EVENTOUT.
R1 VDDA power_in Analog supply pin (VDDA) for the analog peripherals such as the ADCs and DACs.
R2 PA3 bidirectional 5 V tolerant I/O (FT except analog mode). AF: USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL, EVENTOUT. Additional: ADC123_IN3.
R3 PA7 bidirectional 5 V tolerant I/O (FT except analog mode). AF: SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, TIM1_CH1N, ETH_RMII_CRS_DV, EVENTOUT. Additional: ADC12_IN7.
R4 PB1 bidirectional 5 V tolerant I/O (FT except analog mode). AF: TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N, EVENTOUT. Additional: ADC12_IN9.
R5 PB0 bidirectional 5 V tolerant I/O (FT except analog mode). AF: TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N, EVENTOUT. Additional: ADC12_IN8.
R6 PF11 bidirectional 5 V tolerant I/O (FT). AF: DCMI_D12, EVENTOUT.
R7 PF14 bidirectional 5 V tolerant I/O (FT). AF: FSMC_A8, EVENTOUT.
R8 PE7 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D4, TIM1_ETR, EVENTOUT.
R9 PE10 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D7, TIM1_CH2N, EVENTOUT.
R10 PE12 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D9, TIM1_CH3N, EVENTOUT.
R11 PE15 bidirectional 5 V tolerant I/O (FT). AF: FSMC_D12, TIM1_BKIN, EVENTOUT.
R12 PB10 bidirectional 5 V tolerant I/O (FT). AF: SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3, EVENTOUT.
R13 PB11 bidirectional 5 V tolerant I/O (FT). AF: I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN, TIM2_CH4, EVENTOUT.
R14 PB14 bidirectional 5 V tolerant I/O (FT). AF: SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N, I2S2ext_SD, EVENTOUT.
R15 PB15 bidirectional 5 V tolerant I/O (FT). AF: SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2, OTG_HS_DP, EVENTOUT. Additional: RTC_REFIN.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFBGA-201
Category Embedded Processors & Controllers
Pins 201

CAD (KiCad official)

  • Symbol: STM32F407IEH6
  • Footprint: Package_BGA:UFBGA-201_10x10mm_Layout15x15_P0.65mm
  • 3D model: UFBGA-201 (KiCad packages3D, STEP)
  • 3D model files: stm32f407ieh6-etched.step / stm32f407ieh6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f407ieh6.step / stm32f407ieh6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (203 pp, sha256 1356a8eec66c7d48, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF