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STM32F405RGT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32F405RGT6
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32F405RGT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Supply pin (VBAT) for the RTC, backup registers and optional backup SRAM. |
| 2 | PC13 | bidirectional | FT I/O supplied through the power switch (3 mA sink limit), so as an output it is limited to 2 MHz with 30 pF max load and must not source current; functions after first backup power-up are RTC_OUT, RTC_TAMP1 and RTC_TS. |
| 3 | PC14/OSC32_IN | bidirectional | FT I/O supplied through the power switch (2 MHz, 30 pF max as output) that also serves as the 32 kHz oscillator input OSC32_IN. |
| 4 | PC15/OSC32_OUT | bidirectional | FT I/O supplied through the power switch (2 MHz, 30 pF max as output) that also serves as the 32 kHz oscillator output OSC32_OUT. |
| 5 | PH0/OSC_IN | bidirectional | FT I/O (5 V tolerant except in oscillator mode) that also serves as the main oscillator input OSC_IN. |
| 6 | PH1/OSC_OUT | bidirectional | FT I/O (5 V tolerant except in oscillator mode) that also serves as the main oscillator output OSC_OUT. |
| 7 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 8 | PC0 | bidirectional | FT I/O with ADC123_IN10 analog function and OTG_HS_ULPI_STP alternate function. |
| 9 | PC1 | bidirectional | FT I/O with ADC123_IN11 analog function and ETH_MDC alternate function. |
| 10 | PC2 | bidirectional | FT I/O with ADC123_IN12 analog function; alternate functions include SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2 and I2S2ext_SD. |
| 11 | PC3 | bidirectional | FT I/O with ADC123_IN13 analog function; alternate functions include SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT and ETH_MII_TX_CLK. |
| 12 | VSSA | power_in | Analog ground supply pin. |
| 13 | VDDA | power_in | Analog power supply pin. |
| 14 | PA0/WKUP | bidirectional | FT I/O with wakeup (WKUP) and ADC123_IN0 functions; alternate functions include USART2_CTS, UART4_TX, TIM2_CH1_ETR, TIM5_CH1 and TIM8_ETR. |
| 15 | PA1 | bidirectional | FT I/O with ADC123_IN1 analog function; alternate functions include USART2_RTS, UART4_RX, TIM5_CH2, TIM2_CH2 and ETH RMII/MII clock. |
| 16 | PA2 | bidirectional | FT I/O with ADC123_IN2 analog function; alternate functions include USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3 and ETH_MDIO. |
| 17 | PA3 | bidirectional | FT I/O with ADC123_IN3 analog function; alternate functions include USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0 and ETH_MII_COL. |
| 18 | VSS | power_in | Ground supply pin. |
| 19 | VDD | power_in | Digital power supply pin. |
| 20 | PA4 | bidirectional | TTa I/O (3.3 V tolerant, directly connected to ADC) with ADC12_IN4 and DAC_OUT1; alternate functions include SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK and DCMI_HSYNC. |
| 21 | PA5 | bidirectional | TTa I/O with ADC12_IN5 and DAC_OUT2; alternate functions include SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR and TIM8_CH1N. |
| 22 | PA6 | bidirectional | FT I/O with ADC12_IN6 analog function; alternate functions include SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1 and TIM1_BKIN. |
| 23 | PA7 | bidirectional | FT I/O with ADC12_IN7 analog function; alternate functions include SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, TIM1_CH1N and ETH RMII/MII signals. |
| 24 | PC4 | bidirectional | FT I/O with ADC12_IN14 analog function and ETH_RMII_RX_D0/ETH_MII_RX_D0 alternate functions. |
| 25 | PC5 | bidirectional | FT I/O with ADC12_IN15 analog function and ETH_RMII_RX_D1/ETH_MII_RX_D1 alternate functions. |
| 26 | PB0 | bidirectional | FT I/O with ADC12_IN8 analog function; alternate functions include TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2 and TIM1_CH2N. |
| 27 | PB1 | bidirectional | FT I/O with ADC12_IN9 analog function; alternate functions include TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3 and TIM1_CH3N. |
| 28 | PB2/BOOT1 | bidirectional | FT I/O that also serves as the BOOT1 boot mode selection pin. |
| 29 | PB10 | bidirectional | FT I/O; alternate functions include SPI2_SCK/I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER and TIM2_CH3. |
| 30 | PB11 | bidirectional | FT I/O; alternate functions include I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN/ETH_MII_TX_EN and TIM2_CH4. |
| 31 | VCAP_1 | passive | Pin for the external capacitor of the internal 1.2 V regulator (VCAP_1). |
| 32 | VDD | power_in | Digital power supply pin. |
| 33 | PB12 | bidirectional | FT I/O; alternate functions include SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ETH_RMII_TXD0 and OTG_HS_ID. |
| 34 | PB13 | bidirectional | FT I/O with OTG_HS_VBUS additional function; alternate functions include SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and ETH_RMII_TXD1. |
| 35 | PB14 | bidirectional | FT I/O; alternate functions include SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N and I2S2ext_SD. |
| 36 | PB15 | bidirectional | FT I/O with RTC_REFIN additional function; alternate functions include SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2 and OTG_HS_DP. |
| 37 | PC6 | bidirectional | FT I/O; alternate functions include I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0 and TIM3_CH1. |
| 38 | PC7 | bidirectional | FT I/O; alternate functions include I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1 and TIM3_CH2. |
| 39 | PC8 | bidirectional | FT I/O; alternate functions include TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK and DCMI_D2. |
| 40 | PC9 | bidirectional | FT I/O; alternate functions include I2S_CKIN, MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3 and TIM3_CH4. |
| 41 | PA8 | bidirectional | FT I/O; alternate functions include MCO1, USART1_CK, TIM1_CH1, I2C3_SCL and OTG_FS_SOF. |
| 42 | PA9 | bidirectional | FT I/O with OTG_FS_VBUS additional function; alternate functions include USART1_TX, TIM1_CH2, I2C3_SMBA and DCMI_D0. |
| 43 | PA10 | bidirectional | FT I/O; alternate functions include USART1_RX, TIM1_CH3, OTG_FS_ID and DCMI_D1. |
| 44 | PA11 | bidirectional | FT I/O; alternate functions include USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM. |
| 45 | PA12 | bidirectional | FT I/O; alternate functions include USART1_RTS, CAN1_TX, TIM1_ETR and OTG_FS_DP. |
| 46 | PA13 | bidirectional | FT I/O whose function after reset is JTMS-SWDIO. |
| 47 | VCAP_2 | passive | Pin for the external capacitor of the internal 1.2 V regulator (VCAP_2). |
| 48 | VDD | power_in | Digital power supply pin. |
| 49 | PA14 | bidirectional | FT I/O whose function after reset is JTCK/SWCLK. |
| 50 | PA15 | bidirectional | FT I/O whose function after reset is JTDI; alternate functions include SPI3_NSS/I2S3_WS, TIM2_CH1_ETR and SPI1_NSS. |
| 51 | PC10 | bidirectional | FT I/O; alternate functions include SPI3_SCK/I2S3_CK, UART4_TX, SDIO_D2, DCMI_D8 and USART3_TX. |
| 52 | PC11 | bidirectional | FT I/O; alternate functions include UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX and I2S3ext_SD. |
| 53 | PC12 | bidirectional | FT I/O; alternate functions include UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI/I2S3_SD and USART3_CK. |
| 54 | PD2 | bidirectional | FT I/O; alternate functions include TIM3_ETR, UART5_RX, SDIO_CMD and DCMI_D11. |
| 55 | PB3 | bidirectional | FT I/O whose function after reset is JTDO/TRACESWO; alternate functions include SPI3_SCK/I2S3_CK, TIM2_CH2 and SPI1_SCK. |
| 56 | PB4 | bidirectional | FT I/O whose function after reset is NJTRST; alternate functions include SPI3_MISO, TIM3_CH1, SPI1_MISO and I2S3ext_SD. |
| 57 | PB5 | bidirectional | FT I/O; alternate functions include I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI and DCMI_D10. |
| 58 | PB6 | bidirectional | FT I/O; alternate functions include I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5 and USART1_TX. |
| 59 | PB7 | bidirectional | FT I/O; alternate functions include I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX and TIM4_CH2. |
| 60 | BOOT0 | input | Dedicated boot mode selection input pin (also VPP for Flash programming). |
| 61 | PB8 | bidirectional | FT I/O; alternate functions include TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL and CAN1_RX. |
| 62 | PB9 | bidirectional | FT I/O; alternate functions include SPI2_NSS/I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA and CAN1_TX. |
| 63 | VSS | power_in | Ground supply pin. |
| 64 | VDD | power_in | Digital power supply pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32F405RGT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32f405rgt6-etched.step/stm32f405rgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32f405rgt6.step/stm32f405rgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (185 pp, sha256
f83f1f3dca0b4e10, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).