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STM32F401VEH6

Public Made by Adom

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), UFBGA-100. Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f401veh6factory-2.0.0extractor-text
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Contents

README

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STM32F401VEH6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · UFBGA-100

STM32F401VEH6 from STMicroelectronics, in a UFBGA-100. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
B2 PE2 bidirectional 5 V-tolerant I/O (FT), floating input during and after reset; alternate functions SPI4_SCK, TRACECLK, EVENTOUT.
A1 PE3 bidirectional 5 V-tolerant I/O (FT), floating input during and after reset; alternate functions TRACED0, EVENTOUT.
B1 PE4 bidirectional 5 V-tolerant I/O (FT), floating input during and after reset; alternate functions SPI4_NSS, TRACED1, EVENTOUT.
C2 PE5 bidirectional 5 V-tolerant I/O (FT), floating input during and after reset; alternate functions SPI4_MISO, TIM9_CH1, TRACED2, EVENTOUT.
D2 PE6 bidirectional 5 V-tolerant I/O (FT), floating input during and after reset; alternate functions SPI4_MOSI, TIM9_CH2, TRACED3, EVENTOUT.
D3 VSS power_in Ground supply pin (VSS) listed in Table 8.
C4 VDD power_in Digital supply pin; 1.7 V to 3.6 V application supply and I/Os.
E2 VBAT power_in Backup-domain supply pin for the RTC; the features list gives VBAT consumption of 1 µA @25 °C for RTC operation.
C1 PC13 bidirectional 5 V-tolerant I/O (FT) supplied through the power switch, which sinks at most 3 mA, so output use is limited to 2 MHz with 30 pF and it must not source current (e.g. LED drive); main function after first backup-domain power-up is RTC-related (RTC_TAMP1, RTC_OUT, RTC_TS).
D1 PC14 bidirectional 5 V-tolerant I/O (FT, not in oscillator mode) supplied through the power switch (3 mA limit, output at most 2 MHz/30 pF); also OSC32_IN for the 32 kHz oscillator.
E1 PC15 bidirectional 5 V-tolerant I/O (FT, not in oscillator mode) supplied through the power switch (3 mA limit, output at most 2 MHz/30 pF); also OSC32_OUT for the 32 kHz oscillator.
F2 VSS power_in Ground supply pin (VSS) listed in Table 8.
G2 VDD power_in Digital supply pin; 1.7 V to 3.6 V application supply and I/Os.
F1 PH0 bidirectional I/O (FT, except when in oscillator mode) also used as OSC_IN for the 4-26 MHz HSE crystal oscillator.
G1 PH1 bidirectional I/O (FT, except when in oscillator mode) also used as OSC_OUT for the 4-26 MHz HSE crystal oscillator.
H2 NRST bidirectional Bidirectional reset pin with embedded weak pull-up resistor (Table 7).
H1 PC0 bidirectional 5 V-tolerant I/O (FT), floating input at reset; ADC1 input channel IN10, EVENTOUT.
J2 PC1 bidirectional 5 V-tolerant I/O (FT), floating input at reset; ADC1 input channel IN11, EVENTOUT.
J3 PC2 bidirectional 5 V-tolerant I/O (FT), floating input at reset; alternate functions SPI2_MISO, I2S2ext_SD, EVENTOUT; ADC1 input channel IN12.
K2 PC3 bidirectional 5 V-tolerant I/O (FT), floating input at reset; alternate functions SPI2_MOSI/I2S2_SD, EVENTOUT; ADC1 input channel IN13.
J1 VSSA power_in Analog ground pin for the ADC and analog blocks.
K1 VREF- power_in ADC negative reference voltage pin.
L1 VREF+ power_in ADC positive reference voltage input; may be left unconnected from VDDA or tied to VDDA (see Figures 42 and 43).
M1 VDDA power_in Analog supply pin for the ADC and analog blocks.
L2 PA0 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_CTS, TIM2_CH1/TIM2_ETR, TIM5_CH1, EVENTOUT; ADC1 IN0 and WKUP. If BYPASS_REG is tied to VDD, PA0 is used as an internal reset (active low).
M2 PA1 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_RTS, TIM2_CH2, TIM5_CH2, EVENTOUT; ADC1 input channel IN1.
K3 PA2 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_TX, TIM2_CH3, TIM5_CH3, TIM9_CH1, EVENTOUT; ADC1 input channel IN2.
L3 PA3 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_RX, TIM2_CH4, TIM5_CH4, TIM9_CH2, EVENTOUT; ADC1 input channel IN3.
E3 BYPASS_REG input 5 V-tolerant regulator bypass control input (FT); when tied to VDD the device operates in regulator-off/internal reset ON mode (footnote 5).
M3 PA4 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT; ADC1 input channel IN4.
K4 PA5 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI1_SCK, TIM2_CH1/TIM2_ETR, EVENTOUT; ADC1 input channel IN5.
L4 PA6 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI1_MISO, TIM1_BKIN, TIM3_CH1, EVENTOUT; ADC1 input channel IN6.
M4 PA7 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI1_MOSI, TIM1_CH1N, TIM3_CH2, EVENTOUT; ADC1 input channel IN7.
K5 PC4 bidirectional 5 V-tolerant I/O (FT), floating input at reset; EVENTOUT; ADC1 input channel IN14.
L5 PC5 bidirectional 5 V-tolerant I/O (FT), floating input at reset; EVENTOUT; ADC1 input channel IN15.
M5 PB0 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH2N, TIM3_CH3, EVENTOUT; ADC1 input channel IN8.
M6 PB1 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH3N, TIM3_CH4, EVENTOUT; ADC1 input channel IN9.
L6 PB2 bidirectional 5 V-tolerant I/O (FT); EVENTOUT; also BOOT1 additional function.
M7 PE7 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_ETR, EVENTOUT.
L7 PE8 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH1N, EVENTOUT.
M8 PE9 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH1, EVENTOUT.
L8 PE10 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_CH2N, EVENTOUT.
M9 PE11 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI4_NSS, TIM1_CH2, EVENTOUT.
L9 PE12 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI4_SCK, TIM1_CH3N, EVENTOUT.
M10 PE13 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI4_MISO, TIM1_CH3, EVENTOUT.
M11 PE14 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI4_MOSI, TIM1_CH4, EVENTOUT.
M12 PE15 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM1_BKIN, EVENTOUT.
L10 PB10 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_SCK/I2S2_CK, I2C2_SCL, TIM2_CH3, EVENTOUT.
K9 PB11 bidirectional 5 V-tolerant I/O (FT); EVENTOUT.
L11 VCAP1 power_in Internal regulator decoupling pin requiring external capacitors (see Section 6.3.2, VCAP1/VCAP2 external capacitors).
F12 VSS power_in Ground supply pin (VSS) listed in Table 8.
G12 VDD power_in Digital supply pin; 1.7 V to 3.6 V application supply and I/Os.
L12 PB12 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_NSS/I2S2_WS, I2C2_SMBA, TIM1_BKIN, EVENTOUT.
K12 PB13 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_SCK/I2S2_CK, TIM1_CH1N, EVENTOUT.
K11 PB14 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_MISO, I2S2ext_SD, TIM1_CH2N, EVENTOUT.
K10 PB15 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_MOSI/I2S2_SD, TIM1_CH3N, EVENTOUT; RTC_REFIN.
K8 PD9 bidirectional 5 V-tolerant I/O (FT); EVENTOUT.
J12 PD10 bidirectional 5 V-tolerant I/O (FT); EVENTOUT.
J11 PD11 bidirectional 5 V-tolerant I/O (FT); EVENTOUT.
J10 PD12 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM4_CH1, EVENTOUT.
H12 PD13 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM4_CH2, EVENTOUT.
H11 PD14 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM4_CH3, EVENTOUT.
H10 PD15 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM4_CH4, EVENTOUT.
E12 PC6 bidirectional 5 V-tolerant I/O (FT); alternate functions I2S2_MCK, USART6_TX, TIM3_CH1, SDIO_D6, EVENTOUT.
E11 PC7 bidirectional 5 V-tolerant I/O (FT); alternate functions I2S3_MCK, USART6_RX, TIM3_CH2, SDIO_D7, EVENTOUT.
E10 PC8 bidirectional 5 V-tolerant I/O (FT); alternate functions USART6_CK, TIM3_CH3, SDIO_D0, EVENTOUT.
D12 PC9 bidirectional 5 V-tolerant I/O (FT); alternate functions I2S_CKIN, I2C3_SDA, TIM3_CH4, SDIO_D1, MCO_2, EVENTOUT.
D11 PA8 bidirectional 5 V-tolerant I/O (FT); alternate functions I2C3_SCL, USART1_CK, TIM1_CH1, OTG_FS_SOF, MCO_1, EVENTOUT.
D10 PA9 bidirectional 5 V-tolerant I/O (FT); alternate functions I2C3_SMBA, USART1_TX, TIM1_CH2, EVENTOUT; OTG_FS_VBUS.
C12 PA10 bidirectional 5 V-tolerant I/O (FT); alternate functions USART1_RX, TIM1_CH3, OTG_FS_ID, EVENTOUT.
B12 PA11 bidirectional 5 V-tolerant I/O (FT); alternate functions USART1_CTS, USART6_TX, TIM1_CH4, OTG_FS_DM, EVENTOUT.
A12 PA12 bidirectional 5 V-tolerant I/O (FT); alternate functions USART1_RTS, USART6_RX, TIM1_ETR, OTG_FS_DP, EVENTOUT.
A11 PA13 bidirectional 5 V-tolerant I/O (FT); JTMS-SWDIO debug function (SWD data I/O), EVENTOUT.
C11 VCAP2 power_in Internal regulator decoupling pin requiring external capacitors (see Section 6.3.2, VCAP1/VCAP2 external capacitors).
F11 VSS power_in Ground supply pin (VSS) listed in Table 8.
G11 VDD power_in Digital supply pin; 1.7 V to 3.6 V application supply and I/Os.
A10 PA14 bidirectional 5 V-tolerant I/O (FT); JTCK-SWCLK debug function (SWD clock), EVENTOUT.
A9 PA15 bidirectional 5 V-tolerant I/O (FT); JTDI debug function, alternate functions SPI1_NSS, SPI3_NSS/I2S3_WS, TIM2_CH1/TIM2_ETR, EVENTOUT.
B11 PC10 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI3_SCK/I2S3_CK, SDIO_D2, EVENTOUT.
C10 PC11 bidirectional 5 V-tolerant I/O (FT); alternate functions I2S3ext_SD, SPI3_MISO, SDIO_D3, EVENTOUT.
B10 PC12 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI3_MOSI/I2S3_SD, SDIO_CK, EVENTOUT.
C9 PD0 bidirectional 5 V-tolerant I/O (FT); EVENTOUT.
B9 PD1 bidirectional 5 V-tolerant I/O (FT); EVENTOUT.
C8 PD2 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM3_ETR, SDIO_CMD, EVENTOUT.
B8 PD3 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_SCK/I2S2_CK, USART2_CTS, EVENTOUT.
B7 PD4 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_RTS, EVENTOUT.
A6 PD5 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_TX, EVENTOUT.
B6 PD6 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI3_MOSI/I2S3_SD, USART2_RX, EVENTOUT.
A5 PD7 bidirectional 5 V-tolerant I/O (FT); alternate functions USART2_CK, EVENTOUT.
A8 PB3 bidirectional 5 V-tolerant I/O (FT); JTDO-SWO debug function, alternate functions SPI1_SCK, SPI3_SCK/I2S3_CK, I2C2_SDA, TIM2_CH2, EVENTOUT.
A7 PB4 bidirectional 5 V-tolerant I/O (FT); NJTRST debug function, alternate functions SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, TIM3_CH1, EVENTOUT.
C5 PB5 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI1_MOSI, SPI3_MOSI/I2S3_SD, I2C1_SMBA, TIM3_CH2, EVENTOUT.
B5 PB6 bidirectional 5 V-tolerant I/O (FT); alternate functions I2C1_SCL, USART1_TX, TIM4_CH1, EVENTOUT.
B4 PB7 bidirectional 5 V-tolerant I/O (FT); alternate functions I2C1_SDA, USART1_RX, TIM4_CH2, EVENTOUT.
A4 BOOT0 input Dedicated BOOT0 boot-mode selection input (B); also listed with the VPP additional function.
A3 PB8 bidirectional 5 V-tolerant I/O (FT); alternate functions I2C1_SCL, TIM4_CH3, TIM10_CH1, SDIO_D4, EVENTOUT.
B3 PB9 bidirectional 5 V-tolerant I/O (FT); alternate functions SPI2_NSS/I2S2_WS, I2C1_SDA, TIM4_CH4, TIM11_CH1, SDIO_D5, EVENTOUT.
C3 PE0 bidirectional 5 V-tolerant I/O (FT); alternate functions TIM4_ETR, EVENTOUT.
A2 PE1 bidirectional 5 V-tolerant I/O (FT); EVENTOUT.
H3 PDR_ON input 5 V-tolerant power-down reset control input (FT), used with internal reset OFF (see Figure 6, PDR_ON control with internal reset OFF).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package UFBGA-100
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F401VEH6
  • Footprint: Package_BGA:UFBGA-100_7x7mm_Layout12x12_P0.5mm
  • 3D model: UFBGA-100 (KiCad packages3D, STEP)
  • 3D model files: stm32f401veh6-etched.step / stm32f401veh6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f401veh6.step / stm32f401veh6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (135 pp, sha256 7daad2163948dcbe, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF