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STM32F401VCT6

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.

componentembedded processors & controllersstm32f401vct6factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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STM32F401VCT6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

STM32F401VCT6 from STMicroelectronics, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO port E pin 2 with alternate functions including SPI4 clock, Trace clock, and event output.
2 PE3 bidirectional GPIO port E pin 3 with alternate functions including Trace data 0 and event output.
3 PE4 bidirectional GPIO port E pin 4 with alternate functions including SPI4 chip select, Trace data 1, and event output.
4 PE5 bidirectional GPIO port E pin 5 with alternate functions including SPI4 MISO, TIM9 channel 1, Trace data 2, and event output.
5 PE6 bidirectional GPIO port E pin 6 with alternate functions including SPI4 MOSI, TIM9 channel 2, Trace data 3, and event output.
6 VBAT power_in Backup domain power supply pin accepting 1.65 to 3.6 V for RTC and backup registers.
7 PC13 bidirectional GPIO port C pin 13 with 3 mA maximum output current and alternate functions for RTC tamper detection, RTC output, and RTC timestamp.
8 PC14-OSC32_IN bidirectional GPIO port C pin 14 serving as 32 kHz oscillator input with 2 mA maximum output current and event output function.
9 PC15-OSC32_OUT bidirectional GPIO port C pin 15 serving as 32 kHz oscillator output with 2 mA maximum output current and event output function.
10 VSS power_in Ground return path for main power supply.
11 VDD power_in Main power supply pin accepting 1.7 to 3.6 V for device core and I/O logic.
12 PH0-OSC_IN bidirectional GPIO port H pin 0 serving as main oscillator input with event output function.
13 PH1-OSC_OUT bidirectional GPIO port H pin 1 serving as main oscillator output with event output function.
14 NRST bidirectional Active-low reset input pin with embedded weak pull-up resistor, glitch filter, and event output function.
15 PC0 bidirectional GPIO port C pin 0 serving as ADC channel 10 input with event output function.
16 PC1 bidirectional GPIO port C pin 1 serving as ADC channel 11 input with event output function.
17 PC2 bidirectional GPIO port C pin 2 with alternate functions including SPI2 MISO, I2S2 extension SD, ADC channel 12, and event output.
18 PC3 bidirectional GPIO port C pin 3 with alternate functions including SPI2/I2S2 MOSI, ADC channel 13, and event output.
19 VDD power_in Main power supply pin accepting 1.7 to 3.6 V for device core and I/O logic.
20 VSSA/VREF- power_in Analog ground return path and negative ADC reference voltage pin.
21 VREF+ power_in Positive ADC reference voltage pin accepting 1.7 to 3.6 V.
22 VDDA power_in Analog power supply pin accepting 1.7 to 3.6 V for ADC, PLL, and internal oscillators.
23 PA0 bidirectional GPIO port A pin 0 serving as ADC channel 0 and wakeup source from Standby mode, with alternate functions for USART2, TIM2/5, and event output.
24 PA1 bidirectional GPIO port A pin 1 with alternate functions including USART2 RTS, TIM2/5 channels, and event output, with ADC channel 1 input.
25 PA2 bidirectional GPIO port A pin 2 with alternate functions including USART2 TX, TIM2/5/9 channels, and event output, with ADC channel 2 input.
26 PA3 bidirectional GPIO port A pin 3 with alternate functions including USART2 RX, TIM2/5/9 channels, and event output, with ADC channel 3 input.
27 VSS power_in Ground return path for main power supply.
28 VDD power_in Main power supply pin accepting 1.7 to 3.6 V for device core and I/O logic.
29 PA4 bidirectional GPIO port A pin 4 with alternate functions including SPI1/3 chip select, USART2 clock, and event output, with ADC channel 4 input.
30 PA5 bidirectional GPIO port A pin 5 with alternate functions including SPI1 clock and TIM2 channel 1, with ADC channel 5 input.
31 PA6 bidirectional GPIO port A pin 6 with alternate functions including SPI1 MISO, TIM1 break input, and TIM3 channel 1, with ADC channel 6 input.
32 PA7 bidirectional GPIO port A pin 7 with alternate functions including SPI1 MOSI, TIM1 channel 1N, and TIM3 channel 2, with ADC channel 7 input.
33 PC4 bidirectional GPIO port C pin 4 with event output function serving as ADC channel 14 input.
34 PC5 bidirectional GPIO port C pin 5 with event output function serving as ADC channel 15 input.
35 PB0 bidirectional GPIO port B pin 0 with alternate functions including TIM1/3 channels and event output, with ADC channel 8 input.
36 PB1 bidirectional GPIO port B pin 1 with alternate functions including TIM1/3 channels and event output, with ADC channel 9 input.
37 PB2 bidirectional GPIO port B pin 2 with event output function and boot mode selection as BOOT1.
38 PE7 bidirectional GPIO port E pin 7 with alternate functions including TIM1 external trigger and event output.
39 PE8 bidirectional GPIO port E pin 8 with alternate functions including TIM1 channel 1N and event output.
40 PE9 bidirectional GPIO port E pin 9 with alternate functions including TIM1 channel 1 and event output.
41 PE10 bidirectional GPIO port E pin 10 with alternate functions including TIM1 channel 2N and event output.
42 PE11 bidirectional GPIO port E pin 11 with alternate functions including SPI4 chip select, TIM1 channel 2, and event output.
43 PE12 bidirectional GPIO port E pin 12 with alternate functions including SPI4 clock, TIM1 channel 3N, and event output.
44 PE13 bidirectional GPIO port E pin 13 with alternate functions including SPI4 MISO, TIM1 channel 3, and event output.
45 PE14 bidirectional GPIO port E pin 14 with alternate functions including SPI4 MOSI, TIM1 channel 4, and event output.
46 PE15 bidirectional GPIO port E pin 15 with alternate functions including TIM1 break input and event output.
47 PB10 bidirectional GPIO port B pin 10 with alternate functions including SPI2/I2S2 clock, I2C2 SCL, and TIM2 channel 3.
48 VCAP_1 passive Voltage regulator output capacitor connection pin requiring external 2.2 µF ceramic capacitor for power supply stabilization.
49 VSS power_in Ground return path for main power supply.
50 VDD power_in Main power supply pin accepting 1.7 to 3.6 V for device core and I/O logic.
51 PB12 bidirectional GPIO port B pin 12 with alternate functions including SPI2/I2S2 chip select, I2C2 SMB alert, and TIM1 break input.
52 PB13 bidirectional GPIO port B pin 13 with alternate functions including SPI2/I2S2 clock and TIM1 channel 1N.
53 PB14 bidirectional GPIO port B pin 14 with alternate functions including SPI2 MISO, I2S2 extension SD, and TIM1 channel 2N.
54 PB15 bidirectional GPIO port B pin 15 with alternate functions including SPI2/I2S2 MOSI and TIM1 channel 3N, with RTC reference input.
55 PD8 bidirectional GPIO port D pin 8 with event output function.
56 PD9 bidirectional GPIO port D pin 9 with event output function.
57 PD10 bidirectional GPIO port D pin 10 with event output function.
58 PD11 bidirectional GPIO port D pin 11 with event output function.
59 PD12 bidirectional GPIO port D pin 12 with alternate functions including TIM4 channel 1 and event output.
60 PD13 bidirectional GPIO port D pin 13 with alternate functions including TIM4 channel 2 and event output.
61 PD14 bidirectional GPIO port D pin 14 with alternate functions including TIM4 channel 3 and event output.
62 PD15 bidirectional GPIO port D pin 15 with alternate functions including TIM4 channel 4 and event output.
63 PC6 bidirectional GPIO port C pin 6 with alternate functions including I2S2 master clock, USART6 TX, TIM3 channel 1, and SDIO data 6.
64 PC7 bidirectional GPIO port C pin 7 with alternate functions including I2S3 master clock, USART6 RX, TIM3 channel 2, and SDIO data 7.
65 PC8 bidirectional GPIO port C pin 8 with alternate functions including USART6 clock, TIM3 channel 3, and SDIO data 0.
66 PC9 bidirectional GPIO port C pin 9 with alternate functions including I2S clock input, I2C3 SDA, TIM3 channel 4, SDIO data 1, and MCO2 output.
67 PA8 bidirectional GPIO port A pin 8 with alternate functions including I2C3 SCL, USART1 clock, TIM1 channel 1, USB OTG frame output, and MCO1 clock output.
68 PA9 bidirectional GPIO port A pin 9 with alternate functions including I2C3 SMB alert, USART1 TX, TIM1 channel 2, and USB OTG VBUS sensing.
69 PA10 bidirectional GPIO port A pin 10 with alternate functions including USART1 RX, TIM1 channel 3, and USB OTG ID pin.
70 PA11 bidirectional GPIO port A pin 11 with alternate functions including USART1 CTS, USART6 TX, TIM1 channel 4, and USB OTG D- data line.
71 PA12 bidirectional GPIO port A pin 12 with alternate functions including USART1 RTS, USART6 RX, TIM1 external trigger, and USB OTG D+ data line.
72 PA13 bidirectional GPIO port A pin 13 serving as JTAG TMS and serial wire debug I/O with event output function.
73 VCAP_2 passive Voltage regulator output capacitor connection pin (LQFP100 package only) requiring external 2.2 µF ceramic capacitor for power supply stabilization.
74 VSS power_in Ground return path for main power supply.
75 VDD power_in Main power supply pin accepting 1.7 to 3.6 V for device core and I/O logic.
76 PA14 bidirectional GPIO port A pin 14 serving as JTAG TCK and serial wire debug clock with event output function.
77 PA15 bidirectional GPIO port A pin 15 serving as JTAG TDI with alternate functions including SPI1/3 chip select, I2S3 word select, TIM2 channel 1, and event output.
78 PC10 bidirectional GPIO port C pin 10 with alternate functions including SPI3/I2S3 clock and SDIO data 2.
79 PC11 bidirectional GPIO port C pin 11 with alternate functions including I2S3 extension SD, SPI3 MISO, and SDIO data 3.
80 PC12 bidirectional GPIO port C pin 12 with alternate functions including SPI3/I2S3 MOSI and SDIO clock.
81 PD0 bidirectional GPIO port D pin 0 with event output function.
82 PD1 bidirectional GPIO port D pin 1 with event output function.
83 PD2 bidirectional GPIO port D pin 2 with alternate functions including TIM3 external trigger and SDIO command line.
84 PD3 bidirectional GPIO port D pin 3 with alternate functions including SPI2/I2S2 clock and USART2 CTS.
85 PD4 bidirectional GPIO port D pin 4 with alternate functions including USART2 RTS.
86 PD5 bidirectional GPIO port D pin 5 with alternate functions including USART2 TX.
87 PD6 bidirectional GPIO port D pin 6 with alternate functions including SPI3/I2S3 MOSI and USART2 RX.
88 PD7 bidirectional GPIO port D pin 7 with alternate functions including USART2 clock.
89 PB3 bidirectional GPIO port B pin 3 serving as JTAG TDO and serial wire debug output with alternate functions for SPI1/3 clock, I2C2 SDA, TIM2 channel 2, and event output.
90 PB4 bidirectional GPIO port B pin 4 serving as JTAG TRST with alternate functions including SPI1 MISO, SPI3 MISO, I2S3 extension SD, I2C3 SDA, TIM3 channel 1, and event output.
91 PB5 bidirectional GPIO port B pin 5 with alternate functions including SPI1 MOSI, SPI3/I2S3 MOSI, I2C1 SMB alert, TIM3 channel 2, and event output.
92 PB6 bidirectional GPIO port B pin 6 with alternate functions including I2C1 SCL, USART1 TX, TIM4 channel 1, and event output.
93 PB7 bidirectional GPIO port B pin 7 with alternate functions including I2C1 SDA, USART1 RX, TIM4 channel 2, and event output.
94 BOOT0 input Boot mode selection pin (0 = boot from Flash, 1 = boot from system memory) with 9 V absolute maximum input voltage.
95 PB8 bidirectional GPIO port B pin 8 with alternate functions including I2C1 SCL, TIM4 channel 3, TIM10 channel 1, and SDIO data 4.
96 PB9 bidirectional GPIO port B pin 9 with alternate functions including SPI2/I2S2 chip select, I2C1 SDA, TIM4 channel 4, TIM11 channel 1, and SDIO data 5.
97 PE0 bidirectional GPIO port E pin 0 with alternate functions including TIM4 external trigger and event output.
98 PE1 bidirectional GPIO port E pin 1 with alternate functions including TIM1 channel 2N and event output.
99 VSS power_in Ground return path for main power supply.
100 VDD power_in Main power supply pin accepting 1.7 to 3.6 V for device core and I/O logic.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: STM32F401VCT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: stm32f401vct6-etched.step / stm32f401vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm32f401vct6.step / stm32f401vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (139 pp, sha256 c38f92aa9d66e8cb, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF